Integral delay correctly set

diff --git a/ADC/sim/tb_adcprocessor_cfd.vhd b/ADC/sim/tb_adcprocessor_cfd.vhd
index fb51cffa03fa4dd1eff4a80547ab574081b0c89a..5eef971ef556b6640aab2c6034e5d99cc15953aa 100644 (file)
--- a/ADC/sim/tb_adcprocessor_cfd.vhd
+++ b/ADC/sim/tb_adcprocessor_cfd.vhd
@@ -40,6 +40,8 @@ begin
   config.CFDDelay <= to_unsigned(2, 5);
   config.CFDMult <= to_unsigned(2, 4);
   config.CFDMultDly <= to_unsigned(3, 4);
+
+  config.IntegrateWindow <= to_unsigned(60, 8);
    
   config.CheckWord1       <= (others => '0');
   config.CheckWord2       <= (others => '0');

diff --git a/ADC/source/adc_processor_cfd_ch.vhd b/ADC/source/adc_processor_cfd_ch.vhd
index 524b9a7fed2d9dad2b453df576fda3ffa172ebaf..f5b7c4774203ab6ca8736d3c27ce74c06337907f 100644 (file)
--- a/ADC/source/adc_processor_cfd_ch.vhd
+++ b/ADC/source/adc_processor_cfd_ch.vhd
@@ -30,7 +30,7 @@ architecture arch of adc_processor_cfd_ch is
   constant RESOLUTION_BASEAVG : integer := RESOLUTION + 2 ** CONF.BaselineAverage'length - 1;
   constant LENGTH_BASEDLY     : integer := 32; -- longer than typical pulses?
   constant LENGTH_CFDDLY      : integer := 2 ** CONF.CFDDelay'length;
-  constant LENGTH_INTDLY      : integer := 2;  -- must match CFD/zeroX calculation chain
+  constant LENGTH_INTDLY      : integer := 3;  -- must match CFD/zeroX calculation chain
 
   type unsigned_in_thresh_t is record
     value  : unsigned(RESOLUTION - 1 downto 0);
@@ -74,7 +74,7 @@ architecture arch of adc_processor_cfd_ch is
   signal delay_cfd_out : signed(RESOLUTION_SUB - 1 downto 0) := (others => '0');
 
   signal prod, prod_invert : product_thresh_t := product_thresh_t_INIT;
-  signal prod_delay        : signed(RESOLUTION_PROD - 1 downto 0);
+  signal prod_delay        : signed(RESOLUTION_PROD - 1 downto 0) := (others => '0');
 
   signal cfd                               : cfd_thresh_t                        := cfd_thresh_t_INIT; -- the bipolar signal
   signal cfd_prev, cfd_prev_save, cfd_save : signed(RESOLUTION_CFD - 1 downto 0) := (others => '0');