signal rst_n_tx : std_logic;
signal finished_reset_rx : std_logic;
signal finished_reset_rx_q : std_logic;
+signal finished_reset_rx_rxi : std_logic;
signal finished_reset_tx : std_logic;
signal finished_reset_tx_q : std_logic;
LINK_RESET_FIN_RX : signal_sync port map(RESET => '0',CLK0 => CLK_REF, CLK1 => CLK_SYS,
D_IN(0) => finished_reset_rx,
D_OUT(0) => finished_reset_rx_q);
+LINK_RESET_FIN_RX_RXI : signal_sync port map(RESET => '0',CLK0 => CLK_REF, CLK1 => CLK_RXI,
+ D_IN(0) => finished_reset_rx,
+ D_OUT(0) => finished_reset_rx_rxi);
START_TIMER_PROC : process( CLK_SYS )
begin
SEND_LINK_RESET_OUT => send_link_reset_i,
MAKE_RESET_OUT => make_link_reset_i,
RX_ALLOW_IN => rx_allow,
- RX_RESET_FINISHED => finished_reset_rx,
+ RX_RESET_FINISHED => finished_reset_rx_rxi,
GOT_LINK_READY => got_link_ready_i,
DEBUG_OUT => DEBUG_RX_CONTROL,