signal wr_fsm_debug : std_logic_vector(3 downto 0);
signal wr_fsm_debug_r : std_logic_vector(3 downto 0);
signal history_wr_fsm : std_logic_vector(31 downto 0) := (others => '0');
- signal any_hit : std_logic := '0';
+-- signal any_hit : std_logic := '0';
signal data_format_i : std_logic_vector(3 downto 0);
begin -- behavioral
hit_in_i(i+1) <= HIT_IN(i+1); --sync_q(i*3+2);
end generate HitSignalSync;
- any_hit <= or_all(hit_in_i);
+-- any_hit <= or_all(hit_in_i);
CheckHitStatus : process (CLK_100) is
begin
--Bit 0/1 input, serial link RX active
--Bit 2/3 output, serial link TX active
--Connection to ADA AddOn
- SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only
+-- SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only
INP : in std_logic_vector(63 downto 0);
--DAC
DAC_IN_L_SDI : in std_logic;
LED_ORANGE : out std_logic;
LED_RED : out std_logic;
LED_YELLOW : out std_logic;
- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
+-- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
--Test Connectors
TEST_LINE : out std_logic_vector(15 downto 0)
);
attribute syn_useioff of FPGA5_COMM : signal is true;
attribute syn_useioff of TEST_LINE : signal is true;
attribute syn_useioff of INP : signal is false;
- attribute syn_useioff of SPARE_LINE : signal is true;
+-- attribute syn_useioff of SPARE_LINE : signal is true;
attribute syn_useioff of DAC_IN_L_SDI : signal is true;
attribute syn_useioff of DAC_OUT_L_SDO : signal is true;
attribute syn_useioff of DAC_OUT_L_SCK : signal is true;
--Slow Control channel
signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal ctrlbus_rx, bustdc_rx, bustools_rx, bus_master_out : CTRLBUS_RX;
- signal ctrlbus_tx, bustdc_tx, bustools_tx, bus_master_in : CTRLBUS_TX;
+ signal ctrlbus_rx, bustdc_rx, bustools_rx, bus_master_out, bustrigger_rx : CTRLBUS_RX;
+ signal ctrlbus_tx, bustdc_tx, bustools_tx, bus_master_in, bustrigger_tx : CTRLBUS_TX;
signal bus_master_active : std_logic;
signal timer : TIMERS;
signal lcd_data : std_logic_vector(511 downto 0);
attribute nopad : string;
attribute nopad of serdes_i : signal is "true";
-
+ signal triggerlogic_out : std_logic_vector(7 downto 0);
--TDC
signal hit_in_i : std_logic_vector(64 downto 1);
MED_READ_IN => '1',
REFCLK2CORE_OUT => open,
--SFP Connection
--- SD_RXD_P_IN => SERDES_INT_RX(2),
--- SD_RXD_N_IN => SERDES_INT_RX(3),
--- SD_TXD_P_OUT => SERDES_INT_TX(2),
--- SD_TXD_N_OUT => SERDES_INT_TX(3),
--- SD_REFCLK_P_IN => open,
--- SD_REFCLK_N_IN => open,
SD_PRSNT_N_IN => FPGA5_COMM(0),
SD_LOS_IN => FPGA5_COMM(0),
SD_TXDIS_OUT => FPGA5_COMM(2),
ONEWIRE_INOUT => TEMPSENS,
--Timing registers
- TIMERS_OUT => timer
+ TIMERS_OUT => timer
);
timing_trg_received_i <= TRIGGER_LEFT; --TRIGGER_RIGHT; --
---------------------------------------------------------------------------
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
- PORT_NUMBER => 2,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"c000", others => x"0000"),
- PORT_ADDR_MASK => (0 => 12, 1 => 12, others => 0),
+ PORT_NUMBER => 3,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"c000", 2 => x"e000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 12, 2 => 12, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
BUS_RX(1) => bustdc_rx, --TDC config
+ BUS_RX(2) => bustrigger_rx,
BUS_TX(0) => bustools_tx,
BUS_TX(1) => bustdc_tx,
+ BUS_TX(2) => bustrigger_tx,
STAT_DEBUG => open
);
DEBUG_OUT => open
);
+
+THE_TRIGGER_LOGIC : entity work.trigger_logic
+ generic map(
+ INPUTS => 24,
+ OUTPUTS => 8
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+
+ --Slowcontrol
+ BUS_RX => bustrigger_rx,
+ BUS_TX => bustrigger_tx,
+
+ --Inputs and Outputs
+ INPUT => hit_in_i(24 downto 1),
+ OUTPUT => triggerlogic_out(7 downto 0)
+ );
+ FPGA5_COMM(10 downto 7) <= trig_gen_out_i or triggerlogic_out(3 downto 0);
+
+
+ --FPGA5_COMM(10 downto 7) <= trig_gen_out_i;
+
+
---------------------------------------------------------------------------
-- Feature I/O
---------------------------------------------------------------------------
- FPGA5_COMM(10 downto 7) <= trig_gen_out_i;
FPGA5_COMM(6 downto 3) <= (others => 'Z');
FPGA5_COMM(1) <= 'Z';
feature_outputs_i(2) <= spi_cs(4);
feature_outputs_i(3) <= spi_mosi(4);
feature_outputs_i(4) <= spi_clk(4);
- spi_miso(4) <= TEST_LINE(5);
+-- spi_miso(4) <= TEST_LINE(5);
feature_outputs_i(7) <= lcd_out(4); --lcd_cs
feature_outputs_i(8) <= lcd_out(0); --lcd_rst
feature_outputs_i(9) <= lcd_out(3); --lcd_dc
-- Test Connector - Logic Analyser
---------------------------------------------------------------------------
- TEST_LINE <= logic_analyser_i;
+-- TEST_LINE <= logic_analyser_i;
+ TEST_LINE(7 downto 0) <= triggerlogic_out;
-------------------------------------------------------------------------------
-- TDC
CLK_PCLK_LEFT : in std_logic; --Clock Manager 3
CLK_PCLK_RIGHT : in std_logic; --Clock Manager 1
--CLK_PCLK_RIGHT is the only clock with external termination !?
- CLK_EXTERNAL : in std_logic; --Clock Manager 9
+-- CLK_EXTERNAL : in std_logic; --Clock Manager 9
--Trigger
-- TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
--Serdes
- CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 0, not used
- SERDES_TX : out std_logic_vector(3 downto 2);
- SERDES_RX : in std_logic_vector(3 downto 2);
+-- CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 0, not used
+-- SERDES_TX : out std_logic_vector(3 downto 2);
+-- SERDES_RX : in std_logic_vector(3 downto 2);
FPGA5_COMM : inout std_logic_vector(11 downto 0);
--Bit 0/1 input, serial link RX active
end entity;
architecture trb3_periph_gpin_arch of trb3_periph_gpin is
- --Constants
- constant REGIO_NUM_STAT_REGS : integer := 0;
- constant REGIO_NUM_CTRL_REGS : integer := 2;
-
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
--Clock / Reset
signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
- signal clk_cal : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator
+ signal clk_20 : std_logic; --clock for calibration at 20 MHz, via PLL
signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
signal clear_i : std_logic;
signal reset_i : std_logic;
signal GSR_N : std_logic;
+ signal osc_int : std_logic;
attribute syn_keep of GSR_N : signal is true;
attribute syn_preserve of GSR_N : signal is true;
- signal rx_clock_100 : std_logic;
- signal rx_clock_200 : std_logic;
- signal time_counter : unsigned(31 downto 0);
- --Media Interface
- signal med_stat_op : std_logic_vector (1*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0);
- signal med_data_out : std_logic_vector (1*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
- signal med_dataready_out : std_logic;
- signal med_read_out : std_logic;
- signal med_data_in : std_logic_vector (1*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);
- signal med_dataready_in : std_logic;
- signal med_read_in : std_logic;
+ --Media Interface
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+ signal med2int : med2int_array_t(0 to 0);
+ signal int2med : int2med_array_t(0 to 0);
+
--LVL1 channel
- signal timing_trg_received_i : std_logic;
+ signal timing_trg_received_i : std_logic;
--READOUT
signal readout_rx : READOUT_RX;
signal readout_tx : readout_tx_array_t(0 to 0);
--Slow Control channel
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal timer : TIMERS;
-
- --RegIO
- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-
- --Flash
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(8 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_dataready_out : std_logic;
- signal spimem_no_more_data_out : std_logic;
- signal spimem_unknown_addr_out : std_logic;
- signal spimem_write_ack_out : std_logic;
-
- signal spi_bram_addr : std_logic_vector(7 downto 0);
- signal spi_bram_wr_d : std_logic_vector(7 downto 0);
- signal spi_bram_rd_d : std_logic_vector(7 downto 0);
- signal spi_bram_we : std_logic;
-
- signal sci1_ack : std_logic;
- signal sci1_write : std_logic;
- signal sci1_read : std_logic;
- signal sci1_data_in : std_logic_vector(7 downto 0);
- signal sci1_data_out : std_logic_vector(7 downto 0);
- signal sci1_addr : std_logic_vector(8 downto 0);
-
- signal trig_out : std_logic_vector(3 downto 0);
- signal trig_din : std_logic_vector(31 downto 0);
- signal trig_dout : std_logic_vector(31 downto 0);
- signal trig_write : std_logic := '0';
- signal trig_read : std_logic := '0';
- signal trig_ack : std_logic := '0';
- signal trig_nack : std_logic := '0';
- signal trig_addr : std_logic_vector(15 downto 0) := (others => '0');
-
- signal stat_out : std_logic_vector(3 downto 0);
- signal stat_din : std_logic_vector(31 downto 0);
- signal stat_dout : std_logic_vector(31 downto 0);
- signal stat_write : std_logic := '0';
- signal stat_read : std_logic := '0';
- signal stat_ack : std_logic := '0';
- signal stat_nack : std_logic := '0';
- signal stat_addr : std_logic_vector(15 downto 0) := (others => '0');
-
- signal sed_error : std_logic;
- signal bussed_rx, bustdc_rx : CTRLBUS_RX;
- signal bussed_tx, bustdc_tx : CTRLBUS_TX;
+
+ signal ctrlbus_rx, bustdc_rx, bustools_rx, bus_master_out : CTRLBUS_RX;
+ signal ctrlbus_tx, bustdc_tx, bustools_tx, bus_master_in : CTRLBUS_TX;
+ signal bus_master_active : std_logic;
+ signal timer : TIMERS;
+ signal lcd_data : std_logic_vector(511 downto 0);
+ signal lcd_out : std_logic_vector(4 downto 0);
+ signal feature_outputs_i : std_logic_vector(15 downto 0);
+ signal spi_cs, spi_mosi, spi_miso, spi_clk, spi_clr : std_logic_vector(15 downto 0);
+ signal uart_rx, uart_tx, debug_rx, debug_tx : std_logic;
+ signal trig_gen_out_i : std_logic_vector(3 downto 0);
+ signal sed_error_i : std_logic;
+ signal serdes_i : std_logic_vector(3 downto 0);
+ attribute nopad : string;
+ attribute nopad of serdes_i : signal is "true";
+
+
--TDC
- signal hit_in_i : std_logic_vector(48 downto 1);
+ signal hit_in_i : std_logic_vector(24 downto 1);
signal logic_analyser_i : std_logic_vector(15 downto 0);
begin
SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
+ TRB_RESET_IN => med2int(0).stat_op(13), -- TRBnet reset signal (SYSCLK)
CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
DEBUG_OUT => open
pll_calibration : entity work.pll_in125_out33
port map (
CLK => CLK_GPLL_LEFT,
- CLKOP => clk_cal,
+ CLKOP => osc_int,
LOCK => open);
---------------------------------------------------------------------------
CLEAR => clear_i,
CLK_EN => '1',
--Internal Connection
- MED_DATA_IN => med_data_out,
- MED_PACKET_NUM_IN => med_packet_num_out,
- MED_DATAREADY_IN => med_dataready_out,
- MED_READ_OUT => med_read_in,
- MED_DATA_OUT => med_data_in,
- MED_PACKET_NUM_OUT => med_packet_num_in,
- MED_DATAREADY_OUT => med_dataready_in,
- MED_READ_IN => med_read_out,
+ MED_DATA_IN => int2med(0).data,
+ MED_PACKET_NUM_IN => int2med(0).packet_num,
+ MED_DATAREADY_IN => int2med(0).dataready,
+ MED_READ_OUT => med2int(0).tx_read,
+ MED_DATA_OUT => med2int(0).data,
+ MED_PACKET_NUM_OUT => med2int(0).packet_num,
+ MED_DATAREADY_OUT => med2int(0).dataready,
+ MED_READ_IN => '1',
REFCLK2CORE_OUT => open,
- CLK_RX_HALF_OUT => rx_clock_100,
- CLK_RX_FULL_OUT => rx_clock_200,
--SFP Connection
- SD_RXD_P_IN => SERDES_RX(2),
- SD_RXD_N_IN => SERDES_RX(3),
- SD_TXD_P_OUT => SERDES_TX(2),
- SD_TXD_N_OUT => SERDES_TX(3),
- SD_REFCLK_P_IN => open,
- SD_REFCLK_N_IN => open,
SD_PRSNT_N_IN => FPGA5_COMM(0),
SD_LOS_IN => FPGA5_COMM(0),
SD_TXDIS_OUT => FPGA5_COMM(2),
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
+-- SCI_DATA_IN => sci1_data_in,
+-- SCI_DATA_OUT => sci1_data_out,
+-- SCI_ADDR => sci1_addr,
+-- SCI_READ => sci1_read,
+-- SCI_WRITE => sci1_write,
+-- SCI_ACK => sci1_ack,
-- Status and control port
- STAT_OP => med_stat_op,
- CTRL_OP => med_ctrl_op,
+ STAT_OP => med2int(0).stat_op,
+ CTRL_OP => int2med(0).ctrl_op,
STAT_DEBUG => med_stat_debug,
CTRL_DEBUG => (others => '0')
);
-- Endpoint
---------------------------------------------------------------------------
- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
generic map(
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS,
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS,
ADDRESS_MASK => x"FFFF",
BROADCAST_BITMASK => x"FF",
- BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR,
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => HARDWARE_INFO,
- REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES,
- REGIO_INIT_ADDRESS => INIT_ADDRESS,
REGIO_USE_VAR_ENDPOINT_ID => c_YES,
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
- DATA_INTERFACE_NUMBER => 1, --NUM_TDC_MODULES,
+ DATA_INTERFACE_NUMBER => 1,
DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,
DATA_BUFFER_WIDTH => 32,
DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,
CLK => clk_100_i,
RESET => reset_i,
CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_out, -- open, --
- MED_DATA_OUT => med_data_out, -- open, --
- MED_PACKET_NUM_OUT => med_packet_num_out, -- open, --
- MED_READ_IN => med_read_in,
- MED_DATAREADY_IN => med_dataready_in,
- MED_DATA_IN => med_data_in,
- MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out, -- open, --
- MED_STAT_OP_IN => med_stat_op,
- MED_CTRL_OP_OUT => med_ctrl_op,
+
+ -- Media direction port
+ MEDIA_MED2INT => med2int(0),
+ MEDIA_INT2MED => int2med(0),
--Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
- --LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT => readout_rx.data_valid,
- LVL1_VALID_TIMING_TRG_OUT => readout_rx.valid_timing_trg,
- LVL1_VALID_NOTIMING_TRG_OUT => readout_rx.valid_notiming_trg,
- LVL1_INVALID_TRG_OUT => readout_rx.invalid_trg,
-
- LVL1_TRG_TYPE_OUT => readout_rx.trg_type,
- LVL1_TRG_NUMBER_OUT => readout_rx.trg_number,
- LVL1_TRG_CODE_OUT => readout_rx.trg_code,
- LVL1_TRG_INFORMATION_OUT => readout_rx.trg_information,
- LVL1_INT_TRG_NUMBER_OUT => readout_rx.trg_int_number,
-
- --Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT => readout_rx.trg_multiple,
- TRG_TIMEOUT_DETECTED_OUT => readout_rx.trg_timeout,
- TRG_SPURIOUS_TRG_OUT => readout_rx.trg_spurious,
- TRG_MISSING_TMG_TRG_OUT => readout_rx.trg_missing,
- TRG_SPIKE_DETECTED_OUT => readout_rx.trg_spike,
-
- --Response from FEE
- FEE_TRG_RELEASE_IN(0) => readout_tx(0).busy_release,
- FEE_TRG_STATUSBITS_IN => readout_tx(0).statusbits,
- FEE_DATA_IN => readout_tx(0).data,
- FEE_DATA_WRITE_IN(0) => readout_tx(0).data_write,
- FEE_DATA_FINISHED_IN(0) => readout_tx(0).data_finished,
- FEE_DATA_ALMOST_FULL_OUT(0) => readout_rx.buffer_almost_full,
+ TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
+
+ READOUT_RX => readout_rx,
+ READOUT_TX => readout_tx,
-- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
- REGIO_STAT_REG_IN => stat_reg, --start 0x80
- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
- REGIO_STAT_STROBE_OUT => stat_reg_strobe,
- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ BUS_RX => ctrlbus_rx,
+ BUS_TX => ctrlbus_tx,
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+
REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
- BUS_ADDR_OUT => regio_addr_out,
- BUS_READ_ENABLE_OUT => regio_read_enable_out,
- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
- BUS_DATA_OUT => regio_data_out,
- BUS_DATA_IN => regio_data_in,
- BUS_DATAREADY_IN => regio_dataready_in,
- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
- BUS_WRITE_ACK_IN => regio_write_ack_in,
- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- BUS_TIMEOUT_OUT => regio_timeout_out,
ONEWIRE_INOUT => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
-
- TIME_GLOBAL_OUT => global_time,
- TIME_LOCAL_OUT => local_time,
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
- TIME_TICKS_OUT => timer_ticks,
- TEMPERATURE_OUT => timer.temperature,
-
- STAT_DEBUG_IPU => open,
- STAT_DEBUG_1 => open,
- STAT_DEBUG_2 => open,
- STAT_DEBUG_DATA_HANDLER_OUT => open,
- STAT_DEBUG_IPU_HANDLER_OUT => open,
- STAT_TRIGGER_OUT => open,
- CTRL_MPLEX => (others => '0'),
- IOBUF_CTRL_GEN => (others => '0'),
- STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open,
- DEBUG_LVL1_HANDLER_OUT => open
+ --Timing registers
+ TIMERS_OUT => timer
);
----------------------------------------------------------------------------
--- I/O
----------------------------------------------------------------------------
- timing_trg_received_i <= TRIGGER_LEFT;
+ timing_trg_received_i <= TRIGGER_LEFT;
---------------------------------------------------------------------------
-- Bus Handler
---------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
- PORT_NUMBER => 6,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"c000", 2 => x"cf00", 3 => x"cf80",
- 4 => x"d500", 5 => x"b000", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 12, 2 => 6, 3 => 7,
- 4 => 4, 5 => 9, others => 0),
+ PORT_NUMBER => 2,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"c000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 12, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
CLK => clk_100_i,
RESET => reset_i,
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- --Bus Handler (SPI Flash control)
- BUS_READ_ENABLE_OUT(0) => spimem_read_en,
- BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
- BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
- BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
- BUS_DATAREADY_IN(0) => spimem_dataready_out,
- BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
- BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
- BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
- --TDC
- BUS_READ_ENABLE_OUT(1) => bustdc_rx.read,
- BUS_WRITE_ENABLE_OUT(1) => bustdc_rx.write,
- BUS_DATA_OUT(1*32+31 downto 1*32) => bustdc_rx.data,
- BUS_ADDR_OUT(1*16+11 downto 1*16) => bustdc_rx.addr(11 downto 0),
- BUS_TIMEOUT_OUT(1) => bustdc_rx.timeout,
- BUS_DATA_IN(1*32+31 downto 1*32) => bustdc_tx.data,
- BUS_DATAREADY_IN(1) => bustdc_tx.ack,
- BUS_WRITE_ACK_IN(1) => bustdc_tx.ack,
- BUS_NO_MORE_DATA_IN(1) => bustdc_tx.nack,
- BUS_UNKNOWN_ADDR_IN(1) => bustdc_tx.unknown,
- --Trigger logic registers
- BUS_READ_ENABLE_OUT(2) => trig_read,
- BUS_WRITE_ENABLE_OUT(2) => trig_write,
- BUS_DATA_OUT(2*32+31 downto 2*32) => trig_din,
- BUS_ADDR_OUT(2*16+15 downto 2*16) => trig_addr,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_DATA_IN(2*32+31 downto 2*32) => trig_dout,
- BUS_DATAREADY_IN(2) => trig_ack,
- BUS_WRITE_ACK_IN(2) => trig_ack,
- BUS_NO_MORE_DATA_IN(2) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => trig_nack,
- --Input statistics
- BUS_READ_ENABLE_OUT(3) => stat_read,
- BUS_WRITE_ENABLE_OUT(3) => stat_write,
- BUS_DATA_OUT(3*32+31 downto 3*32) => stat_din,
- BUS_ADDR_OUT(3*16+15 downto 3*16) => stat_addr,
- BUS_TIMEOUT_OUT(3) => open,
- BUS_DATA_IN(3*32+31 downto 3*32) => stat_dout,
- BUS_DATAREADY_IN(3) => stat_ack,
- BUS_WRITE_ACK_IN(3) => stat_ack,
- BUS_NO_MORE_DATA_IN(3) => '0',
- BUS_UNKNOWN_ADDR_IN(3) => stat_nack,
- --SEU Detection
- BUS_READ_ENABLE_OUT(4) => bussed_rx.read,
- BUS_WRITE_ENABLE_OUT(4) => bussed_rx.write,
- BUS_DATA_OUT(4*32+31 downto 4*32) => bussed_rx.data,
- BUS_ADDR_OUT(4*16+15 downto 4*16) => bussed_rx.addr,
- BUS_TIMEOUT_OUT(4) => bussed_rx.timeout,
- BUS_DATA_IN(4*32+31 downto 4*32) => bussed_tx.data,
- BUS_DATAREADY_IN(4) => bussed_tx.ack,
- BUS_WRITE_ACK_IN(4) => bussed_tx.ack,
- BUS_NO_MORE_DATA_IN(4) => bussed_tx.nack,
- BUS_UNKNOWN_ADDR_IN(4) => bussed_tx.unknown,
- --SCI first Media Interface
- BUS_READ_ENABLE_OUT(5) => sci1_read,
- BUS_WRITE_ENABLE_OUT(5) => sci1_write,
- BUS_DATA_OUT(5*32+7 downto 5*32) => sci1_data_in,
- BUS_DATA_OUT(5*32+31 downto 5*32+8) => open,
- BUS_ADDR_OUT(5*16+8 downto 5*16) => sci1_addr,
- BUS_ADDR_OUT(5*16+15 downto 5*16+9) => open,
- BUS_TIMEOUT_OUT(5) => open,
- BUS_DATA_IN(5*32+7 downto 5*32) => sci1_data_out,
- BUS_DATAREADY_IN(5) => sci1_ack,
- BUS_WRITE_ACK_IN(5) => sci1_ack,
- BUS_NO_MORE_DATA_IN(5) => '0',
- BUS_UNKNOWN_ADDR_IN(5) => '0',
+ REGIO_RX => ctrlbus_rx,
+ REGIO_TX => ctrlbus_tx,
+
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+ BUS_RX(1) => bustdc_rx, --TDC config
+ BUS_TX(0) => bustools_tx,
+ BUS_TX(1) => bustdc_tx,
STAT_DEBUG => open
);
---------------------------------------------------------------------------
--- SPI / Flash
+-- Control Tools
---------------------------------------------------------------------------
-
- THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload
+ THE_TOOLS : entity work.trb3_tools
port map(
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
-
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_DATAREADY_OUT => spimem_dataready_out,
- BUS_WRITE_ACK_OUT => spimem_write_ack_out,
- BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
- BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
-
- DO_REBOOT_IN => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN,
-
- SPI_CS_OUT => FLASH_CS,
- SPI_SCK_OUT => FLASH_CLK,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SDI_IN => FLASH_DOUT
- );
-
----------------------------------------------------------------------------
--- Trigger logic
----------------------------------------------------------------------------
- gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
- THE_TRIG_LOGIC : input_to_trigger_logic
- generic map(
- INPUTS => PHYSICAL_INPUTS,
- OUTPUTS => 4
- )
- port map(
- CLK => clk_100_i,
-
- INPUT => INP(PHYSICAL_INPUTS-1 downto 0),
- OUTPUT => trig_out,
-
- DATA_IN => trig_din,
- DATA_OUT => trig_dout,
- WRITE_IN => trig_write,
- READ_IN => trig_read,
- ACK_OUT => trig_ack,
- NACK_OUT => trig_nack,
- ADDR_IN => trig_addr
- );
- FPGA5_COMM(10 downto 7) <= trig_out;
- end generate;
+ CLK => clk_100_i,
+ RESET => reset_i,
----------------------------------------------------------------------------
--- Input Statistics
----------------------------------------------------------------------------
- gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate
-
- THE_STAT_LOGIC : entity work.input_statistics
- generic map(
- INPUTS => PHYSICAL_INPUTS
- )
- port map(
- CLK => clk_100_i,
-
- INPUT => INP(PHYSICAL_INPUTS-1 downto 0),
-
- DATA_IN => stat_din,
- DATA_OUT => stat_dout,
- WRITE_IN => stat_write,
- READ_IN => stat_read,
- ACK_OUT => stat_ack,
- NACK_OUT => stat_nack,
- ADDR_IN => stat_addr
- );
- end generate;
+ --Flash & Reload
+ FLASH_CS => FLASH_CS,
+ FLASH_CLK => FLASH_CLK,
+ FLASH_IN => FLASH_DOUT,
+ FLASH_OUT => FLASH_DIN,
+ PROGRAMN => PROGRAMN,
+ REBOOT_IN => common_ctrl_reg(15),
+ --SPI
+ SPI_CS_OUT => spi_cs,
+ SPI_MOSI_OUT => spi_mosi,
+ SPI_MISO_IN => spi_miso,
+ SPI_CLK_OUT => spi_clk,
+ SPI_CLR_OUT => spi_clr,
+ --LCD
+ LCD_DATA_IN => (others => '0'),
+ UART_RX_IN => uart_rx,
+ UART_TX_OUT => uart_tx,
+ DEBUG_RX_IN => debug_rx,
+ DEBUG_TX_OUT => debug_tx,
+
+ --Trigger & Monitor
+ MONITOR_INPUTS(23 downto 0) => hit_in_i(24 downto 1),
+ MONITOR_INPUTS(27 downto 24) => trig_gen_out_i,
+ TRIG_GEN_INPUTS => hit_in_i(24 downto 1),
+ TRIG_GEN_OUTPUTS => trig_gen_out_i,
+ LCD_OUT => lcd_out,
+ --SED
+ SED_ERROR_OUT => sed_error_i,
+ --Slowcontrol
+ BUS_RX => bustools_rx,
+ BUS_TX => bustools_tx,
+ --Control master for default settings
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ DEBUG_OUT => open
+ );
---------------------------------------------------------------------------
--- SED Detection
----------------------------------------------------------------------------
- THE_SED : entity work.sedcheck
- port map(
- CLK => clk_100_i,
- ERROR_OUT => sed_error,
- BUS_RX => bussed_rx,
- BUS_TX => bussed_tx
- );
-
+-- Feature I/O
+---------------------------------------------------------------------------
+
+ FPGA5_COMM(10 downto 7) <= trig_gen_out_i;
+ FPGA5_COMM(6 downto 3) <= (others => 'Z');
+ FPGA5_COMM(1) <= 'Z';
+
+ feature_outputs_i(0) <= uart_rx;
+ feature_outputs_i(1) <= uart_tx;
+ feature_outputs_i(2) <= spi_cs(4);
+ feature_outputs_i(3) <= spi_mosi(4);
+ feature_outputs_i(4) <= spi_clk(4);
+ spi_miso(4) <= TEST_LINE(5);
+ feature_outputs_i(7) <= lcd_out(4); --lcd_cs
+ feature_outputs_i(8) <= lcd_out(0); --lcd_rst
+ feature_outputs_i(9) <= lcd_out(3); --lcd_dc
+ feature_outputs_i(10) <= lcd_out(2); --lcd_mosi
+ feature_outputs_i(11) <= lcd_out(1); --lcd_sck
+ --12 is LCD MISO, but not used
+ feature_outputs_i(14) <= debug_rx;
+ feature_outputs_i(15) <= debug_tx;
+
+
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
- LED_ORANGE <= not reset_i when rising_edge(clk_100_i);
- LED_YELLOW <= '1';
- LED_GREEN <= not med_stat_op(9);
- LED_RED <= not (med_stat_op(10) or med_stat_op(11));
+ LED_GREEN <= not med2int(0).stat_op(9);
+ LED_ORANGE <= not med2int(0).stat_op(10);
+ LED_RED <= not '0';
+ LED_YELLOW <= not med2int(0).stat_op(11);
-------------------------------------------------------------------------------
-- LED ADDON
-- Test Connector
---------------------------------------------------------------------------
-- TEST_LINE(15 downto 0) <= (others => '0');
- TEST_LINE(15 downto 0) <= logic_analyser_i;
-
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
- --process
- --begin
- -- wait until rising_edge(clk_100_i);
- -- time_counter <= time_counter + 1;
- --end process;
+-- TEST_LINE(15 downto 0) <= logic_analyser_i;
-------------------------------------------------------------------------------
-- TDC
SIMULATION => c_NO)
port map (
RESET => reset_i,
- CLK_TDC => CLK_PCLK_LEFT,
+ CLK_TDC => clk_200_i,
CLK_READOUT => clk_100_i, -- Clock for the readout
REFERENCE_TIME => timing_trg_received_i, -- Reference time input
HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
- HIT_CAL_IN => clk_cal, -- Hits for calibrating the TDC
+ HIT_CAL_IN => osc_int, -- Hits for calibrating the TDC
-- Trigger signals from handler
BUSRDO_RX => readout_rx,
BUSRDO_TX => readout_tx(0),
);
- -- For single edge measurements
gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
hit_in_i(8 downto 1) <= INP(7 downto 0);
hit_in_i(24 downto 9) <= not INP(23 downto 8);
end generate;
+ assert DOUBLE_EDGE_TYPE /= 2 report "double edge in separate channels: connections missing" severity error;
+
-- For ToT Measurements
- gen_double : if DOUBLE_EDGE_TYPE = 2 generate
- Gen_Hit_In_Signals : for i in 1 to 8 generate
- hit_in_i(i*2-1) <= INP(i-1);
- hit_in_i(i*2) <= not INP(i-1);
- end generate Gen_Hit_In_Signals;
- Gen_Hit_In_Signals : for i in 9 to 24 generate
- hit_in_i(i*2-1) <= not INP(i-1);
- hit_in_i(i*2) <= INP(i-1);
- end generate Gen_Hit_In_Signals;
- end generate;
+-- gen_double : if DOUBLE_EDGE_TYPE = 2 generate
+-- Gen_Hit_In_Signals : for i in 1 to 8 generate
+-- hit_in_i(i*2-1) <= INP(i-1);
+-- hit_in_i(i*2) <= not INP(i-1);
+-- end generate Gen_Hit_In_Signals;
+-- Gen_Hit_In_Signals : for i in 9 to 24 generate
+-- hit_in_i(i*2-1) <= not INP(i-1);
+-- hit_in_i(i*2) <= INP(i-1);
+-- end generate Gen_Hit_In_Signals;
+-- end generate;
+
end architecture;
--Serdes
CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 0, not used
- SERDES_TX : out std_logic_vector(3 downto 2);
- SERDES_RX : in std_logic_vector(3 downto 2);
+-- SERDES_TX : out std_logic_vector(3 downto 2);
+-- SERDES_RX : in std_logic_vector(3 downto 2);
FPGA5_COMM : inout std_logic_vector(11 downto 0);
--Bit 0/1 input, serial link RX active
--Connections
- SPARE_LINE : inout std_logic_vector(3 downto 0);
+-- SPARE_LINE : inout std_logic_vector(3 downto 0);
INP : in std_logic_vector(63 downto 0);
--Flash ROM & Reboot
attribute syn_useioff of FLASH_DIN : signal is true;
attribute syn_useioff of FLASH_DOUT : signal is true;
attribute syn_useioff of TEST_LINE : signal is true;
- attribute syn_useioff of SPARE_LINE : signal is true;
+-- attribute syn_useioff of SPARE_LINE : signal is true;
attribute syn_useioff of INP : signal is false;
end entity;
architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is
- --Constants
- constant REGIO_NUM_STAT_REGS : integer := 0;
- constant REGIO_NUM_CTRL_REGS : integer := 2;
-
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
--Clock / Reset
- signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
- signal osc_int : std_logic; -- clock for calibrating the tdc, 2.5 MHz, via internal osscilator
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal GSR_N : std_logic;
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
- signal clk_100_internal : std_logic;
- signal clk_200_internal : std_logic;
- signal rx_clock_100 : std_logic;
- signal rx_clock_200 : std_logic;
- signal clk_tdc : std_logic;
- signal time_counter, time_counter2 : unsigned(31 downto 0);
- --Media Interface
- signal med_stat_op : std_logic_vector (1*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0);
- signal med_data_out : std_logic_vector (1*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
- signal med_dataready_out : std_logic;
- signal med_read_out : std_logic;
- signal med_data_in : std_logic_vector (1*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);
- signal med_dataready_in : std_logic;
- signal med_read_in : std_logic;
+ signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
+ signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
+ signal clk_20 : std_logic; --clock for calibration at 20 MHz, via PLL
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
+ signal clear_i : std_logic;
+ signal reset_i : std_logic;
+ signal GSR_N : std_logic;
+ signal osc_int : std_logic;
+ attribute syn_keep of GSR_N : signal is true;
+ attribute syn_preserve of GSR_N : signal is true;
+ --Media Interface
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
+ signal med2int : med2int_array_t(0 to 0);
+ signal int2med : int2med_array_t(0 to 0);
+
--LVL1 channel
- signal timing_trg_received_i : std_logic;
+ signal timing_trg_received_i : std_logic;
--READOUT
signal readout_rx : READOUT_RX;
signal readout_tx : readout_tx_array_t(0 to 0);
--Slow Control channel
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal timer : TIMERS;
-
- --RegIO
- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-
- --Flash
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(8 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_dataready_out : std_logic;
- signal spimem_no_more_data_out : std_logic;
- signal spimem_unknown_addr_out : std_logic;
- signal spimem_write_ack_out : std_logic;
-
- signal dac_read_en : std_logic;
- signal dac_write_en : std_logic;
- signal dac_data_in : std_logic_vector(31 downto 0);
- signal dac_addr : std_logic_vector(4 downto 0);
- signal dac_data_out : std_logic_vector(31 downto 0);
- signal dac_ack : std_logic;
- signal dac_busy : std_logic;
-
- signal spi_bram_addr : std_logic_vector(7 downto 0);
- signal spi_bram_wr_d : std_logic_vector(7 downto 0);
- signal spi_bram_rd_d : std_logic_vector(7 downto 0);
- signal spi_bram_we : std_logic;
-
- signal sci1_ack : std_logic;
- signal sci1_write : std_logic;
- signal sci1_read : std_logic;
- signal sci1_data_in : std_logic_vector(7 downto 0);
- signal sci1_data_out : std_logic_vector(7 downto 0);
- signal sci1_addr : std_logic_vector(8 downto 0);
-
- signal padiwa_cs : std_logic_vector(3 downto 0);
- signal padiwa_sck : std_logic;
- signal padiwa_sdi : std_logic;
- signal padiwa_sdo : std_logic;
-
- signal trig_out : std_logic_vector(3 downto 0);
- signal trig_din : std_logic_vector(31 downto 0);
- signal trig_dout : std_logic_vector(31 downto 0);
- signal trig_write : std_logic := '0';
- signal trig_read : std_logic := '0';
- signal trig_ack : std_logic := '0';
- signal trig_nack : std_logic := '0';
- signal trig_addr : std_logic_vector(15 downto 0) := (others => '0');
-
- signal stat_out : std_logic_vector(3 downto 0);
- signal stat_din : std_logic_vector(31 downto 0);
- signal stat_dout : std_logic_vector(31 downto 0);
- signal stat_write : std_logic := '0';
- signal stat_read : std_logic := '0';
- signal stat_ack : std_logic := '0';
- signal stat_nack : std_logic := '0';
- signal stat_addr : std_logic_vector(15 downto 0) := (others => '0');
-
- signal sed_error : std_logic;
- signal bussed_rx, bustdc_rx : CTRLBUS_RX;
- signal bussed_tx, bustdc_tx : CTRLBUS_TX;
+
+ signal ctrlbus_rx, bustdc_rx, bustools_rx, bus_master_out, bustrigger_rx : CTRLBUS_RX;
+ signal ctrlbus_tx, bustdc_tx, bustools_tx, bus_master_in, bustrigger_tx : CTRLBUS_TX;
+ signal bus_master_active : std_logic;
+ signal timer : TIMERS;
+ signal lcd_data : std_logic_vector(511 downto 0);
+ signal lcd_out : std_logic_vector(4 downto 0);
+ signal feature_outputs_i : std_logic_vector(15 downto 0);
+ signal spi_cs, spi_mosi, spi_miso, spi_clk, spi_clr : std_logic_vector(15 downto 0);
+ signal uart_rx, uart_tx, debug_rx, debug_tx : std_logic;
+ signal trig_gen_out_i : std_logic_vector(3 downto 0);
+ signal sed_error_i : std_logic;
+ signal serdes_i : std_logic_vector(3 downto 0);
+ attribute nopad : string;
+ attribute nopad of serdes_i : signal is "true";
+
+ signal triggerlogic_out : std_logic_vector(7 downto 0);
--TDC
- signal hit_in_i : std_logic_vector(64 downto 1);
- signal input_i : std_logic_vector(64 downto 1);
+ signal hit_in_i : std_logic_vector(64 downto 1);
+ signal logic_analyser_i : std_logic_vector(15 downto 0);
+
begin
---------------------------------------------------------------------------
SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
+ TRB_RESET_IN => med2int(0).stat_op(13), -- TRBnet reset signal (SYSCLK)
CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
DEBUG_OUT => open
port map(
CLK => CLK_GPLL_RIGHT,
RESET => '0',
- CLKOP => clk_100_internal,
- CLKOK => clk_200_internal,
+ CLKOP => clk_100_i,
+ CLKOK => clk_200_i,
LOCK => pll_lock
);
CLKOP => osc_int,
LOCK => open);
- gen_sync_clocks : if SYNC_MODE = c_YES generate
- clk_100_i <= rx_clock_100;
- clk_200_i <= rx_clock_200;
- clk_tdc <= rx_clock_200;
- end generate;
-
- gen_local_clocks : if SYNC_MODE = c_NO generate
- clk_100_i <= clk_100_internal;
- clk_200_i <= clk_200_internal;
- clk_tdc <= CLK_PCLK_LEFT;
- end generate;
+-- gen_sync_clocks : if SYNC_MODE = c_YES generate
+-- clk_100_i <= rx_clock_100;
+-- clk_200_i <= rx_clock_200;
+-- clk_tdc <= rx_clock_200;
+-- end generate;
+--
+-- gen_local_clocks : if SYNC_MODE = c_NO generate
+-- clk_100_i <= clk_100_internal;
+-- clk_200_i <= clk_200_internal;
+-- clk_tdc <= CLK_PCLK_LEFT;
+-- end generate;
---------------------------------------------------------------------------
-- The TrbNet media interface (to other FPGA)
CLEAR => clear_i,
CLK_EN => '1',
--Internal Connection
- MED_DATA_IN => med_data_out,
- MED_PACKET_NUM_IN => med_packet_num_out,
- MED_DATAREADY_IN => med_dataready_out,
- MED_READ_OUT => med_read_in,
- MED_DATA_OUT => med_data_in,
- MED_PACKET_NUM_OUT => med_packet_num_in,
- MED_DATAREADY_OUT => med_dataready_in,
- MED_READ_IN => med_read_out,
+ MED_DATA_IN => int2med(0).data,
+ MED_PACKET_NUM_IN => int2med(0).packet_num,
+ MED_DATAREADY_IN => int2med(0).dataready,
+ MED_READ_OUT => med2int(0).tx_read,
+ MED_DATA_OUT => med2int(0).data,
+ MED_PACKET_NUM_OUT => med2int(0).packet_num,
+ MED_DATAREADY_OUT => med2int(0).dataready,
+ MED_READ_IN => '1',
REFCLK2CORE_OUT => open,
- CLK_RX_HALF_OUT => rx_clock_100,
- CLK_RX_FULL_OUT => rx_clock_200,
-
--SFP Connection
- SD_RXD_P_IN => SERDES_RX(2),
- SD_RXD_N_IN => SERDES_RX(3),
- SD_TXD_P_OUT => SERDES_TX(2),
- SD_TXD_N_OUT => SERDES_TX(3),
- SD_REFCLK_P_IN => open,
- SD_REFCLK_N_IN => open,
SD_PRSNT_N_IN => FPGA5_COMM(0),
SD_LOS_IN => FPGA5_COMM(0),
SD_TXDIS_OUT => FPGA5_COMM(2),
-
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
-- Status and control port
- STAT_OP => med_stat_op,
- CTRL_OP => med_ctrl_op,
+ STAT_OP => med2int(0).stat_op,
+ CTRL_OP => int2med(0).ctrl_op,
STAT_DEBUG => med_stat_debug,
CTRL_DEBUG => (others => '0')
);
-- Endpoint
---------------------------------------------------------------------------
- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
+ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
generic map(
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS,
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS,
ADDRESS_MASK => x"FFFF",
BROADCAST_BITMASK => x"FF",
- BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR,
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => HARDWARE_INFO,
- REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES,
- REGIO_INIT_ADDRESS => INIT_ADDRESS,
REGIO_USE_VAR_ENDPOINT_ID => c_YES,
- CLOCK_FREQUENCY => CLOCK_FREQUENCY,
TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
DATA_INTERFACE_NUMBER => 1,
CLK => clk_100_i,
RESET => reset_i,
CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_out, -- open, --
- MED_DATA_OUT => med_data_out, -- open, --
- MED_PACKET_NUM_OUT => med_packet_num_out, -- open, --
- MED_READ_IN => med_read_in,
- MED_DATAREADY_IN => med_dataready_in,
- MED_DATA_IN => med_data_in,
- MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out, -- open, --
- MED_STAT_OP_IN => med_stat_op,
- MED_CTRL_OP_OUT => med_ctrl_op,
+
+ -- Media direction port
+ MEDIA_MED2INT => med2int(0),
+ MEDIA_INT2MED => int2med(0),
--Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
- --LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT => readout_rx.data_valid,
- LVL1_VALID_TIMING_TRG_OUT => readout_rx.valid_timing_trg,
- LVL1_VALID_NOTIMING_TRG_OUT => readout_rx.valid_notiming_trg,
- LVL1_INVALID_TRG_OUT => readout_rx.invalid_trg,
-
- LVL1_TRG_TYPE_OUT => readout_rx.trg_type,
- LVL1_TRG_NUMBER_OUT => readout_rx.trg_number,
- LVL1_TRG_CODE_OUT => readout_rx.trg_code,
- LVL1_TRG_INFORMATION_OUT => readout_rx.trg_information,
- LVL1_INT_TRG_NUMBER_OUT => readout_rx.trg_int_number,
-
- --Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT => readout_rx.trg_multiple,
- TRG_TIMEOUT_DETECTED_OUT => readout_rx.trg_timeout,
- TRG_SPURIOUS_TRG_OUT => readout_rx.trg_spurious,
- TRG_MISSING_TMG_TRG_OUT => readout_rx.trg_missing,
- TRG_SPIKE_DETECTED_OUT => readout_rx.trg_spike,
-
- --Response from FEE
- FEE_TRG_RELEASE_IN(0) => readout_tx(0).busy_release,
- FEE_TRG_STATUSBITS_IN => readout_tx(0).statusbits,
- FEE_DATA_IN => readout_tx(0).data,
- FEE_DATA_WRITE_IN(0) => readout_tx(0).data_write,
- FEE_DATA_FINISHED_IN(0) => readout_tx(0).data_finished,
- FEE_DATA_ALMOST_FULL_OUT(0) => readout_rx.buffer_almost_full,
+ TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
+
+ READOUT_RX => readout_rx,
+ READOUT_TX => readout_tx,
-- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
- REGIO_STAT_REG_IN => stat_reg, --start 0x80
- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
- REGIO_STAT_STROBE_OUT => stat_reg_strobe,
- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
+ BUS_RX => ctrlbus_rx,
+ BUS_TX => ctrlbus_tx,
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+
REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
- BUS_ADDR_OUT => regio_addr_out,
- BUS_READ_ENABLE_OUT => regio_read_enable_out,
- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
- BUS_DATA_OUT => regio_data_out,
- BUS_DATA_IN => regio_data_in,
- BUS_DATAREADY_IN => regio_dataready_in,
- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
- BUS_WRITE_ACK_IN => regio_write_ack_in,
- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- BUS_TIMEOUT_OUT => regio_timeout_out,
ONEWIRE_INOUT => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
-
- TIME_GLOBAL_OUT => global_time,
- TIME_LOCAL_OUT => local_time,
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
- TIME_TICKS_OUT => timer_ticks,
- TEMPERATURE_OUT => timer.temperature,
-
- STAT_DEBUG_IPU => open,
- STAT_DEBUG_1 => open,
- STAT_DEBUG_2 => open,
- STAT_DEBUG_DATA_HANDLER_OUT => open,
- STAT_DEBUG_IPU_HANDLER_OUT => open,
- STAT_TRIGGER_OUT => open,
- CTRL_MPLEX => (others => '0'),
- IOBUF_CTRL_GEN => (others => '0'),
- STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open,
- DEBUG_LVL1_HANDLER_OUT => open
+ --Timing registers
+ TIMERS_OUT => timer
);
+ timing_trg_received_i <= TRIGGER_LEFT; --TRIGGER_RIGHT; --
----------------------------------------------------------------------------
--- I/O
----------------------------------------------------------------------------
- timing_trg_received_i <= TRIGGER_LEFT;
---------------------------------------------------------------------------
-- Bus Handler
---------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
- PORT_NUMBER => 7,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"d400", 2 => x"c000", 3 => x"b000",
- 4 => x"cf00", 5 => x"cf80", 6 => x"d500", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 12, 3 => 9,
- 4 => 6, 5 => 7, 6 => 4, others => 0),
+ PORT_NUMBER => 3,
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"c000", 2 => x"e000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, 1 => 12, 2 => 12, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
CLK => clk_100_i,
RESET => reset_i,
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- --Bus Handler (SPI Flash control)
- BUS_READ_ENABLE_OUT(0) => spimem_read_en,
- BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
- BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
- BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
- BUS_DATAREADY_IN(0) => spimem_dataready_out,
- BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
- BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
- BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
- --DAC
- BUS_READ_ENABLE_OUT(1) => dac_read_en,
- BUS_WRITE_ENABLE_OUT(1) => dac_write_en,
- BUS_DATA_OUT(1*32+31 downto 1*32) => dac_data_in,
- BUS_ADDR_OUT(1*16+4 downto 1*16) => dac_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+5) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_DATA_IN(1*32+31 downto 1*32) => dac_data_out,
- BUS_DATAREADY_IN(1) => dac_ack,
- BUS_WRITE_ACK_IN(1) => dac_ack,
- BUS_NO_MORE_DATA_IN(1) => dac_busy,
- BUS_UNKNOWN_ADDR_IN(1) => '0',
- --TDC
- BUS_READ_ENABLE_OUT(2) => bustdc_rx.read,
- BUS_WRITE_ENABLE_OUT(2) => bustdc_rx.write,
- BUS_DATA_OUT(2*32+31 downto 2*32) => bustdc_rx.data,
- BUS_ADDR_OUT(2*16+15 downto 2*16) => bustdc_rx.addr,
- BUS_TIMEOUT_OUT(2) => bustdc_rx.timeout,
- BUS_DATA_IN(2*32+31 downto 2*32) => bustdc_tx.data,
- BUS_DATAREADY_IN(2) => bustdc_tx.ack,
- BUS_WRITE_ACK_IN(2) => bustdc_tx.ack,
- BUS_NO_MORE_DATA_IN(2) => bustdc_tx.nack,
- BUS_UNKNOWN_ADDR_IN(2) => bustdc_tx.unknown,
- --SCI first Media Interface
- BUS_READ_ENABLE_OUT(3) => sci1_read,
- BUS_WRITE_ENABLE_OUT(3) => sci1_write,
- BUS_DATA_OUT(3*32+7 downto 3*32) => sci1_data_in,
- BUS_DATA_OUT(3*32+31 downto 3*32+8) => open,
- BUS_ADDR_OUT(3*16+8 downto 3*16) => sci1_addr,
- BUS_ADDR_OUT(3*16+15 downto 3*16+9) => open,
- BUS_TIMEOUT_OUT(3) => open,
- BUS_DATA_IN(3*32+7 downto 3*32) => sci1_data_out,
- BUS_DATAREADY_IN(3) => sci1_ack,
- BUS_WRITE_ACK_IN(3) => sci1_ack,
- BUS_NO_MORE_DATA_IN(3) => '0',
- BUS_UNKNOWN_ADDR_IN(3) => '0',
- --Trigger logic registers
- BUS_READ_ENABLE_OUT(4) => trig_read,
- BUS_WRITE_ENABLE_OUT(4) => trig_write,
- BUS_DATA_OUT(4*32+31 downto 4*32) => trig_din,
- BUS_ADDR_OUT(4*16+15 downto 4*16) => trig_addr,
- BUS_TIMEOUT_OUT(4) => open,
- BUS_DATA_IN(4*32+31 downto 4*32) => trig_dout,
- BUS_DATAREADY_IN(4) => trig_ack,
- BUS_WRITE_ACK_IN(4) => trig_ack,
- BUS_NO_MORE_DATA_IN(4) => '0',
- BUS_UNKNOWN_ADDR_IN(4) => trig_nack,
- --Input statistics
- BUS_READ_ENABLE_OUT(5) => stat_read,
- BUS_WRITE_ENABLE_OUT(5) => stat_write,
- BUS_DATA_OUT(5*32+31 downto 5*32) => stat_din,
- BUS_ADDR_OUT(5*16+15 downto 5*16) => stat_addr,
- BUS_TIMEOUT_OUT(5) => open,
- BUS_DATA_IN(5*32+31 downto 5*32) => stat_dout,
- BUS_DATAREADY_IN(5) => stat_ack,
- BUS_WRITE_ACK_IN(5) => stat_ack,
- BUS_NO_MORE_DATA_IN(5) => '0',
- BUS_UNKNOWN_ADDR_IN(5) => stat_nack,
- --SEU Detection
- BUS_READ_ENABLE_OUT(6) => bussed_rx.read,
- BUS_WRITE_ENABLE_OUT(6) => bussed_rx.write,
- BUS_DATA_OUT(6*32+31 downto 6*32) => bussed_rx.data,
- BUS_ADDR_OUT(6*16+15 downto 6*16) => bussed_rx.addr,
- BUS_TIMEOUT_OUT(6) => bussed_rx.timeout,
- BUS_DATA_IN(6*32+31 downto 6*32) => bussed_tx.data,
- BUS_DATAREADY_IN(6) => bussed_tx.ack,
- BUS_WRITE_ACK_IN(6) => bussed_tx.ack,
- BUS_NO_MORE_DATA_IN(6) => bussed_tx.nack,
- BUS_UNKNOWN_ADDR_IN(6) => bussed_tx.unknown,
+ REGIO_RX => ctrlbus_rx,
+ REGIO_TX => ctrlbus_tx,
+
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
+ BUS_RX(1) => bustdc_rx, --TDC config
+ BUS_RX(2) => bustrigger_rx,
+ BUS_TX(0) => bustools_tx,
+ BUS_TX(1) => bustdc_tx,
+ BUS_TX(2) => bustrigger_tx,
STAT_DEBUG => open
);
---------------------------------------------------------------------------
--- SPI / Flash
+-- Control Tools
---------------------------------------------------------------------------
- THE_SPI_RELOAD : entity spi_flash_and_fpga_reload
+ THE_TOOLS : entity work.trb3_tools
port map(
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
-
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_DATAREADY_OUT => spimem_dataready_out,
- BUS_WRITE_ACK_OUT => spimem_write_ack_out,
- BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
- BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
-
- DO_REBOOT_IN => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN,
-
- SPI_CS_OUT => FLASH_CS,
- SPI_SCK_OUT => FLASH_CLK,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SDI_IN => FLASH_DOUT
- );
-
----------------------------------------------------------------------------
--- DAC
----------------------------------------------------------------------------
- gen_SPI : if INCLUDE_SPI = 1 generate
- THE_DAC_SPI : spi_ltc2600
- port map(
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- -- Slave bus
- BUS_ADDR_IN => dac_addr,
- BUS_READ_IN => dac_read_en,
- BUS_WRITE_IN => dac_write_en,
- BUS_ACK_OUT => dac_ack,
- BUS_BUSY_OUT => dac_busy,
- BUS_DATA_IN => dac_data_in,
- BUS_DATA_OUT => dac_data_out,
- -- SPI connections
- SPI_CS_OUT(3 downto 0) => padiwa_cs,
- SPI_SDI_IN => padiwa_sdi,
- SPI_SDO_OUT => padiwa_sdo,
- SPI_SCK_OUT => padiwa_sck
- );
- OUT_CS <= padiwa_cs(3 downto 0);
- OUT_SCK <= padiwa_sck & padiwa_sck & padiwa_sck & padiwa_sck;
- OUT_SDO <= padiwa_sdo & padiwa_sdo & padiwa_sdo & padiwa_sdo;
- padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0));
- end generate;
+ CLK => clk_100_i,
+ RESET => reset_i,
----------------------------------------------------------------------------
--- Trigger logic
----------------------------------------------------------------------------
- gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
- THE_TRIG_LOGIC : input_to_trigger_logic
- generic map(
- INPUTS => PHYSICAL_INPUTS,
- OUTPUTS => 4
- )
- port map(
- CLK => clk_100_i,
-
- INPUT => input_i(PHYSICAL_INPUTS downto 1),
- OUTPUT => trig_out,
-
- DATA_IN => trig_din,
- DATA_OUT => trig_dout,
- WRITE_IN => trig_write,
- READ_IN => trig_read,
- ACK_OUT => trig_ack,
- NACK_OUT => trig_nack,
- ADDR_IN => trig_addr
- );
- FPGA5_COMM(10 downto 7) <= trig_out;
- end generate;
+ --Flash & Reload
+ FLASH_CS => FLASH_CS,
+ FLASH_CLK => FLASH_CLK,
+ FLASH_IN => FLASH_DOUT,
+ FLASH_OUT => FLASH_DIN,
+ PROGRAMN => PROGRAMN,
+ REBOOT_IN => common_ctrl_reg(15),
+ --SPI
+ SPI_CS_OUT => spi_cs,
+ SPI_MOSI_OUT => spi_mosi,
+ SPI_MISO_IN => spi_miso,
+ SPI_CLK_OUT => spi_clk,
+ SPI_CLR_OUT => spi_clr,
+ --LCD
+ LCD_DATA_IN => lcd_data,
+ UART_RX_IN => uart_rx,
+ UART_TX_OUT => uart_tx,
+ DEBUG_RX_IN => debug_rx,
+ DEBUG_TX_OUT => debug_tx,
+
+ --Trigger & Monitor
+ MONITOR_INPUTS(47 downto 0) => hit_in_i(48 downto 1),
+ MONITOR_INPUTS(51 downto 48) => trig_gen_out_i,
+ TRIG_GEN_INPUTS => hit_in_i(48 downto 1),
+ TRIG_GEN_OUTPUTS => trig_gen_out_i,
+ LCD_OUT => lcd_out,
+ --SED
+ SED_ERROR_OUT => sed_error_i,
+ --Slowcontrol
+ BUS_RX => bustools_rx,
+ BUS_TX => bustools_tx,
+ --Control master for default settings
+ BUS_MASTER_IN => bus_master_in,
+ BUS_MASTER_OUT => bus_master_out,
+ BUS_MASTER_ACTIVE => bus_master_active,
+ DEBUG_OUT => open
+ );
+
+-- OUT_CS <= padiwa_cs(3 downto 0);
+-- OUT_SCK <= padiwa_sck & padiwa_sck & padiwa_sck & padiwa_sck;
+-- OUT_SDO <= padiwa_sdo & padiwa_sdo & padiwa_sdo & padiwa_sdo;
+-- padiwa_sdi <= or_all(IN_SDI and not padiwa_cs(3 downto 0));
+
+
+
+THE_TRIGGER_LOGIC : entity work.trigger_logic
+ generic map(
+ INPUTS => 24,
+ OUTPUTS => 8
+ )
+ port map(
+ CLK => clk_100_i,
+ RESET => reset_i,
+
+ --Slowcontrol
+ BUS_RX => bustrigger_rx,
+ BUS_TX => bustrigger_tx,
+
+ --Inputs and Outputs
+ INPUT => hit_in_i(24 downto 1),
+ OUTPUT => triggerlogic_out(7 downto 0)
+ );
+ FPGA5_COMM(10 downto 7) <= trig_gen_out_i or triggerlogic_out(3 downto 0);
----------------------------------------------------------------------------
--- Input Statistics
----------------------------------------------------------------------------
- gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate
-
- THE_STAT_LOGIC : entity input_statistics
- generic map(
- INPUTS => PHYSICAL_INPUTS
- )
- port map(
- CLK => clk_100_i,
-
- INPUT => input_i(PHYSICAL_INPUTS downto 1),
-
- DATA_IN => stat_din,
- DATA_OUT => stat_dout,
- WRITE_IN => stat_write,
- READ_IN => stat_read,
- ACK_OUT => stat_ack,
- NACK_OUT => stat_nack,
- ADDR_IN => stat_addr
- );
- end generate;
+
+ --FPGA5_COMM(10 downto 7) <= trig_gen_out_i;
+
+
---------------------------------------------------------------------------
--- SED Detection
----------------------------------------------------------------------------
- THE_SED : entity sedcheck
- port map(
- CLK => clk_100_i,
- ERROR_OUT => sed_error,
- BUS_RX => bussed_rx,
- BUS_TX => bussed_tx
- );
-
+-- Feature I/O
+---------------------------------------------------------------------------
+
+ FPGA5_COMM(6 downto 3) <= (others => 'Z');
+ FPGA5_COMM(1) <= 'Z';
+
+ feature_outputs_i(0) <= uart_rx;
+ feature_outputs_i(1) <= uart_tx;
+ feature_outputs_i(2) <= spi_cs(4);
+ feature_outputs_i(3) <= spi_mosi(4);
+ feature_outputs_i(4) <= spi_clk(4);
+-- spi_miso(4) <= TEST_LINE(5);
+ feature_outputs_i(7) <= lcd_out(4); --lcd_cs
+ feature_outputs_i(8) <= lcd_out(0); --lcd_rst
+ feature_outputs_i(9) <= lcd_out(3); --lcd_dc
+ feature_outputs_i(10) <= lcd_out(2); --lcd_mosi
+ feature_outputs_i(11) <= lcd_out(1); --lcd_sck
+ --12 is LCD MISO, but not used
+ feature_outputs_i(14) <= debug_rx;
+ feature_outputs_i(15) <= debug_tx;
+
+ OUT_CS <= spi_cs(3 downto 0);
+ OUT_SCK <= spi_clk(3 downto 0);
+ OUT_SDO <= spi_mosi(3 downto 0);
+ spi_miso(3 downto 0) <= IN_SDI;
+
---------------------------------------------------------------------------
-- LED
---------------------------------------------------------------------------
- LED_ORANGE <= not reset_i when rising_edge(clk_100_i);
- LED_YELLOW <= '1';
- LED_GREEN <= not med_stat_op(9);
- LED_RED <= not (med_stat_op(10) or med_stat_op(11));
+ LED_GREEN <= not med2int(0).stat_op(9);
+ LED_ORANGE <= not med2int(0).stat_op(10);
+ LED_RED <= not '0';
+ LED_YELLOW <= not med2int(0).stat_op(11);
---------------------------------------------------------------------------
-- Test Connector
---------------------------------------------------------------------------
-- TEST_LINE(15 downto 0) <= (others => '0');
+ TEST_LINE(7 downto 0) <= triggerlogic_out;
+
---------------------------------------------------------------------------
-- Test Circuits
---------------------------------------------------------------------------
- process
- begin
- wait until rising_edge(clk_100_i);
- time_counter <= time_counter + 1;
- end process;
+-- process
+-- begin
+-- wait until rising_edge(clk_100_i);
+-- time_counter <= time_counter + 1;
+-- end process;
-------------------------------------------------------------------------------
-- TDC
SIMULATION => c_NO)
port map (
RESET => reset_i,
- CLK_TDC => clk_tdc,
+ CLK_TDC => clk_200_i,
CLK_READOUT => clk_100_i, -- Clock for the readout
REFERENCE_TIME => timing_trg_received_i, -- Reference time input
HIT_IN => hit_in_i(NUM_TDC_CHANNELS-1 downto 1), -- Channel start signals
BUS_TX => bustdc_tx,
-- Dubug signals
INFO_IN => timer,
- LOGIC_ANALYSER_OUT => TEST_LINE
+ LOGIC_ANALYSER_OUT => logic_analyser_i
);
-- For single edge measurements
gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
hit_in_i <= INP;
- input_i <= INP;
+-- input_i <= INP;
end generate;
-- For ToT Measurements
Gen_Hit_In_Signals : for i in 1 to 32 generate
hit_in_i(i*2-1) <= INP(i-1);
hit_in_i(i*2) <= not INP(i-1);
- input_i(i) <= INP(i-1);
+-- input_i(i) <= INP(i-1);
end generate Gen_Hit_In_Signals;
end generate;
Gen_Hit_Fast_Signals : for i in 1 to 32 generate
hit_in_i(i*2-1) <= INP(i*2-2);
hit_in_i(i*2) <= not INP(i*2-2);
- input_i(i) <= INP(i*2-2);
+-- input_i(i) <= INP(i*2-2);
end generate;
end generate;
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