-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
-- Module Version: 5.1
---/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n pll_in100_out25 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -fclkop 25 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode CLOCKTREE -extcap AUTO -noclkos -noclkok -norst -e
+--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n pll_in100_out25 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -fclkop 25 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode INTERNAL -extcap AUTO -noclkos -noclkok -norst -e
--- Wed Mar 10 19:09:50 2010
+-- Fri Mar 12 18:02:07 2010
library IEEE;
use IEEE.std_logic_1164.all;
-- internal signal declarations
signal CLKOP_t: std_logic;
+ signal CLKFB_t: std_logic;
signal scuba_vlo: std_logic;
signal CLK_t: std_logic;
PHASE_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOP_DIV=> 48,
CLKFB_DIV=> 1, CLKI_DIV=> 4)
-- synopsys translate_on
- port map (CLKI=>CLK_t, CLKFB=>CLKOP_t, RST=>scuba_vlo,
+ port map (CLKI=>CLK_t, CLKFB=>CLKFB_t, RST=>scuba_vlo,
RSTK=>scuba_vlo, DPAMODE=>scuba_vlo, DRPAI3=>scuba_vlo,
DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
DFPAI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open,
- LOCK=>LOCK, CLKINTFB=>open);
+ LOCK=>LOCK, CLKINTFB=>CLKFB_t);
CLKOP <= CLKOP_t;
CLK_t <= CLK;