cbmnet phy: additional debug tools .. data transport works ... sometimes

diff --git a/cbmnet/code/cbmnet_phy_ecp3.vhd b/cbmnet/code/cbmnet_phy_ecp3.vhd
index 168dd2a3bd45676107828a02a247bbac6c1c8d8a..1e5f8eadaf69e70fc9eb3ab6a35ee762351b4b89 100755 (executable)
--- a/cbmnet/code/cbmnet_phy_ecp3.vhd
+++ b/cbmnet/code/cbmnet_phy_ecp3.vhd
@@ -96,9 +96,9 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is
    signal rx_dec_error_i:          std_logic;
    signal rx_dec_error_delayed_i : std_logic;
    signal rx_dec_error_250_i : std_logic_vector(1 downto 0);
-   signal rx_dec_error_125_i, rx_dec_error_125_buf_i: std_logic_vector(3 downto 0);
+   signal rx_dec_error_125_i, rx_dec_error_125_buf_i: std_logic_vector(1 downto 0);
 
-   signal rx_error_delay : std_logic_vector(3 downto 0); -- shift register to detect a "stable error condition"
+   signal rx_error_delay : std_logic_vector(7 downto 0) := (others => '0'); -- shift register to detect a "stable error condition"
    
    -- resets
    signal rst_qd_i            : std_logic;
@@ -235,6 +235,13 @@ architecture cbmnet_phy_ecp3_arch of cbmnet_phy_ecp3 is
    
    signal rx_data_sp_i0, rx_data_sp_i1, rx_data_sp_i2, rx_data_sp_i3 : std_logic_vector(17 downto 0);
    
+   signal tx_data_sp_i0, tx_data_sp_i1, tx_data_sp_i2, tx_data_sp_i3 : std_logic_vector(17 downto 0);
+   signal tx_data_sp_i4, tx_data_sp_i5, tx_data_sp_i6, tx_data_sp_i7 : std_logic_vector(17 downto 0);
+   signal tx_data_sp_i8, tx_data_sp_i9, tx_data_sp_i10,tx_data_sp_i11: std_logic_vector(17 downto 0);
+   
+   signal dlm_counter_i : unsigned(15 downto 0) := x"0000";
+   signal detect_dlm_125_i, detect_dlm_250_i : std_logic := '0';
+   
    --signal see_dlm_lb_i, see_dlm_lb_buf_i : std_logic_vector(15 downto 0) := (others => '0');
    --signal see_dlm_lb_aggr_i, see_dlm_hb_i, see_dlm_hb_buf_i : std_logic;
    --signal stat_sync_dlm_counter_i, stat_sync_dlm_inv_counter_i : unsigned(7 downto 0);
@@ -342,7 +349,7 @@ begin
       DEBUG_OUT   => rx_gear_debug_i
    );
    
-   rx_data_i <= rx_data_from_gear_i when rising_edge(clk_125_local);
+   rx_data_i <= rx_data_from_gear_i when rising_edge(rclk_125_i);
    
    THE_TX_GEAR: CBMNET_PHY_TX_GEAR
    generic map (IS_SYNC_SLAVE => IS_SYNC_SLAVE)
@@ -394,13 +401,13 @@ begin
    
    
 --   -- decode error
---   rx_dec_error_delayed_i <= rx_dec_error_delayed_i when rising_edge(rclk_250_i);
---   rx_dec_error_250_i <= rx_dec_error_i & rx_dec_error_delayed_i when rising_edge(rclk_250_i);
---   
---   rx_dec_error_125_i <= rx_dec_error_125_i(0) & rx_dec_error_i when rising_edge(clk_125_local);
---   rx_dec_error_125_buf_i <= rx_dec_error_125_i when rising_edge(clk_125_local);
---   
---   rx_error_delay <= rx_error_delay(rx_error_delay'high - 2 downto 0) & rx_dec_error_125_buf_i when rising_edge(clk_125_local);
+  rx_dec_error_delayed_i <= rx_dec_error_i when rising_edge(rclk_250_i);
+  rx_dec_error_250_i <= rx_dec_error_i & rx_dec_error_delayed_i when rising_edge(rclk_250_i);
+  
+  rx_dec_error_125_i     <= rx_dec_error_250_i when rising_edge(clk_125_local);
+  rx_dec_error_125_buf_i <= rx_dec_error_125_i when rising_edge(clk_125_local);
+  
+  rx_error_delay <= rx_error_delay(rx_error_delay'high - 2 downto 0) & rx_dec_error_125_buf_i when rising_edge(clk_125_local);
 --   process is 
 --   begin
 --      wait until rising_edge(rclk_125_i);
@@ -547,7 +554,7 @@ begin
             sci_read_i      <= '0';
             sci_write_i     <= '0';
             sci_timer       <= sci_timer + 1;
-            if sci_timer(sci_timer'left) = '1' then
+            if sci_timer(sci_timer'left) = '1' and rx_rst_fsm_ready_i = '1' then
                sci_timer     <= (others => '0');
                sci_state     <= GET_WA;
             end if;      
@@ -698,8 +705,12 @@ begin
           DEBUG_OUT(243 downto 212) <= rm_rx_ebtb_code_err_cntr_i(15 downto 0) & rm_rx_ebtb_disp_err_cntr_i(15 downto 0);
 
           DEBUG_OUT(315 downto 244) <= rx_data_sp_i3(17 downto 0) & rx_data_sp_i2(17 downto 0) & rx_data_sp_i1(17 downto 0) & rx_data_sp_i0(17 downto 0);
+          DEBUG_OUT(331 downto 316) <= dlm_counter_i(15 downto 0);
+--        DEBUG_OUT(333 downto 316) <= PHY_TXDATA_K_IN(1 downto 0) & PHY_TXDATA_IN(15 downto 0);
+          
+
+          DEBUG_OUT(511 downto 332) <= tx_data_sp_i3(17 downto 0) & tx_data_sp_i2(17 downto 0) & tx_data_sp_i1(17 downto 0) & tx_data_sp_i0(17 downto 0) & tx_data_sp_i7(17 downto 0) & tx_data_sp_i6(17 downto 0) & tx_data_sp_i5(17 downto 0) & tx_data_sp_i4(17 downto 0) &         tx_data_sp_i8(17 downto 0) & tx_data_sp_i9(17 downto 0);
           
-          DEBUG_OUT(333 downto 316) <= PHY_TXDATA_K_IN(1 downto 0) & PHY_TXDATA_IN(15 downto 0);
           --DEBUG_OUT(341 downto 334) <= stat_sync_dlm_inv_counter_i(7 downto 0) when rising_edge(rclk_125_i);
       --DEBUG_OUT(349 downto 342) <= stat_sync_dlm_counter_i(7 downto 0) when rising_edge(rclk_125_i); 
           
@@ -712,13 +723,61 @@ begin
       process is
       begin
          wait until rising_edge(rclk_125_i);
-         if rx_data_i /= "10" & x"fcc3" then
+         if rx_data_i /= "10" & x"fcc3" and  rx_data_i /= "00" & x"0000" then
             rx_data_sp_i0 <= rx_data_i;
             rx_data_sp_i1 <= rx_data_sp_i0;
             rx_data_sp_i2 <= rx_data_sp_i1;
             rx_data_sp_i3 <= rx_data_sp_i2;
          end if;
       end process;
+
+      
+      process is
+      begin
+         wait until rising_edge(rclk_125_i);
+         if tx_data_i /= "10" & x"fcc3" and tx_data_i(17 downto 16) /= "00" then
+            tx_data_sp_i0 <= tx_data_i;
+            tx_data_sp_i1 <= tx_data_sp_i0;
+            tx_data_sp_i2 <= tx_data_sp_i1;
+            tx_data_sp_i3 <= tx_data_sp_i2;
+            tx_data_sp_i4 <= tx_data_sp_i3;
+            tx_data_sp_i5 <= tx_data_sp_i4;
+            tx_data_sp_i6 <= tx_data_sp_i5;
+            tx_data_sp_i7 <= tx_data_sp_i6;
+            tx_data_sp_i8 <= tx_data_sp_i7;
+            tx_data_sp_i9 <= tx_data_sp_i8;
+            tx_data_sp_i10 <= tx_data_sp_i9;
+            tx_data_sp_i11 <= tx_data_sp_i10;
+         end if;
+      end process;
+      
+      
+      process is 
+         variable detect_first_v : std_logic := '0';
+      begin
+         wait until rising_edge(rclk_250_i);
+         
+         if rx_data_from_serdes_i = "1" & K277 and detect_first_v = '1' then
+            detect_dlm_250_i <= not detect_dlm_250_i;
+         end if;
+         
+         detect_first_v := '0';
+         if rx_data_from_serdes_i = "0" & EBTB_D_ENCODE(14, 6) then
+            detect_first_v := '1';
+         end if;
+      end process;
+      
+      process is 
+      begin
+         wait until rising_edge(rclk_125_i);
+         
+         if detect_dlm_250_i /= detect_dlm_125_i then
+            dlm_counter_i <= dlm_counter_i + 1;
+         end if;
+         
+         detect_dlm_125_i <= detect_dlm_250_i;
+      end process;
+      
       
       --PROC_SEE_FAST_DLM: process is
          --variable saw_lb_v, saw_hb_v : std_logic;

diff --git a/cbmnet/code/cbmnet_phy_pkg.vhd b/cbmnet/code/cbmnet_phy_pkg.vhd
index a7675580039b22276604c0eeb6b07d8fd452d18f..c5e2d4dba592f92f0b015b977dbc6c8a9d82936c 100755 (executable)
--- a/cbmnet/code/cbmnet_phy_pkg.vhd
+++ b/cbmnet/code/cbmnet_phy_pkg.vhd
@@ -10,7 +10,8 @@ package cbmnet_phy_pkg is
       generic(
          IS_SYNC_SLAVE   : integer := c_NO;       --select slave mode
          IS_SIMULATED    : integer := c_NO;
-         INCL_DEBUG_AIDS : integer := c_YES
+         INCL_DEBUG_AIDS : integer;
+         DETERMINISTIC_LATENCY : integer := c_YES -- if selected proper alignment of barrel shifter and word alignment is enforced (link may come up slower)
       );
       port(
          CLK                : in  std_logic; -- *internal* 125 MHz reference clock

diff --git a/cbmnet/code/cbmnet_phy_rx_gear.vhd b/cbmnet/code/cbmnet_phy_rx_gear.vhd
index f7b132e13bd7080ab49ecae8fa2171ba978ceebf..07508d04da256c5244275e02ff3b42a082bf1008 100644 (file)
--- a/cbmnet/code/cbmnet_phy_rx_gear.vhd
+++ b/cbmnet/code/cbmnet_phy_rx_gear.vhd
@@ -73,7 +73,7 @@ begin
          delay_clock_i <= '0';
          fsm_state_i <= x"0";
          
-      elsif rising_edge(clk_125_i) then
+      else
          SERDES_RESET_OUT <= '0';
          RESET_OUT <= '1';
          reset_timer_i <= '0';
@@ -125,38 +125,33 @@ begin
       end if;
    end process;
    
--- Timeout (approx. 2ms)
+-- Timeout (approx. 4ms)
    proc_timeout: process is 
-      variable timer_v : unsigned(19 downto 0) := (others => '0');
-      variable idx : integer := 18;
+      variable timer_v : unsigned(20 downto 0) := (others => '0');
    begin
       wait until rising_edge(clk_125_i);
       
-      if IS_SYNC_SLAVE = 0 then
-         idx := timer_v'high;
-      end if;
-      
       if reset_timer_i = '1' then
          timer_v := TO_UNSIGNED(0, timer_v'length);
          
-      elsif timer_v(idx) = '0' then
+      elsif timer_v(timer_v'high) = '0' then
          timer_v := timer_v + TO_UNSIGNED(1,1);
          
       end if;
 
-      timeout_i <= timer_v(idx);
+      timeout_i <= timer_v(timer_v'high);
    end process;
 
 -- Implement the 2:1 gearing and clock down-sampling
-   delay_clock_buf1_i <= delay_clock_i when rising_edge(CLK_250_IN);
-   delay_clock_buf_i <= delay_clock_buf1_i when rising_edge(CLK_250_IN);
+   --delay_clock_buf1_i <= delay_clock_i when rising_edge(CLK_250_IN);
+   delay_clock_buf_i <= delay_clock_i when rising_edge(CLK_250_IN);
  
 
    proc_ctrl_gear: process
    begin
       wait until rising_edge(CLK_250_IN);
 
-      if not (delay_clock_buf_i = '1' and last_delay_clock_i = '0') then
+      if not (delay_clock_buf_i = '1' and last_delay_clock_i = '0') or PCS_READY_IN='0' then
          word_idx_i <= not word_idx_i;
       end if;
       

diff --git a/cbmnet/code/cbmnet_phy_tx_gear.vhd b/cbmnet/code/cbmnet_phy_tx_gear.vhd
index 7d7df3988e17d4acffdb00dbd04af0f5b4106142..ca0ff1ef2a482a0ebc22446f81d133f74dc039f5 100644 (file)
--- a/cbmnet/code/cbmnet_phy_tx_gear.vhd
+++ b/cbmnet/code/cbmnet_phy_tx_gear.vhd
@@ -57,7 +57,7 @@ begin
          delay_counter_i <= TO_UNSIGNED(0,16);
       end if;
       
-      data_in_buf250_0_i <= data_in_buf250_i;
+      data_in_buf250_0_i <= data_in_buf125_i;
       data_in_buf250_i <= data_in_buf250_0_i;