fixed wrong signal to inhibit TX

diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd
index a46bdef423cf0f525535b83e29636732a021455b..61bf2737e92293da531054a846db47c886a102ac 100644 (file)
--- a/media_interfaces/sync/med_sync_control_RS.vhd
+++ b/media_interfaces/sync/med_sync_control_RS.vhd
@@ -235,7 +235,7 @@ begin
       SEND_RST_IN              => TX_RST_IN,
       SEND_RST_WORD_IN         => TX_RST_WORD_IN,
      -- link status signals, internally synced
-      LINK_TX_READY_IN         => '0', -- BUG
+      LINK_TX_READY_IN         => LINK_TX_READY_IN,
       LINK_RX_READY_IN         => link_rx_ready_i,
       LINK_HALF_DONE_IN        => link_half_done_i,
       LINK_FULL_DONE_IN        => link_full_done_i,
@@ -289,15 +289,15 @@ begin
                                          else x"7";
 
 -- TEST_LINE signals
-  DEBUG_OUT(3 downto 0)   <= rx_fsm_state;
-  DEBUG_OUT(4)            <= RX_LOS_IN;
-  DEBUG_OUT(5)            <= RX_CDR_LOL_IN;
-  DEBUG_OUT(6)            <= TX_PLL_LOL_IN;
-  DEBUG_OUT(7)            <= LINK_TX_READY_IN;
-  DEBUG_OUT(8)            <= link_rx_ready_i;
-  DEBUG_OUT(9)            <= is_wap_zero_i;
-  DEBUG_OUT(10)           <= link_half_done_i;
-  DEBUG_OUT(11)           <= link_full_done_i;
+  DEBUG_OUT(3 downto 0)   <= rx_fsm_state when rising_edge(CLK_REF);
+  DEBUG_OUT(4)            <= RX_LOS_IN when rising_edge(CLK_REF);
+  DEBUG_OUT(5)            <= RX_CDR_LOL_IN when rising_edge(CLK_REF);
+  DEBUG_OUT(6)            <= TX_PLL_LOL_IN when rising_edge(CLK_REF);
+  DEBUG_OUT(7)            <= LINK_TX_READY_IN when rising_edge(CLK_REF);
+  DEBUG_OUT(8)            <= link_rx_ready_i when rising_edge(CLK_REF);
+  DEBUG_OUT(9)            <= is_wap_zero_i when rising_edge(CLK_REF);
+  DEBUG_OUT(10)           <= link_half_done_i when rising_edge(CLK_REF);
+  DEBUG_OUT(11)           <= link_full_done_i when rising_edge(CLK_REF);
   DEBUG_OUT(12)           <= '0';
   DEBUG_OUT(13)           <= '0';
   DEBUG_OUT(14)           <= '0';

diff --git a/media_interfaces/sync/rx_rsl.vhd b/media_interfaces/sync/rx_rsl.vhd
index 019a9038c5b9461dbdc3c299af80643de9d55fc6..91cfdca84b91740006a4614916634cf735223fe2 100644 (file)
--- a/media_interfaces/sync/rx_rsl.vhd
+++ b/media_interfaces/sync/rx_rsl.vhd
@@ -42,8 +42,8 @@ architecture rx_rsl_arc of rx_rsl is
   signal cnt          : unsigned(31 downto 0);\r
 \r
   type rx_sm_state is (POWERUP, APPLY_CDR_RST, WAIT_CDR_LOCK, TEST_CDR, \r
-                       CHECK_WAP, APPLY_RXPCS_RST, WAIT_RXPCS_LOCK, \r
-                       TEST_RXPCS, NORMAL_OP);\r
+                       APPLY_RXPCS_RST, WAIT_RXPCS_LOCK, TEST_RXPCS, \r
+                       CHECK_WAP, NORMAL_OP);\r
 \r
   signal rx_sm : rx_sm_state;\r
   \r
@@ -131,27 +131,14 @@ begin
         else\r
           if( cnt = Tcdr ) then\r
             cnt <= (others => '0');\r
-            rx_sm <= CHECK_WAP;\r
+            rx_sm <= APPLY_RXPCS_RST;\r
           else\r
             cnt <= cnt + 1;\r
           end if;\r
         end if;\r
 \r
-      -- THIS STATE CAN BE ASSIMILATED INTO TEST_CDR\r
-      when CHECK_WAP => \r
-        STATE_OUT <= x"4";\r
-        RX_SERDES_RST_OUT <= '0';\r
-        RX_PCS_RST_OUT    <= '1'; -- really?\r
-        LINK_RX_READY_OUT <= '0';\r
-        cnt <= (others => '0');\r
-        if( WAP_ZERO_IN = '1' ) then\r
-          rx_sm <= NORMAL_OP;\r
-        else\r
-          rx_sm <= APPLY_CDR_RST;\r
-        end if;\r
-\r
       when APPLY_RXPCS_RST =>\r
-        STATE_OUT <= x"5";\r
+        STATE_OUT <= x"4";\r
         RX_SERDES_RST_OUT <= '0';\r
         RX_PCS_RST_OUT    <= '1';\r
         LINK_RX_READY_OUT <= '0';\r
@@ -163,7 +150,7 @@ begin
         end if;\r
 \r
       when WAIT_RXPCS_LOCK =>\r
-        STATE_OUT <= x"6";\r
+        STATE_OUT <= x"5";\r
         RX_SERDES_RST_OUT <= '0';\r
         RX_PCS_RST_OUT    <= '0';\r
         LINK_RX_READY_OUT <= '0';\r
@@ -175,7 +162,7 @@ begin
         end if;\r
 \r
       when TEST_RXPCS =>\r
-        STATE_OUT <= x"7";\r
+        STATE_OUT <= x"6";\r
         RX_SERDES_RST_OUT <= '0';\r
         RX_PCS_RST_OUT    <= '0';\r
         LINK_RX_READY_OUT <= '0';\r
@@ -185,11 +172,24 @@ begin
         else\r
           if( cnt = Tviol ) then\r
             cnt <= (others => '0');\r
-            rx_sm <= NORMAL_OP;\r
+            rx_sm <= CHECK_WAP;\r
           else\r
             cnt <= cnt + 1;\r
           end if;\r
         end if;\r
+\r
+      when CHECK_WAP =>\r
+        STATE_OUT <= x"7";\r
+        RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '0';\r
+        LINK_RX_READY_OUT <= '0';\r
+        cnt <= (others => '0');\r
+        if( WAP_ZERO_IN = '1' ) then\r
+          rx_sm <= NORMAL_OP;\r
+        else\r
+--          rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK\r
+          rx_sm <= APPLY_CDR_RST;\r
+        end if;\r
      \r
       when NORMAL_OP =>\r
         STATE_OUT <= x"8";\r

diff --git a/media_interfaces/sync/rx_rsl_ORIG.vhd b/media_interfaces/sync/rx_rsl_WRONG.vhd
similarity index 92%
rename from media_interfaces/sync/rx_rsl_ORIG.vhd
rename to media_interfaces/sync/rx_rsl_WRONG.vhd
index 0e3cabf153b31c01edd4c06466522637be005a44..019a9038c5b9461dbdc3c299af80643de9d55fc6 100644 (file)
--- a/media_interfaces/sync/rx_rsl_ORIG.vhd
+++ b/media_interfaces/sync/rx_rsl_WRONG.vhd
@@ -42,8 +42,8 @@ architecture rx_rsl_arc of rx_rsl is
   signal cnt          : unsigned(31 downto 0);\r
 \r
   type rx_sm_state is (POWERUP, APPLY_CDR_RST, WAIT_CDR_LOCK, TEST_CDR, \r
-                       APPLY_RXPCS_RST, WAIT_RXPCS_LOCK, TEST_RXPCS, \r
-                       CHECK_WAP, TX_SYNC, NORMAL_OP);\r
+                       CHECK_WAP, APPLY_RXPCS_RST, WAIT_RXPCS_LOCK, \r
+                       TEST_RXPCS, NORMAL_OP);\r
 \r
   signal rx_sm : rx_sm_state;\r
   \r
@@ -131,15 +131,28 @@ begin
         else\r
           if( cnt = Tcdr ) then\r
             cnt <= (others => '0');\r
-            rx_sm <= APPLY_RXPCS_RST;\r
+            rx_sm <= CHECK_WAP;\r
           else\r
             cnt <= cnt + 1;\r
           end if;\r
         end if;\r
 \r
-      when APPLY_RXPCS_RST =>\r
+      -- THIS STATE CAN BE ASSIMILATED INTO TEST_CDR\r
+      when CHECK_WAP => \r
         STATE_OUT <= x"4";\r
         RX_SERDES_RST_OUT <= '0';\r
+        RX_PCS_RST_OUT    <= '1'; -- really?\r
+        LINK_RX_READY_OUT <= '0';\r
+        cnt <= (others => '0');\r
+        if( WAP_ZERO_IN = '1' ) then\r
+          rx_sm <= NORMAL_OP;\r
+        else\r
+          rx_sm <= APPLY_CDR_RST;\r
+        end if;\r
+\r
+      when APPLY_RXPCS_RST =>\r
+        STATE_OUT <= x"5";\r
+        RX_SERDES_RST_OUT <= '0';\r
         RX_PCS_RST_OUT    <= '1';\r
         LINK_RX_READY_OUT <= '0';\r
         if( cnt = Tshort ) then\r
@@ -150,7 +163,7 @@ begin
         end if;\r
 \r
       when WAIT_RXPCS_LOCK =>\r
-        STATE_OUT <= x"5";\r
+        STATE_OUT <= x"6";\r
         RX_SERDES_RST_OUT <= '0';\r
         RX_PCS_RST_OUT    <= '0';\r
         LINK_RX_READY_OUT <= '0';\r
@@ -162,7 +175,7 @@ begin
         end if;\r
 \r
       when TEST_RXPCS =>\r
-        STATE_OUT <= x"6";\r
+        STATE_OUT <= x"7";\r
         RX_SERDES_RST_OUT <= '0';\r
         RX_PCS_RST_OUT    <= '0';\r
         LINK_RX_READY_OUT <= '0';\r
@@ -172,24 +185,11 @@ begin
         else\r
           if( cnt = Tviol ) then\r
             cnt <= (others => '0');\r
-            rx_sm <= CHECK_WAP;\r
+            rx_sm <= NORMAL_OP;\r
           else\r
             cnt <= cnt + 1;\r
           end if;\r
         end if;\r
-\r
-      when CHECK_WAP =>\r
-        STATE_OUT <= x"7";\r
-        RX_SERDES_RST_OUT <= '0';\r
-        RX_PCS_RST_OUT    <= '0';\r
-        LINK_RX_READY_OUT <= '0';\r
-        cnt <= (others => '0');\r
-        if( WAP_ZERO_IN = '1' ) then\r
-          rx_sm <= NORMAL_OP;\r
-        else\r
---          rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK\r
-          rx_sm <= APPLY_CDR_RST;\r
-        end if;\r
      \r
       when NORMAL_OP =>\r
         STATE_OUT <= x"8";\r