+++ /dev/null
-BLOCK RESETPATHS ;
-BLOCK ASYNCPATHS ;
-BLOCK RD_DURING_WR_PATHS ;
-
-#################################################################
-# Reset Nets
-#################################################################
-GSR_NET NET "GSR_N";
-
-
-#################################################################
-# Locate Serdes and media interfaces
-#################################################################
-LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;
-
-
-REGION "MEDIA_UPLINK" "R102C95D" 13 25;
-LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ;
-
-# REGION "REGION_ENDPOINT" "" ;
-
-
-
-
-#################################################################
-# TDC Constraints
-#################################################################
-##############################################################################
-## REGION DECLERATION ##
-##############################################################################
-#REGION "Region_0" "R109C2D" 6 93 DEVSIZE;
-#REGION "Region_1" "R100C2D" 5 93 DEVSIZE;
-#REGION "Region_2" "R89C2D" 6 93 DEVSIZE;
-#REGION "Region_3" "R82C2D" 6 93 DEVSIZE;
-
-#REGION "Region_4" "R71C2D" 6 93 DEVSIZE;
-#REGION "Region_5" "R64C2D" 6 93 DEVSIZE;
-#REGION "Region_6" "R53C2D" 6 93 DEVSIZE;
-#REGION "Region_7" "R46C2D" 6 93 DEVSIZE;
-
-REGION "Region_E&F_0" "R105C2D" 6 60 DEVSIZE;
-REGION "Region_E&F_1" "R92C2D" 10 60 DEVSIZE;
-REGION "Region_E&F_2" "R74C2D" 10 60 DEVSIZE;
-REGION "Region_E&F_3" "R56C2D" 10 60 DEVSIZE;
-REGION "Region_E&F_4" "R38C2D" 10 60 DEVSIZE;
-REGION "Region_E&F_5" "R24C2D" 5 60 DEVSIZE;
-REGION "Region_E&F_6" "R11C2D" 10 60 DEVSIZE;
-
-REGION "Region_E&F_7" "R105C122D" 6 60 DEVSIZE;
-REGION "Region_E&F_8" "R92C122D" 10 60 DEVSIZE;
-REGION "Region_E&F_9" "R74C122D" 10 60 DEVSIZE;
-REGION "Region_E&F_10" "R56C122D" 10 60 DEVSIZE;
-REGION "Region_E&F_11" "R38C122D" 10 60 DEVSIZE;
-REGION "Region_E&F_12" "R24C122D" 5 60 DEVSIZE;
-REGION "Region_E&F_13" "R11C122D" 10 60 DEVSIZE;
-
-
-
-
-
-
-
-
-##############################################################################
-## DELAY LINE and HIT BUFFER PLACEMENTS ##
-##############################################################################
-#
-UGROUP "FC_1" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_1_Channels/FC;
-LOCATE UGROUP "FC_1" SITE "R110C2D" ;
-UGROUP "hit_1"
- BLKNAME THE_TDC/GEN_Channels_1_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_1" SITE "R111C4D" ;
-#
-UGROUP "FC_2" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_2_Channels/FC;
-LOCATE UGROUP "FC_2" SITE "R104C2D" ;
-UGROUP "hit_2"
- BLKNAME THE_TDC/GEN_Channels_2_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_2" SITE "R105C4D" ;
-#
-UGROUP "FC_3" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_3_Channels/FC;
-LOCATE UGROUP "FC_3" SITE "R101C2D" ;
-UGROUP "hit_3"
- BLKNAME THE_TDC/GEN_Channels_3_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_3" SITE "R102C4D" ;
-#
-UGROUP "FC_4" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_4_Channels/FC;
-LOCATE UGROUP "FC_4" SITE "R92C2D" ;
-UGROUP "hit_4"
- BLKNAME THE_TDC/GEN_Channels_4_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_4" SITE "R93C4D" ;
-#
-UGROUP "FC_5" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_5_Channels/FC;
-LOCATE UGROUP "FC_5" SITE "R89C2D" ;
-UGROUP "hit_5"
- BLKNAME THE_TDC/GEN_Channels_5_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_5" SITE "R90C4D" ;
-#
-UGROUP "FC_6" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_6_Channels/FC;
-LOCATE UGROUP "FC_6" SITE "R86C2D" ;
-UGROUP "hit_6"
- BLKNAME THE_TDC/GEN_Channels_6_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_6" SITE "R87C4D" ;
-#
-UGROUP "FC_7" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_7_Channels/FC;
-LOCATE UGROUP "FC_7" SITE "R83C2D" ;
-UGROUP "hit_7"
- BLKNAME THE_TDC/GEN_Channels_7_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_7" SITE "R84C4D" ;
-#
-UGROUP "FC_8" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_8_Channels/FC;
-LOCATE UGROUP "FC_8" SITE "R74C2D" ;
-UGROUP "hit_8"
- BLKNAME THE_TDC/GEN_Channels_8_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_8" SITE "R75C4D" ;
-#
-UGROUP "FC_9" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_9_Channels/FC;
-LOCATE UGROUP "FC_9" SITE "R71C2D" ;
-UGROUP "hit_9"
- BLKNAME THE_TDC/GEN_Channels_9_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_9" SITE "R72C4D" ;
-#
-UGROUP "FC_10" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_10_Channels/FC;
-LOCATE UGROUP "FC_10" SITE "R68C2D" ;
-UGROUP "hit_10"
- BLKNAME THE_TDC/GEN_Channels_10_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_10" SITE "R69C4D" ;
-#
-UGROUP "FC_11" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_11_Channels/FC;
-LOCATE UGROUP "FC_11" SITE "R65C2D" ;
-UGROUP "hit_11"
- BLKNAME THE_TDC/GEN_Channels_11_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_11" SITE "R66C4D" ;
-#
-UGROUP "FC_12" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_12_Channels/FC;
-LOCATE UGROUP "FC_12" SITE "R56C2D" ;
-UGROUP "hit_12"
- BLKNAME THE_TDC/GEN_Channels_12_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_12" SITE "R57C4D" ;
-#
-UGROUP "FC_13" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_13_Channels/FC;
-LOCATE UGROUP "FC_13" SITE "R53C2D" ;
-UGROUP "hit_13"
- BLKNAME THE_TDC/GEN_Channels_13_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_13" SITE "R54C4D" ;
-#
-UGROUP "FC_14" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_14_Channels/FC;
-LOCATE UGROUP "FC_14" SITE "R50C2D" ;
-UGROUP "hit_14"
- BLKNAME THE_TDC/GEN_Channels_14_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_14" SITE "R51C4D" ;
-#
-UGROUP "FC_15" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_15_Channels/FC;
-LOCATE UGROUP "FC_15" SITE "R47C2D" ;
-UGROUP "hit_15"
- BLKNAME THE_TDC/GEN_Channels_15_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_15" SITE "R48C4D" ;
-#
-UGROUP "FC_16" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_16_Channels/FC;
-LOCATE UGROUP "FC_16" SITE "R38C2D" ;
-UGROUP "hit_16"
- BLKNAME THE_TDC/GEN_Channels_16_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_16" SITE "R39C4D" ;
-#
-UGROUP "FC_17" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_17_Channels/FC;
-LOCATE UGROUP "FC_17" SITE "R35C2D" ;
-UGROUP "hit_17"
- BLKNAME THE_TDC/GEN_Channels_17_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_17" SITE "R36C4D" ;
-#
-UGROUP "FC_18" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_18_Channels/FC;
-LOCATE UGROUP "FC_18" SITE "R32C2D" ;
-UGROUP "hit_18"
- BLKNAME THE_TDC/GEN_Channels_18_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_18" SITE "R33C4D" ;
-#
-UGROUP "FC_19" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_19_Channels/FC;
-LOCATE UGROUP "FC_19" SITE "R29C2D" ;
-UGROUP "hit_19"
- BLKNAME THE_TDC/GEN_Channels_19_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_19" SITE "R30C4D" ;
-#
-UGROUP "FC_20" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_20_Channels/FC;
-LOCATE UGROUP "FC_20" SITE "R23C2D" ;
-UGROUP "hit_20"
- BLKNAME THE_TDC/GEN_Channels_20_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_20" SITE "R24C4D" ;
-#
-UGROUP "FC_21" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_21_Channels/FC;
-LOCATE UGROUP "FC_21" SITE "R20C2D" ;
-UGROUP "hit_21"
- BLKNAME THE_TDC/GEN_Channels_21_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_21" SITE "R21C4D" ;
-#
-UGROUP "FC_22" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_22_Channels/FC;
-LOCATE UGROUP "FC_22" SITE "R10C2D" ;
-UGROUP "hit_22"
- BLKNAME THE_TDC/GEN_Channels_22_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_22" SITE "R11C4D" ;
-#
-UGROUP "FC_23" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_23_Channels/FC;
-LOCATE UGROUP "FC_23" SITE "R7C2D" ;
-UGROUP "hit_23"
- BLKNAME THE_TDC/GEN_Channels_23_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_23" SITE "R8C4D" ;
-#
-
-
-
-
-UGROUP "FC_24" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_24_Channels/FC;
-LOCATE UGROUP "FC_24" SITE "R113C125D" ;
-UGROUP "hit_24"
- BLKNAME THE_TDC/GEN_Channels_24_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_24" SITE "R114C127D" ;
-#
-UGROUP "FC_25" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_25_Channels/FC;
-LOCATE UGROUP "FC_25" SITE "R110C125D" ;
-UGROUP "hit_25"
- BLKNAME THE_TDC/GEN_Channels_25_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_25" SITE "R111C127D" ;
-#
-UGROUP "FC_26" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_26_Channels/FC;
-LOCATE UGROUP "FC_26" SITE "R104C125D" ;
-UGROUP "hit_26"
- BLKNAME THE_TDC/GEN_Channels_26_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_26" SITE "R105C127D" ;
-#
-UGROUP "FC_27" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_27_Channels/FC;
-LOCATE UGROUP "FC_27" SITE "R101C125D" ;
-UGROUP "hit_27"
- BLKNAME THE_TDC/GEN_Channels_27_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_27" SITE "R102C127D" ;
-#
-UGROUP "FC_28" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_28_Channels/FC;
-LOCATE UGROUP "FC_28" SITE "R92C125D" ;
-UGROUP "hit_28"
- BLKNAME THE_TDC/GEN_Channels_28_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_28" SITE "R93C127D" ;
-#
-UGROUP "FC_29" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_29_Channels/FC;
-LOCATE UGROUP "FC_29" SITE "R89C125D" ;
-UGROUP "hit_29"
- BLKNAME THE_TDC/GEN_Channels_29_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_29" SITE "R90C127D" ;
-#
-UGROUP "FC_30" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_30_Channels/FC;
-LOCATE UGROUP "FC_30" SITE "R86C125D" ;
-UGROUP "hit_30"
- BLKNAME THE_TDC/GEN_Channels_30_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_30" SITE "R87C127D" ;
-#
-UGROUP "FC_31" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_31_Channels/FC;
-LOCATE UGROUP "FC_31" SITE "R83C125D" ;
-UGROUP "hit_31"
- BLKNAME THE_TDC/GEN_Channels_31_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_31" SITE "R84C127D" ;
-#
-UGROUP "FC_32" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_32_Channels/FC;
-LOCATE UGROUP "FC_32" SITE "R74C125D" ;
-UGROUP "hit_32"
- BLKNAME THE_TDC/GEN_Channels_32_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_32" SITE "R75C127D" ;
-#
-UGROUP "FC_33" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_33_Channels/FC;
-LOCATE UGROUP "FC_33" SITE "R71C125D" ;
-UGROUP "hit_33"
- BLKNAME THE_TDC/GEN_Channels_33_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_33" SITE "R72C127D" ;
-#
-UGROUP "FC_34" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_34_Channels/FC;
-LOCATE UGROUP "FC_34" SITE "R68C125D" ;
-UGROUP "hit_34"
- BLKNAME THE_TDC/GEN_Channels_34_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_34" SITE "R69C127D" ;
-#
-UGROUP "FC_35" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_35_Channels/FC;
-LOCATE UGROUP "FC_35" SITE "R65C125D" ;
-UGROUP "hit_35"
- BLKNAME THE_TDC/GEN_Channels_35_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_35" SITE "R66C127D" ;
-#
-UGROUP "FC_36" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_36_Channels/FC;
-LOCATE UGROUP "FC_36" SITE "R56C125D" ;
-UGROUP "hit_36"
- BLKNAME THE_TDC/GEN_Channels_36_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_36" SITE "R57C127D" ;
-#
-UGROUP "FC_37" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_37_Channels/FC;
-LOCATE UGROUP "FC_37" SITE "R53C125D" ;
-UGROUP "hit_37"
- BLKNAME THE_TDC/GEN_Channels_37_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_37" SITE "R54C127D" ;
-#
-UGROUP "FC_38" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_38_Channels/FC;
-LOCATE UGROUP "FC_38" SITE "R50C125D" ;
-UGROUP "hit_38"
- BLKNAME THE_TDC/GEN_Channels_38_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_38" SITE "R51C127D" ;
-#
-UGROUP "FC_39" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_39_Channels/FC;
-LOCATE UGROUP "FC_39" SITE "R47C125D" ;
-UGROUP "hit_39"
- BLKNAME THE_TDC/GEN_Channels_39_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_39" SITE "R48C127D" ;
-#
-UGROUP "FC_40" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_40_Channels/FC;
-LOCATE UGROUP "FC_40" SITE "R38C125D" ;
-UGROUP "hit_40"
- BLKNAME THE_TDC/GEN_Channels_40_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_40" SITE "R39C127D" ;
-#
-UGROUP "FC_41" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_41_Channels/FC;
-LOCATE UGROUP "FC_41" SITE "R35C125D" ;
-UGROUP "hit_41"
- BLKNAME THE_TDC/GEN_Channels_41_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_41" SITE "R36C127D" ;
-#
-UGROUP "FC_42" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_42_Channels/FC;
-LOCATE UGROUP "FC_42" SITE "R32C125D" ;
-UGROUP "hit_42"
- BLKNAME THE_TDC/GEN_Channels_42_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_42" SITE "R33C127D" ;
-#
-UGROUP "FC_43" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_43_Channels/FC;
-LOCATE UGROUP "FC_43" SITE "R29C125D" ;
-UGROUP "hit_43"
- BLKNAME THE_TDC/GEN_Channels_43_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_43" SITE "R30C127D" ;
-#
-UGROUP "FC_44" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_44_Channels/FC;
-LOCATE UGROUP "FC_44" SITE "R23C125D" ;
-UGROUP "hit_44"
- BLKNAME THE_TDC/GEN_Channels_44_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_44" SITE "R24C127D" ;
-#
-UGROUP "FC_45" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_45_Channels/FC;
-LOCATE UGROUP "FC_45" SITE "R20C125D" ;
-UGROUP "hit_45"
- BLKNAME THE_TDC/GEN_Channels_45_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_45" SITE "R21C127D" ;
-#
-UGROUP "FC_46" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_46_Channels/FC;
-LOCATE UGROUP "FC_46" SITE "R10C125D" ;
-UGROUP "hit_46"
- BLKNAME THE_TDC/GEN_Channels_46_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_46" SITE "R11C127D" ;
-#
-UGROUP "FC_47" BBOX 1 51
- BLKNAME THE_TDC/GEN_Channels_47_Channels/FC;
-LOCATE UGROUP "FC_47" SITE "R7C125D" ;
-UGROUP "hit_47"
- BLKNAME THE_TDC/GEN_Channels_47_Channels/hit_buf_RNO;
-LOCATE UGROUP "hit_47" SITE "R8C127D" ;
-#
-
-
-
-
-
-
-
-##############################################################################
-## REFERENCE CHANNEL PLACEMENT ##
-##############################################################################
-UGROUP "Ref_Ch" BBOX 1 51
- BLKNAME THE_TDC/The_Reference_Time/FC;
-LOCATE UGROUP "Ref_Ch" SITE "R113C2D" ;
-
-UGROUP "hit_ref_ch"
- BLKNAME THE_TDC/The_Reference_Time/hit_buf_RNO;
-LOCATE UGROUP "hit_ref_ch" SITE "R114C4D" ;
-
-MAXDELAY NET "THE_TDC/The_Reference_Time/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-
-UGROUP "Encoder_ref" BBOX 2 28
- BLKNAME THE_TDC/The_Reference_Time/Encoder;
-LOCATE UGROUP "Encoder_ref" REGION "Region_E&F_0" ;
-
-UGROUP "FIFO_ref" BBOX 2 14
- BLKNAME THE_TDC/The_Reference_Time/FIFO;
-LOCATE UGROUP "FIFO_ref" REGION "Region_E&F_0" ;
-
-#
-MAXDELAY NET "THE_TDC/GEN_Channels_1_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_2_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_3_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_4_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_5_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_6_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_7_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_8_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_9_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_10_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_11_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_12_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_13_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_14_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_15_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_16_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_17_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_18_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_19_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_20_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_21_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_22_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_23_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_24_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_25_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_26_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_27_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_28_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_29_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_30_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_31_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_32_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_33_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_34_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_35_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_36_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_37_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_38_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_39_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_40_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_41_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_42_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_43_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_44_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_45_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_46_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-MAXDELAY NET "THE_TDC/GEN_Channels_47_Channels/hit_buf" 0.700000 nS DATAPATH_ONLY ;
-
-##############################################################################
-## CHANNEL PLACEMENTS ##
-##############################################################################
-UGROUP "Encoder_1" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_1_Channels/Encoder;
-LOCATE UGROUP "Encoder_1" REGION "Region_E&F_0" ;
-UGROUP "FIFO_1" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_1_Channels/FIFO;
-LOCATE UGROUP "FIFO_1" REGION "Region_E&F_0" ;
-UGROUP "Encoder_2" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_2_Channels/Encoder;
-LOCATE UGROUP "Encoder_2" REGION "Region_E&F_1" ;
-UGROUP "FIFO_2" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_2_Channels/FIFO;
-LOCATE UGROUP "FIFO_2" REGION "Region_E&F_1" ;
-UGROUP "Encoder_3" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_3_Channels/Encoder;
-LOCATE UGROUP "Encoder_3" REGION "Region_E&F_1" ;
-UGROUP "FIFO_3" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_3_Channels/FIFO;
-LOCATE UGROUP "FIFO_3" REGION "Region_E&F_1" ;
-UGROUP "Encoder_4" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_4_Channels/Encoder;
-LOCATE UGROUP "Encoder_4" REGION "Region_E&F_1" ;
-UGROUP "FIFO_4" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_4_Channels/FIFO;
-LOCATE UGROUP "FIFO_4" REGION "Region_E&F_1" ;
-UGROUP "Encoder_5" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_5_Channels/Encoder;
-LOCATE UGROUP "Encoder_5" REGION "Region_E&F_1" ;
-UGROUP "FIFO_5" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_5_Channels/FIFO;
-LOCATE UGROUP "FIFO_5" REGION "Region_E&F_1" ;
-UGROUP "Encoder_6" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_6_Channels/Encoder;
-LOCATE UGROUP "Encoder_6" REGION "Region_E&F_2" ;
-UGROUP "FIFO_6" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_6_Channels/FIFO;
-LOCATE UGROUP "FIFO_6" REGION "Region_E&F_2" ;
-UGROUP "Encoder_7" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_7_Channels/Encoder;
-LOCATE UGROUP "Encoder_7" REGION "Region_E&F_2" ;
-UGROUP "FIFO_7" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_7_Channels/FIFO;
-LOCATE UGROUP "FIFO_7" REGION "Region_E&F_2" ;
-UGROUP "Encoder_8" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_8_Channels/Encoder;
-LOCATE UGROUP "Encoder_8" REGION "Region_E&F_2" ;
-UGROUP "FIFO_8" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_8_Channels/FIFO;
-LOCATE UGROUP "FIFO_8" REGION "Region_E&F_2" ;
-UGROUP "Encoder_9" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_9_Channels/Encoder;
-LOCATE UGROUP "Encoder_9" REGION "Region_E&F_2" ;
-UGROUP "FIFO_9" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_9_Channels/FIFO;
-LOCATE UGROUP "FIFO_9" REGION "Region_E&F_2" ;
-UGROUP "Encoder_10" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_10_Channels/Encoder;
-LOCATE UGROUP "Encoder_10" REGION "Region_E&F_3" ;
-UGROUP "FIFO_10" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_10_Channels/FIFO;
-LOCATE UGROUP "FIFO_10" REGION "Region_E&F_3" ;
-UGROUP "Encoder_11" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_11_Channels/Encoder;
-LOCATE UGROUP "Encoder_11" REGION "Region_E&F_3" ;
-UGROUP "FIFO_11" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_11_Channels/FIFO;
-LOCATE UGROUP "FIFO_11" REGION "Region_E&F_3" ;
-UGROUP "Encoder_12" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_12_Channels/Encoder;
-LOCATE UGROUP "Encoder_12" REGION "Region_E&F_3" ;
-UGROUP "FIFO_12" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_12_Channels/FIFO;
-LOCATE UGROUP "FIFO_12" REGION "Region_E&F_3" ;
-UGROUP "Encoder_13" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_13_Channels/Encoder;
-LOCATE UGROUP "Encoder_13" REGION "Region_E&F_3" ;
-UGROUP "FIFO_13" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_13_Channels/FIFO;
-LOCATE UGROUP "FIFO_13" REGION "Region_E&F_3" ;
-UGROUP "Encoder_14" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_14_Channels/Encoder;
-LOCATE UGROUP "Encoder_14" REGION "Region_E&F_4" ;
-UGROUP "FIFO_14" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_14_Channels/FIFO;
-LOCATE UGROUP "FIFO_14" REGION "Region_E&F_4" ;
-UGROUP "Encoder_15" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_15_Channels/Encoder;
-LOCATE UGROUP "Encoder_15" REGION "Region_E&F_4" ;
-UGROUP "FIFO_15" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_15_Channels/FIFO;
-LOCATE UGROUP "FIFO_15" REGION "Region_E&F_4" ;
-UGROUP "Encoder_16" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_16_Channels/Encoder;
-LOCATE UGROUP "Encoder_16" REGION "Region_E&F_4" ;
-UGROUP "FIFO_16" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_16_Channels/FIFO;
-LOCATE UGROUP "FIFO_16" REGION "Region_E&F_4" ;
-UGROUP "Encoder_17" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_17_Channels/Encoder;
-LOCATE UGROUP "Encoder_17" REGION "Region_E&F_4" ;
-UGROUP "FIFO_17" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_17_Channels/FIFO;
-LOCATE UGROUP "FIFO_17" REGION "Region_E&F_4" ;
-UGROUP "Encoder_18" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_18_Channels/Encoder;
-LOCATE UGROUP "Encoder_18" REGION "Region_E&F_5" ;
-UGROUP "FIFO_18" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_18_Channels/FIFO;
-LOCATE UGROUP "FIFO_18" REGION "Region_E&F_5" ;
-UGROUP "Encoder_19" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_19_Channels/Encoder;
-LOCATE UGROUP "Encoder_19" REGION "Region_E&F_5" ;
-UGROUP "FIFO_19" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_19_Channels/FIFO;
-LOCATE UGROUP "FIFO_19" REGION "Region_E&F_5" ;
-UGROUP "Encoder_20" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_20_Channels/Encoder;
-LOCATE UGROUP "Encoder_20" REGION "Region_E&F_6" ;
-UGROUP "FIFO_20" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_20_Channels/FIFO;
-LOCATE UGROUP "FIFO_20" REGION "Region_E&F_6" ;
-UGROUP "Encoder_21" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_21_Channels/Encoder;
-LOCATE UGROUP "Encoder_21" REGION "Region_E&F_6" ;
-UGROUP "FIFO_21" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_21_Channels/FIFO;
-LOCATE UGROUP "FIFO_21" REGION "Region_E&F_6" ;
-UGROUP "Encoder_22" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_22_Channels/Encoder;
-LOCATE UGROUP "Encoder_22" REGION "Region_E&F_6" ;
-UGROUP "FIFO_22" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_22_Channels/FIFO;
-LOCATE UGROUP "FIFO_22" REGION "Region_E&F_6" ;
-UGROUP "Encoder_23" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_23_Channels/Encoder;
-LOCATE UGROUP "Encoder_23" REGION "Region_E&F_6" ;
-UGROUP "FIFO_23" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_23_Channels/FIFO;
-LOCATE UGROUP "FIFO_23" REGION "Region_E&F_6" ;
-UGROUP "Encoder_24" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_24_Channels/Encoder;
-LOCATE UGROUP "Encoder_24" REGION "Region_E&F_7" ;
-UGROUP "FIFO_24" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_24_Channels/FIFO;
-LOCATE UGROUP "FIFO_24" REGION "Region_E&F_7" ;
-UGROUP "Encoder_25" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_25_Channels/Encoder;
-LOCATE UGROUP "Encoder_25" REGION "Region_E&F_7" ;
-UGROUP "FIFO_25" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_25_Channels/FIFO;
-LOCATE UGROUP "FIFO_25" REGION "Region_E&F_7" ;
-UGROUP "Encoder_26" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_26_Channels/Encoder;
-LOCATE UGROUP "Encoder_26" REGION "Region_E&F_8" ;
-UGROUP "FIFO_26" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_26_Channels/FIFO;
-LOCATE UGROUP "FIFO_26" REGION "Region_E&F_8" ;
-UGROUP "Encoder_27" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_27_Channels/Encoder;
-LOCATE UGROUP "Encoder_27" REGION "Region_E&F_8" ;
-UGROUP "FIFO_27" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_27_Channels/FIFO;
-LOCATE UGROUP "FIFO_27" REGION "Region_E&F_8" ;
-UGROUP "Encoder_28" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_28_Channels/Encoder;
-LOCATE UGROUP "Encoder_28" REGION "Region_E&F_8" ;
-UGROUP "FIFO_28" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_28_Channels/FIFO;
-LOCATE UGROUP "FIFO_28" REGION "Region_E&F_8" ;
-UGROUP "Encoder_29" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_29_Channels/Encoder;
-LOCATE UGROUP "Encoder_29" REGION "Region_E&F_8" ;
-UGROUP "FIFO_29" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_29_Channels/FIFO;
-LOCATE UGROUP "FIFO_29" REGION "Region_E&F_8" ;
-UGROUP "Encoder_30" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_30_Channels/Encoder;
-LOCATE UGROUP "Encoder_30" REGION "Region_E&F_9" ;
-UGROUP "FIFO_30" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_30_Channels/FIFO;
-LOCATE UGROUP "FIFO_30" REGION "Region_E&F_9" ;
-UGROUP "Encoder_31" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_31_Channels/Encoder;
-LOCATE UGROUP "Encoder_31" REGION "Region_E&F_9" ;
-UGROUP "FIFO_31" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_31_Channels/FIFO;
-LOCATE UGROUP "FIFO_31" REGION "Region_E&F_9" ;
-UGROUP "Encoder_32" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_32_Channels/Encoder;
-LOCATE UGROUP "Encoder_32" REGION "Region_E&F_9" ;
-UGROUP "FIFO_32" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_32_Channels/FIFO;
-LOCATE UGROUP "FIFO_32" REGION "Region_E&F_9" ;
-UGROUP "Encoder_33" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_33_Channels/Encoder;
-LOCATE UGROUP "Encoder_33" REGION "Region_E&F_9" ;
-UGROUP "FIFO_33" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_33_Channels/FIFO;
-LOCATE UGROUP "FIFO_33" REGION "Region_E&F_9" ;
-UGROUP "Encoder_34" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_34_Channels/Encoder;
-LOCATE UGROUP "Encoder_34" REGION "Region_E&F_10" ;
-UGROUP "FIFO_34" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_34_Channels/FIFO;
-LOCATE UGROUP "FIFO_34" REGION "Region_E&F_10" ;
-UGROUP "Encoder_35" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_35_Channels/Encoder;
-LOCATE UGROUP "Encoder_35" REGION "Region_E&F_10" ;
-UGROUP "FIFO_35" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_35_Channels/FIFO;
-LOCATE UGROUP "FIFO_35" REGION "Region_E&F_10" ;
-UGROUP "Encoder_36" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_36_Channels/Encoder;
-LOCATE UGROUP "Encoder_36" REGION "Region_E&F_10" ;
-UGROUP "FIFO_36" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_36_Channels/FIFO;
-LOCATE UGROUP "FIFO_36" REGION "Region_E&F_10" ;
-UGROUP "Encoder_37" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_37_Channels/Encoder;
-LOCATE UGROUP "Encoder_37" REGION "Region_E&F_10" ;
-UGROUP "FIFO_37" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_37_Channels/FIFO;
-LOCATE UGROUP "FIFO_37" REGION "Region_E&F_10" ;
-UGROUP "Encoder_38" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_38_Channels/Encoder;
-LOCATE UGROUP "Encoder_38" REGION "Region_E&F_11" ;
-UGROUP "FIFO_38" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_38_Channels/FIFO;
-LOCATE UGROUP "FIFO_38" REGION "Region_E&F_11" ;
-UGROUP "Encoder_39" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_39_Channels/Encoder;
-LOCATE UGROUP "Encoder_39" REGION "Region_E&F_11" ;
-UGROUP "FIFO_39" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_39_Channels/FIFO;
-LOCATE UGROUP "FIFO_39" REGION "Region_E&F_11" ;
-UGROUP "Encoder_40" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_40_Channels/Encoder;
-LOCATE UGROUP "Encoder_40" REGION "Region_E&F_11" ;
-UGROUP "FIFO_40" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_40_Channels/FIFO;
-LOCATE UGROUP "FIFO_40" REGION "Region_E&F_11" ;
-UGROUP "Encoder_41" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_41_Channels/Encoder;
-LOCATE UGROUP "Encoder_41" REGION "Region_E&F_11" ;
-UGROUP "FIFO_41" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_41_Channels/FIFO;
-LOCATE UGROUP "FIFO_41" REGION "Region_E&F_11" ;
-UGROUP "Encoder_42" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_42_Channels/Encoder;
-LOCATE UGROUP "Encoder_42" REGION "Region_E&F_12" ;
-UGROUP "FIFO_42" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_42_Channels/FIFO;
-LOCATE UGROUP "FIFO_42" REGION "Region_E&F_12" ;
-UGROUP "Encoder_43" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_43_Channels/Encoder;
-LOCATE UGROUP "Encoder_43" REGION "Region_E&F_12" ;
-UGROUP "FIFO_43" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_43_Channels/FIFO;
-LOCATE UGROUP "FIFO_43" REGION "Region_E&F_12" ;
-UGROUP "Encoder_44" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_44_Channels/Encoder;
-LOCATE UGROUP "Encoder_44" REGION "Region_E&F_13" ;
-UGROUP "FIFO_44" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_44_Channels/FIFO;
-LOCATE UGROUP "FIFO_44" REGION "Region_E&F_13" ;
-UGROUP "Encoder_45" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_45_Channels/Encoder;
-LOCATE UGROUP "Encoder_45" REGION "Region_E&F_13" ;
-UGROUP "FIFO_45" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_45_Channels/FIFO;
-LOCATE UGROUP "FIFO_45" REGION "Region_E&F_13" ;
-UGROUP "Encoder_46" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_46_Channels/Encoder;
-LOCATE UGROUP "Encoder_46" REGION "Region_E&F_13" ;
-UGROUP "FIFO_46" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_46_Channels/FIFO;
-LOCATE UGROUP "FIFO_46" REGION "Region_E&F_13" ;
-UGROUP "Encoder_47" BBOX 2 28
- BLKNAME THE_TDC/GEN_Channels_47_Channels/Encoder;
-LOCATE UGROUP "Encoder_47" REGION "Region_E&F_13" ;
-UGROUP "FIFO_47" BBOX 2 14
- BLKNAME THE_TDC/GEN_Channels_47_Channels/FIFO;
-LOCATE UGROUP "FIFO_47" REGION "Region_E&F_13" ;
-
-
-##############################################################################
-## FF ARRAY ENABLE PLACEMENT ##
-##############################################################################
-UGROUP "ff_en_0" BBOX 1 1
- BLKNAME I_686_lat_r;
-LOCATE UGROUP "ff_en_0" SITE "R113C27D" ; ##
-UGROUP "ff_en_1" BBOX 1 1
- BLKNAME I_693_lat_r;
-LOCATE UGROUP "ff_en_1" SITE "R110C27D" ; ##
-UGROUP "ff_en_2" BBOX 1 1
- BLKNAME I_692_lat_r;
-LOCATE UGROUP "ff_en_2" SITE "R104C27D" ; ##
-UGROUP "ff_en_3" BBOX 1 1
- BLKNAME I_691_lat_r;
-LOCATE UGROUP "ff_en_3" SITE "R101C27D" ; ##
-UGROUP "ff_en_4" BBOX 1 1
- BLKNAME I_690_lat_r;
-LOCATE UGROUP "ff_en_4" SITE "R92C27D" ; ##
-UGROUP "ff_en_5" BBOX 1 1
- BLKNAME I_689_lat_r;
-LOCATE UGROUP "ff_en_5" SITE "R89C27D" ; ##
-UGROUP "ff_en_6" BBOX 1 1
- BLKNAME I_688_lat_r;
-LOCATE UGROUP "ff_en_6" SITE "R86C27D" ; ##
-UGROUP "ff_en_7" BBOX 1 1
- BLKNAME I_687_lat_r;
-LOCATE UGROUP "ff_en_7" SITE "R83C27D" ; ##
-
-
-#UGROUP "ff_en_8" BBOX 1 1
-# BLKNAME I_2161_lat_r;
-#LOCATE UGROUP "ff_en_8" SITE "R74C27D" ; ##
-#UGROUP "ff_en_9" BBOX 1 1
-# BLKNAME I_2160_lat_r;
-#LOCATE UGROUP "ff_en_9" SITE "R71C27D" ; ##
-#UGROUP "ff_en_10" BBOX 1 1
-# BLKNAME I_2174_lat_r;
-#LOCATE UGROUP "ff_en_10" SITE "R68C27D" ; ##
-#UGROUP "ff_en_11" BBOX 1 1
-# BLKNAME I_2173_lat_r;
-#LOCATE UGROUP "ff_en_11" SITE "R65C27D" ; ##
-#UGROUP "ff_en_12" BBOX 1 1
-# BLKNAME I_2172_lat_r;
-#LOCATE UGROUP "ff_en_12" SITE "R56C27D" ; ##
-#UGROUP "ff_en_13" BBOX 1 1
-# BLKNAME I_2171_lat_r;
-#LOCATE UGROUP "ff_en_13" SITE "R53C27D" ; ##
-#UGROUP "ff_en_14" BBOX 1 1
-# BLKNAME I_2170_lat_r;
-#LOCATE UGROUP "ff_en_14" SITE "R50C27D" ; ##
-#UGROUP "ff_en_15" BBOX 1 1
-# BLKNAME I_2169_lat_r;
-#LOCATE UGROUP "ff_en_15" SITE "R47C27D" ; ##
-
-
-#UGROUP "ff_en_16" BBOX 1 1
-# BLKNAME I_2170_lat_r;
-#LOCATE UGROUP "ff_en_16" SITE "R38C27D" ; ##
-#UGROUP "ff_en_17" BBOX 1 1
-# BLKNAME I_2169_lat_r;
-#LOCATE UGROUP "ff_en_17" SITE "R35C27D" ; ##
-#UGROUP "ff_en_18" BBOX 1 1
-# BLKNAME I_2168_lat_r;
-#LOCATE UGROUP "ff_en_18" SITE "R32C27D" ; ##
-#UGROUP "ff_en_19" BBOX 1 1
-# BLKNAME I_2167_lat_r;
-#LOCATE UGROUP "ff_en_19" SITE "R29C27D" ; ##
-#UGROUP "ff_en_20" BBOX 1 1
-# BLKNAME I_1234_lat_r;
-#LOCATE UGROUP "ff_en_20" SITE "R23C27D" ; ##
-#UGROUP "ff_en_21" BBOX 1 1
-# BLKNAME I_1233_lat_r;
-#LOCATE UGROUP "ff_en_21" SITE "R20C27D" ; ##
-#UGROUP "ff_en_22" BBOX 1 1
-# BLKNAME I_1232_lat_r;
-#LOCATE UGROUP "ff_en_22" SITE "R10C27D" ; ##
-#UGROUP "ff_en_23" BBOX 1 1
-# BLKNAME I_1231_lat_r;
-#LOCATE UGROUP "ff_en_23" SITE "R7C27D" ; ##
-
-
-#UGROUP "ff_en_24" BBOX 1 1
-# BLKNAME I_1230_lat_r;
-#LOCATE UGROUP "ff_en_24" SITE "R113C150D" ; ##
-#UGROUP "ff_en_25" BBOX 1 1
-# BLKNAME I_1229_lat_r;
-#LOCATE UGROUP "ff_en_25" SITE "R110C150D" ; ##
-#UGROUP "ff_en_26" BBOX 1 1
-# BLKNAME I_1228_lat_r;
-#LOCATE UGROUP "ff_en_26" SITE "R104C150D" ; ##
-#UGROUP "ff_en_27" BBOX 1 1
-# BLKNAME I_1227_lat_r;
-#LOCATE UGROUP "ff_en_27" SITE "R101C150D" ; ##
-#UGROUP "ff_en_28" BBOX 1 1
-# BLKNAME I_1226_lat_r;
-#LOCATE UGROUP "ff_en_28" SITE "R92C150D" ; ##
-#UGROUP "ff_en_29" BBOX 1 1
-# BLKNAME I_1225_lat_r;
-#LOCATE UGROUP "ff_en_29" SITE "R89C150D" ; ##
-#UGROUP "ff_en_30" BBOX 1 1
-# BLKNAME I_1223_lat_r;
-#LOCATE UGROUP "ff_en_30" SITE "R86C150D" ; ##
-#UGROUP "ff_en_31" BBOX 1 1
-# BLKNAME I_1222_lat_r;
-#LOCATE UGROUP "ff_en_31" SITE "R83C150D" ; ##
-
-
-#UGROUP "ff_en_32" BBOX 1 1
-# BLKNAME I_1221_lat_r;
-#LOCATE UGROUP "ff_en_32" SITE "R74C150D" ; ##
-#UGROUP "ff_en_33" BBOX 1 1
-# BLKNAME I_1220_lat_r;
-#LOCATE UGROUP "ff_en_33" SITE "R71C150D" ; ##
-#UGROUP "ff_en_34" BBOX 1 1
-# BLKNAME I_1219_lat_r;
-#LOCATE UGROUP "ff_en_34" SITE "R68C150D" ; ##
-#UGROUP "ff_en_35" BBOX 1 1
-# BLKNAME I_1218_lat_r;
-#LOCATE UGROUP "ff_en_35" SITE "R65C150D" ; ##
-#UGROUP "ff_en_36" BBOX 1 1
-# BLKNAME I_1217_lat_r;
-#LOCATE UGROUP "ff_en_36" SITE "R56C150D" ; ##
-#UGROUP "ff_en_37" BBOX 1 1
-# BLKNAME I_1216_lat_r;
-#LOCATE UGROUP "ff_en_37" SITE "R53C150D" ; ##
-#UGROUP "ff_en_38" BBOX 1 1
-# BLKNAME I_1215_lat_r;
-#LOCATE UGROUP "ff_en_38" SITE "R50C150D" ; ##
-#UGROUP "ff_en_39" BBOX 1 1
-# BLKNAME I_1214_lat_r;
-#LOCATE UGROUP "ff_en_39" SITE "R47C150D" ; ##
-
-
-#UGROUP "ff_en_40" BBOX 1 1
-# BLKNAME I_1212_lat_r;
-#LOCATE UGROUP "ff_en_40" SITE "R38C150D" ; ##
-#UGROUP "ff_en_41" BBOX 1 1
-# BLKNAME I_1211_lat_r;
-#LOCATE UGROUP "ff_en_41" SITE "R35C150D" ; ##
-#UGROUP "ff_en_42" BBOX 1 1
-# BLKNAME I_1210_lat_r;
-#LOCATE UGROUP "ff_en_42" SITE "R32C150D" ; ##
-#UGROUP "ff_en_43" BBOX 1 1
-# BLKNAME I_1209_lat_r;
-#LOCATE UGROUP "ff_en_43" SITE "R29C150D" ; ##
-#UGROUP "ff_en_44" BBOX 1 1
-# BLKNAME I_1208_lat_r;
-#LOCATE UGROUP "ff_en_44" SITE "R23C150D" ; ##
-#UGROUP "ff_en_45" BBOX 1 1
-# BLKNAME I_1207_lat_r;
-#LOCATE UGROUP "ff_en_45" SITE "R20C150D" ; ##
-#UGROUP "ff_en_46" BBOX 1 1
-# BLKNAME I_1206_lat_r;
-#LOCATE UGROUP "ff_en_46" SITE "R10C150D" ; ##
-#UGROUP "ff_en_47" BBOX 1 1
-# BLKNAME I_1205_lat_r;
-#LOCATE UGROUP "ff_en_47" SITE "R7C150D" ; ##
-
-
-
-
-##############################################################################
-
-MULTICYCLE FROM CELL "THE_TDC/The_Reset_Generator/reset_cnt_*" 3.000000 X ;
-MULTICYCLE FROM CELL "THE_TDC/The_Reset_Generator/RESET_OUT_*" 3.000000 X ;
-MULTICYCLE FROM CELL "THE_TDC/The_Reset_Generator/reset_i*" 3.000000 X ;
-#MULTICYCLE TO PORT "TEST_LINE_*" 2.000000 X ;
-
-
-##############################################################################
-## PIN PLACEMENT FOR CORELL ##
-##############################################################################
-
-LOCATE COMP "MOSI_OUT" SITE "G6"; #"DQUL_7" DQSUL0_C #88 #IN_L_SDIb
-LOCATE COMP "SCK_OUT" SITE "E4"; #"DQUL_3" DQUL0_3 #80 #OUT_L_SDOb
-LOCATE COMP "CS_OUT_0" SITE "C3"; #"DQUL_4" DQUL0_4 #82 #OUT_L_SCK
-LOCATE COMP "CS_OUT_1" SITE "D3"; #"DQUL_5" DQUL0_5 #84 #OUT_L_SCKb
-LOCATE COMP "CS_OUT_2" SITE "U24"; #"DQLR_32" DQLR2_6 #186 #OUT_H_SCK
-LOCATE COMP "CS_OUT_3" SITE "V24"; #"DQLR_33" DQLR2_7 #188 #OUT_H_SCKb
-
-IOBUF PORT "MOSI_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
-IOBUF PORT "SCK_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP;
-DEFINE PORT GROUP "CS_group" "CS_OUT_*" ;
-IOBUF GROUP "CS_group" IO_TYPE=LVCMOS25 PULLMODE=UP;
+++ /dev/null
-
-# implementation: "workdir"
-impl -add workdir -type fpga
-
-# device options
-set_option -technology LATTICE-ECP3
-set_option -part LFE3_150EA
-set_option -package FN672C
-set_option -speed_grade -8
-set_option -part_companion ""
-
-# compilation/mapping options
-set_option -default_enum_encoding sequential
-set_option -symbolic_fsm_compiler 1
-set_option -top_module "trb3_periph"
-set_option -resource_sharing true
-
-# map options
-set_option -frequency 200
-set_option -fanout_limit 100
-set_option -disable_io_insertion 0
-set_option -retiming 0
-set_option -pipe 0
-#set_option -force_gsr
-set_option -force_gsr false
-set_option -fixgatedclocks 3
-set_option -fixgeneratedclocks 3
-set_option -compiler_compatible true
-
-
-# simulation options
-set_option -write_verilog 0
-set_option -write_vhdl 1
-
-# automatic place and route (vendor) options
-set_option -write_apr_constraint 0
-
-# set result format/file last
-project -result_format "edif"
-project -result_file "workdir/trb3_periph.edf"
-
-#implementation attributes
-
-set_option -vlog_std v2001
-set_option -project_relative_includes 1
-impl -active "workdir"
-
-####################
-
-
-
-#add_file options
-
-add_file -vhdl -lib work "version.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
-add_file -vhdl -lib "work" "../base/trb3_components.vhd"
-
-add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
-add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
-
-add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
-add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
-add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
-add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
-
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd"
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd"
-
-add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd"
-
-add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
-add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
-add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
-
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd"
-
-add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd"
-
-
-add_file -vhdl -lib "work" "source/Adder_304.vhd"
-add_file -vhdl -lib "work" "source/bit_sync.vhd"
-add_file -vhdl -lib "work" "source/Channel.vhd"
-#add_file -vhdl -lib "work" "source/corell.vhd"
-
-add_file -vhdl -lib "work" "source/Encoder_304_Bit.vhd"
-#add_file -vhdl -lib "work" "source/Encoder_304_ROMsuz.vhd"
-#add_file -vhdl -lib "work" "source/Encoder_304_Sngl_ROMsuz.vhd"
-
-add_file -vhdl -lib "work" "source/FIFO_32x512_OutReg.vhd"
-#add_file -vhdl -lib "work" "source/pll_100_in_5_out.vhd"
-add_file -vhdl -lib "work" "source/Reference_channel.vhd"
-add_file -vhdl -lib "work" "source/reset_generator.vhd"
-
-add_file -vhdl -lib "work" "source/ROM_Encoder.vhd"
-
-add_file -vhdl -lib "work" "source/ROM_FIFO.vhd"
-
-add_file -vhdl -lib "work" "source/TDC.vhd"
-add_file -vhdl -lib "work" "source/trb3_periph.vhd"
-add_file -vhdl -lib "work" "source/up_counter.vhd"
-
+++ /dev/null
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-
-entity Adder_304 is
- port (CLK : in std_logic;
- RESET : in std_logic;
- DataA : in std_logic_vector(303 downto 0);
- DataB : in std_logic_vector(303 downto 0);
- ClkEn : in std_logic;
- Result : out std_logic_vector(303 downto 0)
- );
-end Adder_304;
-
-architecture Structure of Adder_304 is
-
--- internal signal declarations
- signal r0_sum : std_logic_vector(303 downto 0);
- signal tsum : std_logic_vector(303 downto 0);
- signal co : std_logic_vector(151 downto 0);
- signal scuba_vlo : std_logic;
-
--- local component declarations
- component FADD2B
- port (A0 : in std_logic;
- A1 : in std_logic;
- B0 : in std_logic;
- B1 : in std_logic;
- CI : in std_logic;
- COUT : out std_logic;
- S0 : out std_logic;
- S1 : out std_logic);
- end component;
- component FD1P3DX
- port (D : in std_logic;
- SP : in std_logic;
- CK : in std_logic;
- CD : in std_logic;
- Q : out std_logic);
- end component;
- component VLO
- port (Z : out std_logic);
- end component;
-
- attribute GSR : string;
- attribute GSR of FF_303 : label is "ENABLED";
- attribute GSR of FF_302 : label is "ENABLED";
- attribute GSR of FF_301 : label is "ENABLED";
- attribute GSR of FF_300 : label is "ENABLED";
- attribute GSR of FF_299 : label is "ENABLED";
- attribute GSR of FF_298 : label is "ENABLED";
- attribute GSR of FF_297 : label is "ENABLED";
- attribute GSR of FF_296 : label is "ENABLED";
- attribute GSR of FF_295 : label is "ENABLED";
- attribute GSR of FF_294 : label is "ENABLED";
- attribute GSR of FF_293 : label is "ENABLED";
- attribute GSR of FF_292 : label is "ENABLED";
- attribute GSR of FF_291 : label is "ENABLED";
- attribute GSR of FF_290 : label is "ENABLED";
- attribute GSR of FF_289 : label is "ENABLED";
- attribute GSR of FF_288 : label is "ENABLED";
- attribute GSR of FF_287 : label is "ENABLED";
- attribute GSR of FF_286 : label is "ENABLED";
- attribute GSR of FF_285 : label is "ENABLED";
- attribute GSR of FF_284 : label is "ENABLED";
- attribute GSR of FF_283 : label is "ENABLED";
- attribute GSR of FF_282 : label is "ENABLED";
- attribute GSR of FF_281 : label is "ENABLED";
- attribute GSR of FF_280 : label is "ENABLED";
- attribute GSR of FF_279 : label is "ENABLED";
- attribute GSR of FF_278 : label is "ENABLED";
- attribute GSR of FF_277 : label is "ENABLED";
- attribute GSR of FF_276 : label is "ENABLED";
- attribute GSR of FF_275 : label is "ENABLED";
- attribute GSR of FF_274 : label is "ENABLED";
- attribute GSR of FF_273 : label is "ENABLED";
- attribute GSR of FF_272 : label is "ENABLED";
- attribute GSR of FF_271 : label is "ENABLED";
- attribute GSR of FF_270 : label is "ENABLED";
- attribute GSR of FF_269 : label is "ENABLED";
- attribute GSR of FF_268 : label is "ENABLED";
- attribute GSR of FF_267 : label is "ENABLED";
- attribute GSR of FF_266 : label is "ENABLED";
- attribute GSR of FF_265 : label is "ENABLED";
- attribute GSR of FF_264 : label is "ENABLED";
- attribute GSR of FF_263 : label is "ENABLED";
- attribute GSR of FF_262 : label is "ENABLED";
- attribute GSR of FF_261 : label is "ENABLED";
- attribute GSR of FF_260 : label is "ENABLED";
- attribute GSR of FF_259 : label is "ENABLED";
- attribute GSR of FF_258 : label is "ENABLED";
- attribute GSR of FF_257 : label is "ENABLED";
- attribute GSR of FF_256 : label is "ENABLED";
- attribute GSR of FF_255 : label is "ENABLED";
- attribute GSR of FF_254 : label is "ENABLED";
- attribute GSR of FF_253 : label is "ENABLED";
- attribute GSR of FF_252 : label is "ENABLED";
- attribute GSR of FF_251 : label is "ENABLED";
- attribute GSR of FF_250 : label is "ENABLED";
- attribute GSR of FF_249 : label is "ENABLED";
- attribute GSR of FF_248 : label is "ENABLED";
- attribute GSR of FF_247 : label is "ENABLED";
- attribute GSR of FF_246 : label is "ENABLED";
- attribute GSR of FF_245 : label is "ENABLED";
- attribute GSR of FF_244 : label is "ENABLED";
- attribute GSR of FF_243 : label is "ENABLED";
- attribute GSR of FF_242 : label is "ENABLED";
- attribute GSR of FF_241 : label is "ENABLED";
- attribute GSR of FF_240 : label is "ENABLED";
- attribute GSR of FF_239 : label is "ENABLED";
- attribute GSR of FF_238 : label is "ENABLED";
- attribute GSR of FF_237 : label is "ENABLED";
- attribute GSR of FF_236 : label is "ENABLED";
- attribute GSR of FF_235 : label is "ENABLED";
- attribute GSR of FF_234 : label is "ENABLED";
- attribute GSR of FF_233 : label is "ENABLED";
- attribute GSR of FF_232 : label is "ENABLED";
- attribute GSR of FF_231 : label is "ENABLED";
- attribute GSR of FF_230 : label is "ENABLED";
- attribute GSR of FF_229 : label is "ENABLED";
- attribute GSR of FF_228 : label is "ENABLED";
- attribute GSR of FF_227 : label is "ENABLED";
- attribute GSR of FF_226 : label is "ENABLED";
- attribute GSR of FF_225 : label is "ENABLED";
- attribute GSR of FF_224 : label is "ENABLED";
- attribute GSR of FF_223 : label is "ENABLED";
- attribute GSR of FF_222 : label is "ENABLED";
- attribute GSR of FF_221 : label is "ENABLED";
- attribute GSR of FF_220 : label is "ENABLED";
- attribute GSR of FF_219 : label is "ENABLED";
- attribute GSR of FF_218 : label is "ENABLED";
- attribute GSR of FF_217 : label is "ENABLED";
- attribute GSR of FF_216 : label is "ENABLED";
- attribute GSR of FF_215 : label is "ENABLED";
- attribute GSR of FF_214 : label is "ENABLED";
- attribute GSR of FF_213 : label is "ENABLED";
- attribute GSR of FF_212 : label is "ENABLED";
- attribute GSR of FF_211 : label is "ENABLED";
- attribute GSR of FF_210 : label is "ENABLED";
- attribute GSR of FF_209 : label is "ENABLED";
- attribute GSR of FF_208 : label is "ENABLED";
- attribute GSR of FF_207 : label is "ENABLED";
- attribute GSR of FF_206 : label is "ENABLED";
- attribute GSR of FF_205 : label is "ENABLED";
- attribute GSR of FF_204 : label is "ENABLED";
- attribute GSR of FF_203 : label is "ENABLED";
- attribute GSR of FF_202 : label is "ENABLED";
- attribute GSR of FF_201 : label is "ENABLED";
- attribute GSR of FF_200 : label is "ENABLED";
- attribute GSR of FF_199 : label is "ENABLED";
- attribute GSR of FF_198 : label is "ENABLED";
- attribute GSR of FF_197 : label is "ENABLED";
- attribute GSR of FF_196 : label is "ENABLED";
- attribute GSR of FF_195 : label is "ENABLED";
- attribute GSR of FF_194 : label is "ENABLED";
- attribute GSR of FF_193 : label is "ENABLED";
- attribute GSR of FF_192 : label is "ENABLED";
- attribute GSR of FF_191 : label is "ENABLED";
- attribute GSR of FF_190 : label is "ENABLED";
- attribute GSR of FF_189 : label is "ENABLED";
- attribute GSR of FF_188 : label is "ENABLED";
- attribute GSR of FF_187 : label is "ENABLED";
- attribute GSR of FF_186 : label is "ENABLED";
- attribute GSR of FF_185 : label is "ENABLED";
- attribute GSR of FF_184 : label is "ENABLED";
- attribute GSR of FF_183 : label is "ENABLED";
- attribute GSR of FF_182 : label is "ENABLED";
- attribute GSR of FF_181 : label is "ENABLED";
- attribute GSR of FF_180 : label is "ENABLED";
- attribute GSR of FF_179 : label is "ENABLED";
- attribute GSR of FF_178 : label is "ENABLED";
- attribute GSR of FF_177 : label is "ENABLED";
- attribute GSR of FF_176 : label is "ENABLED";
- attribute GSR of FF_175 : label is "ENABLED";
- attribute GSR of FF_174 : label is "ENABLED";
- attribute GSR of FF_173 : label is "ENABLED";
- attribute GSR of FF_172 : label is "ENABLED";
- attribute GSR of FF_171 : label is "ENABLED";
- attribute GSR of FF_170 : label is "ENABLED";
- attribute GSR of FF_169 : label is "ENABLED";
- attribute GSR of FF_168 : label is "ENABLED";
- attribute GSR of FF_167 : label is "ENABLED";
- attribute GSR of FF_166 : label is "ENABLED";
- attribute GSR of FF_165 : label is "ENABLED";
- attribute GSR of FF_164 : label is "ENABLED";
- attribute GSR of FF_163 : label is "ENABLED";
- attribute GSR of FF_162 : label is "ENABLED";
- attribute GSR of FF_161 : label is "ENABLED";
- attribute GSR of FF_160 : label is "ENABLED";
- attribute GSR of FF_159 : label is "ENABLED";
- attribute GSR of FF_158 : label is "ENABLED";
- attribute GSR of FF_157 : label is "ENABLED";
- attribute GSR of FF_156 : label is "ENABLED";
- attribute GSR of FF_155 : label is "ENABLED";
- attribute GSR of FF_154 : label is "ENABLED";
- attribute GSR of FF_153 : label is "ENABLED";
- attribute GSR of FF_152 : label is "ENABLED";
- attribute GSR of FF_151 : label is "ENABLED";
- attribute GSR of FF_150 : label is "ENABLED";
- attribute GSR of FF_149 : label is "ENABLED";
- attribute GSR of FF_148 : label is "ENABLED";
- attribute GSR of FF_147 : label is "ENABLED";
- attribute GSR of FF_146 : label is "ENABLED";
- attribute GSR of FF_145 : label is "ENABLED";
- attribute GSR of FF_144 : label is "ENABLED";
- attribute GSR of FF_143 : label is "ENABLED";
- attribute GSR of FF_142 : label is "ENABLED";
- attribute GSR of FF_141 : label is "ENABLED";
- attribute GSR of FF_140 : label is "ENABLED";
- attribute GSR of FF_139 : label is "ENABLED";
- attribute GSR of FF_138 : label is "ENABLED";
- attribute GSR of FF_137 : label is "ENABLED";
- attribute GSR of FF_136 : label is "ENABLED";
- attribute GSR of FF_135 : label is "ENABLED";
- attribute GSR of FF_134 : label is "ENABLED";
- attribute GSR of FF_133 : label is "ENABLED";
- attribute GSR of FF_132 : label is "ENABLED";
- attribute GSR of FF_131 : label is "ENABLED";
- attribute GSR of FF_130 : label is "ENABLED";
- attribute GSR of FF_129 : label is "ENABLED";
- attribute GSR of FF_128 : label is "ENABLED";
- attribute GSR of FF_127 : label is "ENABLED";
- attribute GSR of FF_126 : label is "ENABLED";
- attribute GSR of FF_125 : label is "ENABLED";
- attribute GSR of FF_124 : label is "ENABLED";
- attribute GSR of FF_123 : label is "ENABLED";
- attribute GSR of FF_122 : label is "ENABLED";
- attribute GSR of FF_121 : label is "ENABLED";
- attribute GSR of FF_120 : label is "ENABLED";
- attribute GSR of FF_119 : label is "ENABLED";
- attribute GSR of FF_118 : label is "ENABLED";
- attribute GSR of FF_117 : label is "ENABLED";
- attribute GSR of FF_116 : label is "ENABLED";
- attribute GSR of FF_115 : label is "ENABLED";
- attribute GSR of FF_114 : label is "ENABLED";
- attribute GSR of FF_113 : label is "ENABLED";
- attribute GSR of FF_112 : label is "ENABLED";
- attribute GSR of FF_111 : label is "ENABLED";
- attribute GSR of FF_110 : label is "ENABLED";
- attribute GSR of FF_109 : label is "ENABLED";
- attribute GSR of FF_108 : label is "ENABLED";
- attribute GSR of FF_107 : label is "ENABLED";
- attribute GSR of FF_106 : label is "ENABLED";
- attribute GSR of FF_105 : label is "ENABLED";
- attribute GSR of FF_104 : label is "ENABLED";
- attribute GSR of FF_103 : label is "ENABLED";
- attribute GSR of FF_102 : label is "ENABLED";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
-
- FF_303 : FD1P3DX
- port map (D => tsum(303), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(303));
- FF_302 : FD1P3DX
- port map (D => tsum(302), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(302));
- FF_301 : FD1P3DX
- port map (D => tsum(301), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(301));
- FF_300 : FD1P3DX
- port map (D => tsum(300), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(300));
- FF_299 : FD1P3DX
- port map (D => tsum(299), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(299));
- FF_298 : FD1P3DX
- port map (D => tsum(298), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(298));
- FF_297 : FD1P3DX
- port map (D => tsum(297), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(297));
- FF_296 : FD1P3DX
- port map (D => tsum(296), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(296));
- FF_295 : FD1P3DX
- port map (D => tsum(295), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(295));
- FF_294 : FD1P3DX
- port map (D => tsum(294), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(294));
- FF_293 : FD1P3DX
- port map (D => tsum(293), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(293));
- FF_292 : FD1P3DX
- port map (D => tsum(292), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(292));
- FF_291 : FD1P3DX
- port map (D => tsum(291), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(291));
- FF_290 : FD1P3DX
- port map (D => tsum(290), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(290));
- FF_289 : FD1P3DX
- port map (D => tsum(289), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(289));
- FF_288 : FD1P3DX
- port map (D => tsum(288), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(288));
- FF_287 : FD1P3DX
- port map (D => tsum(287), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(287));
- FF_286 : FD1P3DX
- port map (D => tsum(286), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(286));
- FF_285 : FD1P3DX
- port map (D => tsum(285), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(285));
- FF_284 : FD1P3DX
- port map (D => tsum(284), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(284));
- FF_283 : FD1P3DX
- port map (D => tsum(283), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(283));
- FF_282 : FD1P3DX
- port map (D => tsum(282), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(282));
- FF_281 : FD1P3DX
- port map (D => tsum(281), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(281));
- FF_280 : FD1P3DX
- port map (D => tsum(280), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(280));
- FF_279 : FD1P3DX
- port map (D => tsum(279), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(279));
- FF_278 : FD1P3DX
- port map (D => tsum(278), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(278));
- FF_277 : FD1P3DX
- port map (D => tsum(277), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(277));
- FF_276 : FD1P3DX
- port map (D => tsum(276), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(276));
- FF_275 : FD1P3DX
- port map (D => tsum(275), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(275));
- FF_274 : FD1P3DX
- port map (D => tsum(274), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(274));
- FF_273 : FD1P3DX
- port map (D => tsum(273), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(273));
- FF_272 : FD1P3DX
- port map (D => tsum(272), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(272));
- FF_271 : FD1P3DX
- port map (D => tsum(271), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(271));
- FF_270 : FD1P3DX
- port map (D => tsum(270), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(270));
- FF_269 : FD1P3DX
- port map (D => tsum(269), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(269));
- FF_268 : FD1P3DX
- port map (D => tsum(268), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(268));
- FF_267 : FD1P3DX
- port map (D => tsum(267), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(267));
- FF_266 : FD1P3DX
- port map (D => tsum(266), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(266));
- FF_265 : FD1P3DX
- port map (D => tsum(265), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(265));
- FF_264 : FD1P3DX
- port map (D => tsum(264), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(264));
- FF_263 : FD1P3DX
- port map (D => tsum(263), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(263));
- FF_262 : FD1P3DX
- port map (D => tsum(262), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(262));
- FF_261 : FD1P3DX
- port map (D => tsum(261), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(261));
- FF_260 : FD1P3DX
- port map (D => tsum(260), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(260));
- FF_259 : FD1P3DX
- port map (D => tsum(259), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(259));
- FF_258 : FD1P3DX
- port map (D => tsum(258), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(258));
- FF_257 : FD1P3DX
- port map (D => tsum(257), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(257));
- FF_256 : FD1P3DX
- port map (D => tsum(256), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(256));
- FF_255 : FD1P3DX
- port map (D => tsum(255), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(255));
- FF_254 : FD1P3DX
- port map (D => tsum(254), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(254));
- FF_253 : FD1P3DX
- port map (D => tsum(253), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(253));
- FF_252 : FD1P3DX
- port map (D => tsum(252), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(252));
- FF_251 : FD1P3DX
- port map (D => tsum(251), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(251));
- FF_250 : FD1P3DX
- port map (D => tsum(250), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(250));
- FF_249 : FD1P3DX
- port map (D => tsum(249), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(249));
- FF_248 : FD1P3DX
- port map (D => tsum(248), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(248));
- FF_247 : FD1P3DX
- port map (D => tsum(247), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(247));
- FF_246 : FD1P3DX
- port map (D => tsum(246), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(246));
- FF_245 : FD1P3DX
- port map (D => tsum(245), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(245));
- FF_244 : FD1P3DX
- port map (D => tsum(244), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(244));
- FF_243 : FD1P3DX
- port map (D => tsum(243), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(243));
- FF_242 : FD1P3DX
- port map (D => tsum(242), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(242));
- FF_241 : FD1P3DX
- port map (D => tsum(241), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(241));
- FF_240 : FD1P3DX
- port map (D => tsum(240), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(240));
- FF_239 : FD1P3DX
- port map (D => tsum(239), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(239));
- FF_238 : FD1P3DX
- port map (D => tsum(238), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(238));
- FF_237 : FD1P3DX
- port map (D => tsum(237), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(237));
- FF_236 : FD1P3DX
- port map (D => tsum(236), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(236));
- FF_235 : FD1P3DX
- port map (D => tsum(235), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(235));
- FF_234 : FD1P3DX
- port map (D => tsum(234), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(234));
- FF_233 : FD1P3DX
- port map (D => tsum(233), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(233));
- FF_232 : FD1P3DX
- port map (D => tsum(232), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(232));
- FF_231 : FD1P3DX
- port map (D => tsum(231), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(231));
- FF_230 : FD1P3DX
- port map (D => tsum(230), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(230));
- FF_229 : FD1P3DX
- port map (D => tsum(229), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(229));
- FF_228 : FD1P3DX
- port map (D => tsum(228), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(228));
- FF_227 : FD1P3DX
- port map (D => tsum(227), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(227));
- FF_226 : FD1P3DX
- port map (D => tsum(226), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(226));
- FF_225 : FD1P3DX
- port map (D => tsum(225), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(225));
- FF_224 : FD1P3DX
- port map (D => tsum(224), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(224));
- FF_223 : FD1P3DX
- port map (D => tsum(223), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(223));
- FF_222 : FD1P3DX
- port map (D => tsum(222), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(222));
- FF_221 : FD1P3DX
- port map (D => tsum(221), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(221));
- FF_220 : FD1P3DX
- port map (D => tsum(220), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(220));
- FF_219 : FD1P3DX
- port map (D => tsum(219), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(219));
- FF_218 : FD1P3DX
- port map (D => tsum(218), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(218));
- FF_217 : FD1P3DX
- port map (D => tsum(217), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(217));
- FF_216 : FD1P3DX
- port map (D => tsum(216), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(216));
- FF_215 : FD1P3DX
- port map (D => tsum(215), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(215));
- FF_214 : FD1P3DX
- port map (D => tsum(214), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(214));
- FF_213 : FD1P3DX
- port map (D => tsum(213), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(213));
- FF_212 : FD1P3DX
- port map (D => tsum(212), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(212));
- FF_211 : FD1P3DX
- port map (D => tsum(211), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(211));
- FF_210 : FD1P3DX
- port map (D => tsum(210), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(210));
- FF_209 : FD1P3DX
- port map (D => tsum(209), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(209));
- FF_208 : FD1P3DX
- port map (D => tsum(208), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(208));
- FF_207 : FD1P3DX
- port map (D => tsum(207), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(207));
- FF_206 : FD1P3DX
- port map (D => tsum(206), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(206));
- FF_205 : FD1P3DX
- port map (D => tsum(205), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(205));
- FF_204 : FD1P3DX
- port map (D => tsum(204), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(204));
- FF_203 : FD1P3DX
- port map (D => tsum(203), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(203));
- FF_202 : FD1P3DX
- port map (D => tsum(202), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(202));
- FF_201 : FD1P3DX
- port map (D => tsum(201), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(201));
- FF_200 : FD1P3DX
- port map (D => tsum(200), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(200));
- FF_199 : FD1P3DX
- port map (D => tsum(199), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(199));
- FF_198 : FD1P3DX
- port map (D => tsum(198), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(198));
- FF_197 : FD1P3DX
- port map (D => tsum(197), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(197));
- FF_196 : FD1P3DX
- port map (D => tsum(196), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(196));
- FF_195 : FD1P3DX
- port map (D => tsum(195), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(195));
- FF_194 : FD1P3DX
- port map (D => tsum(194), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(194));
- FF_193 : FD1P3DX
- port map (D => tsum(193), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(193));
- FF_192 : FD1P3DX
- port map (D => tsum(192), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(192));
- FF_191 : FD1P3DX
- port map (D => tsum(191), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(191));
- FF_190 : FD1P3DX
- port map (D => tsum(190), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(190));
- FF_189 : FD1P3DX
- port map (D => tsum(189), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(189));
- FF_188 : FD1P3DX
- port map (D => tsum(188), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(188));
- FF_187 : FD1P3DX
- port map (D => tsum(187), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(187));
- FF_186 : FD1P3DX
- port map (D => tsum(186), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(186));
- FF_185 : FD1P3DX
- port map (D => tsum(185), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(185));
- FF_184 : FD1P3DX
- port map (D => tsum(184), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(184));
- FF_183 : FD1P3DX
- port map (D => tsum(183), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(183));
- FF_182 : FD1P3DX
- port map (D => tsum(182), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(182));
- FF_181 : FD1P3DX
- port map (D => tsum(181), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(181));
- FF_180 : FD1P3DX
- port map (D => tsum(180), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(180));
- FF_179 : FD1P3DX
- port map (D => tsum(179), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(179));
- FF_178 : FD1P3DX
- port map (D => tsum(178), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(178));
- FF_177 : FD1P3DX
- port map (D => tsum(177), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(177));
- FF_176 : FD1P3DX
- port map (D => tsum(176), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(176));
- FF_175 : FD1P3DX
- port map (D => tsum(175), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(175));
- FF_174 : FD1P3DX
- port map (D => tsum(174), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(174));
- FF_173 : FD1P3DX
- port map (D => tsum(173), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(173));
- FF_172 : FD1P3DX
- port map (D => tsum(172), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(172));
- FF_171 : FD1P3DX
- port map (D => tsum(171), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(171));
- FF_170 : FD1P3DX
- port map (D => tsum(170), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(170));
- FF_169 : FD1P3DX
- port map (D => tsum(169), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(169));
- FF_168 : FD1P3DX
- port map (D => tsum(168), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(168));
- FF_167 : FD1P3DX
- port map (D => tsum(167), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(167));
- FF_166 : FD1P3DX
- port map (D => tsum(166), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(166));
- FF_165 : FD1P3DX
- port map (D => tsum(165), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(165));
- FF_164 : FD1P3DX
- port map (D => tsum(164), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(164));
- FF_163 : FD1P3DX
- port map (D => tsum(163), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(163));
- FF_162 : FD1P3DX
- port map (D => tsum(162), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(162));
- FF_161 : FD1P3DX
- port map (D => tsum(161), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(161));
- FF_160 : FD1P3DX
- port map (D => tsum(160), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(160));
- FF_159 : FD1P3DX
- port map (D => tsum(159), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(159));
- FF_158 : FD1P3DX
- port map (D => tsum(158), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(158));
- FF_157 : FD1P3DX
- port map (D => tsum(157), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(157));
- FF_156 : FD1P3DX
- port map (D => tsum(156), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(156));
- FF_155 : FD1P3DX
- port map (D => tsum(155), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(155));
- FF_154 : FD1P3DX
- port map (D => tsum(154), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(154));
- FF_153 : FD1P3DX
- port map (D => tsum(153), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(153));
- FF_152 : FD1P3DX
- port map (D => tsum(152), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(152));
- FF_151 : FD1P3DX
- port map (D => tsum(151), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(151));
- FF_150 : FD1P3DX
- port map (D => tsum(150), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(150));
- FF_149 : FD1P3DX
- port map (D => tsum(149), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(149));
- FF_148 : FD1P3DX
- port map (D => tsum(148), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(148));
- FF_147 : FD1P3DX
- port map (D => tsum(147), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(147));
- FF_146 : FD1P3DX
- port map (D => tsum(146), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(146));
- FF_145 : FD1P3DX
- port map (D => tsum(145), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(145));
- FF_144 : FD1P3DX
- port map (D => tsum(144), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(144));
- FF_143 : FD1P3DX
- port map (D => tsum(143), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(143));
- FF_142 : FD1P3DX
- port map (D => tsum(142), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(142));
- FF_141 : FD1P3DX
- port map (D => tsum(141), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(141));
- FF_140 : FD1P3DX
- port map (D => tsum(140), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(140));
- FF_139 : FD1P3DX
- port map (D => tsum(139), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(139));
- FF_138 : FD1P3DX
- port map (D => tsum(138), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(138));
- FF_137 : FD1P3DX
- port map (D => tsum(137), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(137));
- FF_136 : FD1P3DX
- port map (D => tsum(136), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(136));
- FF_135 : FD1P3DX
- port map (D => tsum(135), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(135));
- FF_134 : FD1P3DX
- port map (D => tsum(134), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(134));
- FF_133 : FD1P3DX
- port map (D => tsum(133), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(133));
- FF_132 : FD1P3DX
- port map (D => tsum(132), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(132));
- FF_131 : FD1P3DX
- port map (D => tsum(131), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(131));
- FF_130 : FD1P3DX
- port map (D => tsum(130), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(130));
- FF_129 : FD1P3DX
- port map (D => tsum(129), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(129));
- FF_128 : FD1P3DX
- port map (D => tsum(128), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(128));
- FF_127 : FD1P3DX
- port map (D => tsum(127), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(127));
- FF_126 : FD1P3DX
- port map (D => tsum(126), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(126));
- FF_125 : FD1P3DX
- port map (D => tsum(125), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(125));
- FF_124 : FD1P3DX
- port map (D => tsum(124), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(124));
- FF_123 : FD1P3DX
- port map (D => tsum(123), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(123));
- FF_122 : FD1P3DX
- port map (D => tsum(122), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(122));
- FF_121 : FD1P3DX
- port map (D => tsum(121), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(121));
- FF_120 : FD1P3DX
- port map (D => tsum(120), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(120));
- FF_119 : FD1P3DX
- port map (D => tsum(119), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(119));
- FF_118 : FD1P3DX
- port map (D => tsum(118), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(118));
- FF_117 : FD1P3DX
- port map (D => tsum(117), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(117));
- FF_116 : FD1P3DX
- port map (D => tsum(116), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(116));
- FF_115 : FD1P3DX
- port map (D => tsum(115), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(115));
- FF_114 : FD1P3DX
- port map (D => tsum(114), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(114));
- FF_113 : FD1P3DX
- port map (D => tsum(113), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(113));
- FF_112 : FD1P3DX
- port map (D => tsum(112), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(112));
- FF_111 : FD1P3DX
- port map (D => tsum(111), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(111));
- FF_110 : FD1P3DX
- port map (D => tsum(110), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(110));
- FF_109 : FD1P3DX
- port map (D => tsum(109), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(109));
- FF_108 : FD1P3DX
- port map (D => tsum(108), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(108));
- FF_107 : FD1P3DX
- port map (D => tsum(107), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(107));
- FF_106 : FD1P3DX
- port map (D => tsum(106), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(106));
- FF_105 : FD1P3DX
- port map (D => tsum(105), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(105));
- FF_104 : FD1P3DX
- port map (D => tsum(104), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(104));
- FF_103 : FD1P3DX
- port map (D => tsum(103), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(103));
- FF_102 : FD1P3DX
- port map (D => tsum(102), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(102));
- FF_101 : FD1P3DX
- port map (D => tsum(101), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(101));
- FF_100 : FD1P3DX
- port map (D => tsum(100), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(100));
- FF_99 : FD1P3DX
- port map (D => tsum(99), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(99));
- FF_98 : FD1P3DX
- port map (D => tsum(98), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(98));
- FF_97 : FD1P3DX
- port map (D => tsum(97), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(97));
- FF_96 : FD1P3DX
- port map (D => tsum(96), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(96));
- FF_95 : FD1P3DX
- port map (D => tsum(95), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(95));
- FF_94 : FD1P3DX
- port map (D => tsum(94), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(94));
- FF_93 : FD1P3DX
- port map (D => tsum(93), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(93));
- FF_92 : FD1P3DX
- port map (D => tsum(92), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(92));
- FF_91 : FD1P3DX
- port map (D => tsum(91), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(91));
- FF_90 : FD1P3DX
- port map (D => tsum(90), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(90));
- FF_89 : FD1P3DX
- port map (D => tsum(89), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(89));
- FF_88 : FD1P3DX
- port map (D => tsum(88), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(88));
- FF_87 : FD1P3DX
- port map (D => tsum(87), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(87));
- FF_86 : FD1P3DX
- port map (D => tsum(86), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(86));
- FF_85 : FD1P3DX
- port map (D => tsum(85), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(85));
- FF_84 : FD1P3DX
- port map (D => tsum(84), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(84));
- FF_83 : FD1P3DX
- port map (D => tsum(83), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(83));
- FF_82 : FD1P3DX
- port map (D => tsum(82), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(82));
- FF_81 : FD1P3DX
- port map (D => tsum(81), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(81));
- FF_80 : FD1P3DX
- port map (D => tsum(80), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(80));
- FF_79 : FD1P3DX
- port map (D => tsum(79), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(79));
- FF_78 : FD1P3DX
- port map (D => tsum(78), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(78));
- FF_77 : FD1P3DX
- port map (D => tsum(77), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(77));
- FF_76 : FD1P3DX
- port map (D => tsum(76), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(76));
- FF_75 : FD1P3DX
- port map (D => tsum(75), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(75));
- FF_74 : FD1P3DX
- port map (D => tsum(74), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(74));
- FF_73 : FD1P3DX
- port map (D => tsum(73), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(73));
- FF_72 : FD1P3DX
- port map (D => tsum(72), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(72));
- FF_71 : FD1P3DX
- port map (D => tsum(71), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(71));
- FF_70 : FD1P3DX
- port map (D => tsum(70), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(70));
- FF_69 : FD1P3DX
- port map (D => tsum(69), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(69));
- FF_68 : FD1P3DX
- port map (D => tsum(68), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(68));
- FF_67 : FD1P3DX
- port map (D => tsum(67), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(67));
- FF_66 : FD1P3DX
- port map (D => tsum(66), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(66));
- FF_65 : FD1P3DX
- port map (D => tsum(65), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(65));
- FF_64 : FD1P3DX
- port map (D => tsum(64), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(64));
- FF_63 : FD1P3DX
- port map (D => tsum(63), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(63));
- FF_62 : FD1P3DX
- port map (D => tsum(62), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(62));
- FF_61 : FD1P3DX
- port map (D => tsum(61), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(61));
- FF_60 : FD1P3DX
- port map (D => tsum(60), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(60));
- FF_59 : FD1P3DX
- port map (D => tsum(59), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(59));
- FF_58 : FD1P3DX
- port map (D => tsum(58), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(58));
- FF_57 : FD1P3DX
- port map (D => tsum(57), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(57));
- FF_56 : FD1P3DX
- port map (D => tsum(56), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(56));
- FF_55 : FD1P3DX
- port map (D => tsum(55), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(55));
- FF_54 : FD1P3DX
- port map (D => tsum(54), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(54));
- FF_53 : FD1P3DX
- port map (D => tsum(53), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(53));
- FF_52 : FD1P3DX
- port map (D => tsum(52), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(52));
- FF_51 : FD1P3DX
- port map (D => tsum(51), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(51));
- FF_50 : FD1P3DX
- port map (D => tsum(50), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(50));
- FF_49 : FD1P3DX
- port map (D => tsum(49), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(49));
- FF_48 : FD1P3DX
- port map (D => tsum(48), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(48));
- FF_47 : FD1P3DX
- port map (D => tsum(47), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(47));
- FF_46 : FD1P3DX
- port map (D => tsum(46), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(46));
- FF_45 : FD1P3DX
- port map (D => tsum(45), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(45));
- FF_44 : FD1P3DX
- port map (D => tsum(44), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(44));
- FF_43 : FD1P3DX
- port map (D => tsum(43), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(43));
- FF_42 : FD1P3DX
- port map (D => tsum(42), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(42));
- FF_41 : FD1P3DX
- port map (D => tsum(41), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(41));
- FF_40 : FD1P3DX
- port map (D => tsum(40), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(40));
- FF_39 : FD1P3DX
- port map (D => tsum(39), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(39));
- FF_38 : FD1P3DX
- port map (D => tsum(38), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(38));
- FF_37 : FD1P3DX
- port map (D => tsum(37), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(37));
- FF_36 : FD1P3DX
- port map (D => tsum(36), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(36));
- FF_35 : FD1P3DX
- port map (D => tsum(35), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(35));
- FF_34 : FD1P3DX
- port map (D => tsum(34), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(34));
- FF_33 : FD1P3DX
- port map (D => tsum(33), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(33));
- FF_32 : FD1P3DX
- port map (D => tsum(32), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(32));
- FF_31 : FD1P3DX
- port map (D => tsum(31), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(31));
- FF_30 : FD1P3DX
- port map (D => tsum(30), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(30));
- FF_29 : FD1P3DX
- port map (D => tsum(29), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(29));
- FF_28 : FD1P3DX
- port map (D => tsum(28), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(28));
- FF_27 : FD1P3DX
- port map (D => tsum(27), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(27));
- FF_26 : FD1P3DX
- port map (D => tsum(26), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(26));
- FF_25 : FD1P3DX
- port map (D => tsum(25), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(25));
- FF_24 : FD1P3DX
- port map (D => tsum(24), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(24));
- FF_23 : FD1P3DX
- port map (D => tsum(23), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(23));
- FF_22 : FD1P3DX
- port map (D => tsum(22), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(22));
- FF_21 : FD1P3DX
- port map (D => tsum(21), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(21));
- FF_20 : FD1P3DX
- port map (D => tsum(20), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(20));
- FF_19 : FD1P3DX
- port map (D => tsum(19), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(19));
- FF_18 : FD1P3DX
- port map (D => tsum(18), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(18));
- FF_17 : FD1P3DX
- port map (D => tsum(17), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(17));
- FF_16 : FD1P3DX
- port map (D => tsum(16), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(16));
- FF_15 : FD1P3DX
- port map (D => tsum(15), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(15));
- FF_14 : FD1P3DX
- port map (D => tsum(14), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(14));
- FF_13 : FD1P3DX
- port map (D => tsum(13), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(13));
- FF_12 : FD1P3DX
- port map (D => tsum(12), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(12));
- FF_11 : FD1P3DX
- port map (D => tsum(11), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(11));
- FF_10 : FD1P3DX
- port map (D => tsum(10), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(10));
- FF_9 : FD1P3DX
- port map (D => tsum(9), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(9));
- FF_8 : FD1P3DX
- port map (D => tsum(8), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(8));
- FF_7 : FD1P3DX
- port map (D => tsum(7), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(7));
- FF_6 : FD1P3DX
- port map (D => tsum(6), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(6));
- FF_5 : FD1P3DX
- port map (D => tsum(5), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(5));
- FF_4 : FD1P3DX
- port map (D => tsum(4), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(4));
- FF_3 : FD1P3DX
- port map (D => tsum(3), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(3));
- FF_2 : FD1P3DX
- port map (D => tsum(2), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(2));
- FF_1 : FD1P3DX
- port map (D => tsum(1), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(1));
- FF_0 : FD1P3DX
- port map (D => tsum(0), SP => CLKEn, CK => CLK, CD => Reset,
- Q => r0_sum(0));
-
- GEN_0_ADD : FADD2B
- port map (A0 => DataA(0),
- A1 => DataA(1),
- B0 => DataB(0),
- B1 => DataB(1),
- CI => scuba_vlo,
- COUT => co(0),
- S0 => tsum(0),
- S1 => tsum(1));
-
- GEN : for i in 1 to 151 generate
- ADD : FADD2B
- port map (A0 => DataA(2*i),
- A1 => DataA(2*i+1),
- B0 => DataB(2*i),
- B1 => DataB(2*i+1),
- CI => co(i-1),
- COUT => co(i),
- S0 => tsum(2*i),
- S1 => tsum(2*i+1));
- end generate GEN;
-
- scuba_vlo_inst : VLO
- port map (Z => scuba_vlo);
-
- Result <= r0_sum;
-
-end Structure;
-
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of adder_304 is
- for Structure
- for all : FADD2B use entity ecp3.FADD2B(V); end for;
- for all : FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all : VLO use entity ecp3.VLO(V); end for;
- end for;
-end Structure_CON;
--- synopsys translate_on
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_arith.all;
-
-entity Channel is
-
- generic (
- CHANNEL_ID : integer range 0 to 64);
- port (
- RESET_WR : in std_logic;
- RESET_RD : in std_logic;
- CLK_WR : in std_logic;
- CLK_RD : in std_logic;
---
- HIT_IN : in std_logic;
- READ_EN_IN : in std_logic;
- FIFO_DATA_OUT : out std_logic_vector(31 downto 0);
- FIFO_EMPTY_OUT : out std_logic;
- FIFO_FULL_OUT : out std_logic;
- COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
---
- LOST_HIT_NUMBER : out std_logic_vector(23 downto 0);
- MEASUREMENT_NUMBER : out std_logic_vector(23 downto 0);
- ENCODER_START_NUMBER : out std_logic_vector(23 downto 0);
---
- Channel_DEBUG_01 : out std_logic_vector(31 downto 0)
--- Channel_DEBUG_02 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_03 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_04 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_05 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_06 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_07 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_08 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_09 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_10 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_11 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_12 : out std_logic_vector(31 downto 0)
- );
-
-end Channel;
-
-architecture Channel of Channel is
-
--------------------------------------------------------------------------------
--- Component Declarations
--------------------------------------------------------------------------------
-
- component Adder_304
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- DataA : in std_logic_vector(303 downto 0);
- DataB : in std_logic_vector(303 downto 0);
- ClkEn : in std_logic;
- Result : out std_logic_vector(303 downto 0));
- end component;
---
- component Encoder_304_Bit
- port (
- RESET : in std_logic;
- CLK : in std_logic;
- START_IN : in std_logic;
- THERMOCODE_IN : in std_logic_vector(303 downto 0);
- FINISHED_OUT : out std_logic;
- BINARY_CODE_OUT : out std_logic_vector(9 downto 0);
- BUSY_OUT : out std_logic;
- ENCODER_DEBUG : out std_logic_vector(31 downto 0));
- end component;
---
- --component Encoder_304_ROMsuz
- -- port (
- -- RESET : in std_logic;
- -- CLK : in std_logic;
- -- START_IN : in std_logic;
- -- THERMOCODE_IN : in std_logic_vector(303 downto 0);
- -- FINISHED_OUT : out std_logic;
- -- BINARY_CODE_OUT : out std_logic_vector(9 downto 0);
- -- ENCODER_DEBUG : out std_logic_vector(31 downto 0));
- --end component;
---
- --component Encoder_304_Sngl_ROMsuz
- -- port (
- -- RESET : in std_logic;
- -- CLK : in std_logic;
- -- START_IN : in std_logic;
- -- THERMOCODE_IN : in std_logic_vector(303 downto 0);
- -- FINISHED_OUT : out std_logic;
- -- BINARY_CODE_OUT : out std_logic_vector(9 downto 0);
- -- ENCODER_DEBUG : out std_logic_vector(31 downto 0));
- --end component;
---
- component FIFO_32x512_OutReg
- port (
- Data : in std_logic_vector(31 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(31 downto 0);
- Empty : out std_logic;
- Full : out std_logic);
- end component;
---
- component edge_to_pulse
- port (
- clock : in std_logic;
- en_clk : in std_logic;
- signal_in : in std_logic;
- pulse : out std_logic);
- end component;
---
- component signal_sync
- generic (
- WIDTH : integer;
- DEPTH : integer);
- port (
- RESET : in std_logic;
- CLK0 : in std_logic;
- CLK1 : in std_logic;
- D_IN : in std_logic_vector(WIDTH-1 downto 0);
- D_OUT : out std_logic_vector(WIDTH-1 downto 0));
- end component;
--------------------------------------------------------------------------------
--- Signal Declarations
--------------------------------------------------------------------------------
-
- signal data_a_i : std_logic_vector(303 downto 0);
- signal data_b_i : std_logic_vector(303 downto 0);
- signal result_i : std_logic_vector(303 downto 0);
- signal result_reg : std_logic_vector(303 downto 0);
- signal hit_in_i : std_logic;
- signal hit_detect_i : std_logic;
- signal result_2_reg : std_logic;
- signal coarse_cntr_i : std_logic_vector(10 downto 0);
- signal hit_time_stamp_i : std_logic_vector(10 downto 0);
- signal hit_time_stamp_reg : std_logic_vector(10 downto 0);
- signal hit_time_stamp_reg2 : std_logic_vector(10 downto 0);
- signal hit_time_stamp_reg3 : std_logic_vector(10 downto 0);
- signal fine_counter_i : std_logic_vector(9 downto 0);
- signal encoder_start_i : std_logic;
- signal encoder_busy_i : std_logic;
- signal fifo_data_out_i : std_logic_vector(31 downto 0);
- signal fifo_data_in_i : std_logic_vector(31 downto 0);
- signal fifo_empty_i : std_logic;
- signal fifo_full_i : std_logic;
- signal fifo_wr_en_i : std_logic;
- signal fifo_rd_en_i : std_logic;
- signal sync_q : std_logic_vector(3 downto 0);
- signal hit_pulse : std_logic;
- signal lost_hit_cntr : std_logic_vector(23 downto 0);
- signal lost_hit_number_reg : std_logic_vector(23 downto 0);
- signal hit_buf : std_logic;
- signal ff_array_en_i : std_logic := '1';
-
--------------------------------------------------------------------------------
--- Debug Signals
--------------------------------------------------------------------------------
- signal measurement_cntr : std_logic_vector(23 downto 0);
- signal measurement_reg : std_logic_vector(23 downto 0);
- signal encoder_start_cntr : std_logic_vector(23 downto 0);
- signal encoder_start_cntr_reg : std_logic_vector(23 downto 0);
- signal encoder_debug_i : std_logic_vector(31 downto 0);
--------------------------------------------------------------------------------
-
- attribute syn_keep : boolean;
- attribute syn_keep of hit_buf : signal is true;
- attribute syn_keep of hit_in_i : signal is true;
- attribute syn_keep of ff_array_en_i : signal is true;
- attribute NOMERGE : string;
- attribute NOMERGE of hit_buf : signal is "true";
- attribute NOMERGE of ff_array_en_i : signal is "true";
-
--------------------------------------------------------------------------------
-
-begin
-
- fifo_rd_en_i <= READ_EN_IN;
- coarse_cntr_i <= COARSE_COUNTER_IN;
- hit_in_i <= HIT_IN;
- hit_buf <= not hit_in_i;
-
- --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition
- FC : Adder_304
- port map (
- CLK => CLK_WR,
- RESET => RESET_WR,
- DataA => data_a_i,
- DataB => data_b_i,
- ClkEn => '1', -- ff_array_en_i, -- '1',
- Result => result_i);
- data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF";
- data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(hit_buf) & x"000000" & "00" & hit_buf;
-
- --FF_Array_Enable : process (hit_detect_i, encoder_busy_i)
- --begin
- -- if hit_detect_i = '1' then
- -- ff_array_en_i <= '0';
- -- elsif encoder_busy_i = '1' then
- -- ff_array_en_i <= '1';
- -- end if;
- --end process FF_Array_Enable;
-
- --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) single transition
- --FC : Adder_304
- -- port map (
- -- CLK => CLK_WR,
- -- RESET => RESET_WR,
- -- DataA => data_a_i,
- -- DataB => data_b_i,
- -- ClkEn => '1',
- -- Result => result_i);
- --data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
- --data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000000000" & "000" & hit_in_i;
-
- --purpose: Tapped Delay Line 288 (Carry Chain) single transition
--- FC : Adder_288
--- port map (
--- CLK => CLK_WR,
--- RESET => RESET_WR,
--- DataA => data_a_i,
--- DataB => data_b_i,
--- ClkEn => '1',
--- Result => result_i);
--- data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
--- data_b_i <= x"00000000000000000000000000000000000000000000000000000000000000000000000" & "000" & hit_in_i;
-
- --purpose: Registers the hit detection bit
- Hit_Register : process (CLK_WR, RESET_WR)
- begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
- result_2_reg <= '0';
- else
- result_2_reg <= result_i(2);
- end if;
- end if;
- end process Hit_Register;
-
- --purpose: Detects the hit
- Hit_Detect : process (result_2_reg, result_i)
- begin
- hit_detect_i <= (not result_2_reg) and result_i(2); -- result_2_reg and (not result_i(2));
- end process Hit_Detect;
-
- --purpose: Double Synchroniser
- Double_Syncroniser : process (CLK_WR)
- begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
- result_reg <= (others => '1');
- elsif hit_detect_i = '1' then
- result_reg <= result_i;
- end if;
- end if;
- end process Double_Syncroniser;
-
- --purpose: Start Encoder and captures the time stamp of the hit
- Start_Encoder : process (CLK_WR)
- begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
- encoder_start_i <= '0';
- hit_time_stamp_i <= (others => '0');
- hit_time_stamp_reg <= (others => '0');
- hit_time_stamp_reg2 <= (others => '0');
- hit_time_stamp_reg3 <= (others => '0');
- elsif hit_detect_i = '1' then
- encoder_start_i <= '1';
- hit_time_stamp_i <= coarse_cntr_i-1;
- else
- encoder_start_i <= '0';
- hit_time_stamp_reg <= hit_time_stamp_i;
- hit_time_stamp_reg2 <= hit_time_stamp_reg;
- hit_time_stamp_reg3 <= hit_time_stamp_reg2;
- end if;
- end if;
- end process Start_Encoder;
-
- --purpose: Encoder
- Encoder : Encoder_304_Bit
- port map (
- RESET => RESET_WR,
- CLK => CLK_WR,
- START_IN => encoder_start_i,
- THERMOCODE_IN => result_reg,
- FINISHED_OUT => fifo_wr_en_i,
- BINARY_CODE_OUT => fine_counter_i,
- BUSY_OUT => encoder_busy_i,
- ENCODER_DEBUG => encoder_debug_i);
-
- ----purpose: Encoder
- --Encoder : Encoder_304_ROMsuz
- -- port map (
- -- RESET => RESET_WR,
- -- CLK => CLK_WR,
- -- START_IN => encoder_start_i,
- -- THERMOCODE_IN => result_reg,
- -- FINISHED_OUT => fifo_wr_en_i,
- -- BINARY_CODE_OUT => fine_counter_i,
- -- ENCODER_DEBUG => encoder_debug_i);
-
- --purpose: Encoder
- --Encoder : Encoder_304_Sngl_ROMsuz
- -- port map (
- -- RESET => RESET_WR,
- -- CLK => CLK_WR,
- -- START_IN => encoder_start_i,
- -- THERMOCODE_IN => result_reg,
- -- FINISHED_OUT => fifo_wr_en_i,
- -- BINARY_CODE_OUT => fine_counter_i,
- -- ENCODER_DEBUG => encoder_debug_i);
-
- FIFO : FIFO_32x512_OutReg
- port map (
- Data => fifo_data_in_i,
- WrClock => CLK_WR,
- RdClock => CLK_RD,
- WrEn => fifo_wr_en_i,
- RdEn => fifo_rd_en_i,
- Reset => RESET_RD,
- RPReset => RESET_RD,
- Q => fifo_data_out_i,
- Empty => fifo_empty_i,
- Full => fifo_full_i);
- fifo_data_in_i(31) <= '1'; -- data marker
- fifo_data_in_i(30 downto 28) <= "000"; -- reserved bits
- fifo_data_in_i(27 downto 22) <= conv_std_logic_vector(CHANNEL_ID, 6); -- channel number
- fifo_data_in_i(21 downto 12) <= fine_counter_i; -- fine time from the encoder
- fifo_data_in_i(11) <= '1'; -- rising '1' or falling '0' edge
- fifo_data_in_i(10 downto 0) <= hit_time_stamp_reg3; -- hit time stamp
-
- Register_Outputs : process (CLK_RD, RESET_RD)
- begin
- if rising_edge(CLK_RD) then
- if RESET_RD = '1' then
- FIFO_DATA_OUT <= (others => '1');
- FIFO_EMPTY_OUT <= '0';
- FIFO_FULL_OUT <= '0';
- else
- FIFO_DATA_OUT <= fifo_data_out_i;
- FIFO_EMPTY_OUT <= fifo_empty_i;
- FIFO_FULL_OUT <= fifo_full_i;
- end if;
- end if;
- end process Register_Outputs;
-
--------------------------------------------------------------------------------
--- Lost Hit Detection
--------------------------------------------------------------------------------
- --purpose: Hit Signal Synchroniser
- GEN_flipflops : for i in 1 to 3 generate
- Hit_Sync : process (CLK_WR)
- begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
- sync_q(i) <= '0';
- else
- sync_q(i) <= sync_q(i-1);
- end if;
- end if;
- end process Hit_Sync;
- end generate GEN_flipflops;
- sync_q(0) <= HIT_IN;
-
- --purpose: Creates a pulse out of the synchronised hit signal
- Edge_To_Pulse_Hit : edge_to_pulse
- port map (
- clock => CLK_WR,
- en_clk => '1',
- signal_in => sync_q(3),
- pulse => hit_pulse);
-
- --purpose: Counts the detected but unwritten hits
- Lost_Hit_Counter : process (CLK_WR)
- begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
- lost_hit_cntr <= (others => '0');
- elsif hit_pulse = '1' then
- lost_hit_cntr <= lost_hit_cntr + 1;
- elsif fifo_wr_en_i = '1' then
- lost_hit_cntr <= lost_hit_cntr - 1;
- end if;
- end if;
- end process Lost_Hit_Counter;
-
- --purpose: Synchronises the lost hit counter to the slowcontrol clock
- Lost_Hit_Sync : signal_sync
- generic map (
- WIDTH => 24,
- DEPTH => 3)
- port map (
- RESET => RESET_RD,
- CLK0 => CLK_WR,
- CLK1 => CLK_RD,
- D_IN => lost_hit_cntr,
- D_OUT => lost_hit_number_reg);
-
- LOST_HIT_NUMBER <= lost_hit_number_reg;
-
-
--------------------------------------------------------------------------------
--- DEBUG
--------------------------------------------------------------------------------
- --purpose: Counts the written hits
- Encoder_Start_Counter : process (CLK_WR)
- begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
- encoder_start_cntr <= (others => '0');
- elsif encoder_start_i = '1' then
- encoder_start_cntr <= encoder_start_cntr + 1;
- end if;
- end if;
- end process Encoder_Start_Counter;
-
- --purpose: Synchronises the measurement counter to the slowcontrol clock
- Encoder_Start_Sync : signal_sync
- generic map (
- WIDTH => 24,
- DEPTH => 3)
- port map (
- RESET => RESET_RD,
- CLK0 => CLK_WR,
- CLK1 => CLK_RD,
- D_IN => encoder_start_cntr,
- D_OUT => encoder_start_cntr_reg);
-
- ENCODER_START_NUMBER <= encoder_start_cntr_reg;
-
- --purpose: Counts the written hits
- Measurement_Counter : process (CLK_WR)
- begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
- measurement_cntr <= (others => '0');
- elsif fifo_wr_en_i = '1' then
- measurement_cntr <= measurement_cntr + 1;
- end if;
- end if;
- end process Measurement_Counter;
-
- --purpose: Synchronises the measurement counter to the slowcontrol clock
- Measurement_Sync : signal_sync
- generic map (
- WIDTH => 24,
- DEPTH => 3)
- port map (
- RESET => RESET_RD,
- CLK0 => CLK_WR,
- CLK1 => CLK_RD,
- D_IN => measurement_cntr,
- D_OUT => measurement_reg);
-
- MEASUREMENT_NUMBER <= measurement_reg;
-
- Channel_DEBUG_01(0) <= hit_pulse;
- Channel_DEBUG_01(1) <= encoder_start_i;
- Channel_DEBUG_01(2) <= fifo_wr_en_i;
- Channel_DEBUG_01(11 downto 3) <= encoder_debug_i(8 downto 0);
--------------------------------------------------------------------------------
-
-end Channel;
+++ /dev/null
--------------------------------------------------------------------------------
--- Title : Encoder 304 bits
--------------------------------------------------------------------------------
--- File : Encoder_304_Bit.vhd
--- Author : Cahit Ugur
--- Created : 2011-11-28
--- Last update: 2012-03-09
--------------------------------------------------------------------------------
--- Description: Encoder for 304 bits
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2011-11-28 1.0 ugur Created
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_unsigned.all;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity Encoder_304_Bit is
- port (
- RESET : in std_logic; -- system reset
- CLK : in std_logic; -- system clock
- START_IN : in std_logic;
- THERMOCODE_IN : in std_logic_vector(303 downto 0);
- FINISHED_OUT : out std_logic;
- BINARY_CODE_OUT : out std_logic_vector(9 downto 0);
- BUSY_OUT : out std_logic;
- ENCODER_DEBUG : out std_logic_vector(31 downto 0)
- );
-end Encoder_304_Bit;
-
-architecture behavioral of Encoder_304_Bit is
-
--------------------------------------------------------------------------------
--- Component Declarations
--------------------------------------------------------------------------------
- component LUT4
- generic (
- INIT : std_logic_vector);
- port (
- A, B, C, D : in std_ulogic;
- Z : out std_ulogic);
- end component;
-
- component ROM_Encoder
- port (
- Address : in std_logic_vector(9 downto 0);
- OutClock : in std_logic;
- OutClockEn : in std_logic;
- Reset : in std_logic;
- Q : out std_logic_vector(7 downto 0));
- end component;
-
--------------------------------------------------------------------------------
--- Signal Declarations
--------------------------------------------------------------------------------
- signal P_lut : std_logic_vector(37 downto 0);
- signal P_one : std_logic_vector(37 downto 0);
- signal mux_control : std_logic_vector(5 downto 0);
- signal mux_control_reg : std_logic_vector(5 downto 0);
- signal mux_control_2reg : std_logic_vector(5 downto 0);
- signal mux_control_3reg : std_logic_vector(5 downto 0);
- signal mux_control_4reg : std_logic_vector(5 downto 0);
- signal interval_reg : std_logic_vector(8 downto 0);
- signal interval_binary : std_logic_vector(2 downto 0);
- signal conversion_nr : std_logic_vector(1 downto 0);
- signal binary_code_f : std_logic_vector(8 downto 0);
- signal binary_code_r : std_logic_vector(8 downto 0);
- signal start_reg : std_logic;
- signal start_2reg : std_logic;
- signal rom_done_i : std_logic; -- indicates that the encoding of rising edge is done
- signal rom_reset_reg : std_logic;
- signal rom_reset_i : std_logic;
- signal address_i : std_logic_vector(9 downto 0);
- signal q_i : std_logic_vector(7 downto 0);
- signal q_reg : std_logic_vector(7 downto 0);
- signal q_2reg : std_logic_vector(7 downto 0);
- signal busy_out_i : std_logic;
-
--------------------------------------------------------------------------------
-begin
-
- --purpose : Register start signal
- Start_Register : process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- start_reg <= '0';
- start_2reg <= '0';
- else
- start_reg <= START_IN;
- start_2reg <= start_reg;
- end if;
- end if;
- end process Start_Register;
-
- Interval_Determination_First : LUT4
- generic map (INIT => X"15A8")
- port map (A => '1', B => '1', C => THERMOCODE_IN(0), D => START_IN,
- Z => P_lut(0));
-
- Interval_Determination : for i in 1 to 37 generate
- U : LUT4
- generic map (INIT => X"15A8")
- port map (A => THERMOCODE_IN(8*i-2), B => THERMOCODE_IN(8*i-1), C => THERMOCODE_IN(8*i), D => START_IN,
- Z => P_lut(i));
- end generate Interval_Determination;
--------------------------------------------------------------------------------
-
- Gen_P_one : for i in 0 to 36 generate
- P_one(i) <= P_lut(i) and (not P_lut(i+1));
- end generate Gen_P_one;
-
- P_one_assign : process (START_IN, P_lut)
- begin
- if START_IN = '1' then
- P_one(37) <= P_lut(37);
- else
- P_one(37) <= '0';
- end if;
- end process P_one_assign;
-
- Interval_Number_to_Binary : process (CLK, RESET)
- begin -- The interval number with the 0-1 transition is converted from 1-of-N code to binary
- -- code for the control of the MUX.
- if rising_edge(CLK) then
- if RESET = '1' then
- mux_control <= (others => '0');
- mux_control_reg <= (others => '0');
- mux_control_2reg <= (others => '0');
- mux_control_3reg <= (others => '0');
- mux_control_4reg <= (others => '0');
- elsif START_IN = '1' or start_reg = '1' then
- mux_control(0) <= P_one(0) or P_one(2) or P_one(4) or P_one(6) or P_one(8) or P_one(10) or
- P_one(12) or P_one(14) or P_one(16) or P_one(18) or P_one(20) or P_one(22) or
- P_one(24) or P_one(26) or P_one(28) or P_one(30) or P_one(32) or P_one(34) or
- P_one(36);
- mux_control(1) <= P_one(1) or P_one(2) or P_one(5) or P_one(6) or P_one(9) or P_one(10) or
- P_one(13) or P_one(14) or P_one(17) or P_one(18) or P_one(21) or P_one(22) or
- P_one(25) or P_one(26) or P_one(29) or P_one(30) or P_one(33) or P_one(34) or
- P_one(37);
- mux_control(2) <= P_one(3) or P_one(4) or P_one(5) or P_one(6) or P_one(11) or P_one(12) or
- P_one(13) or P_one(14) or P_one(19) or P_one(20) or P_one(21) or P_one(22) or
- P_one(27) or P_one(28) or P_one(29) or P_one(30) or P_one(35) or P_one(36) or
- P_one(37);
- mux_control(3) <= P_one(7) or P_one(8) or P_one(9) or P_one(10) or P_one(11) or P_one(12) or
- P_one(13) or P_one(14) or P_one(23) or P_one(24) or P_one(25) or P_one(26) or
- P_one(27) or P_one(28) or P_one(29) or P_one(30);
- mux_control(4) <= P_one(15) or P_one(16) or P_one(17) or P_one(18) or P_one(19) or P_one(20) or
- P_one(21) or P_one(22) or P_one(23) or P_one(24) or P_one(25) or P_one(26) or
- P_one(27) or P_one(28) or P_one(29) or P_one(30);
- mux_control(5) <= P_one(31) or P_one(32) or P_one(33) or P_one(34) or P_one(35) or P_one(36) or
- P_one(37);
- mux_control_reg <= mux_control;
- mux_control_2reg <= mux_control_reg;
- else
- mux_control <= (others => '0');
- mux_control_reg <= mux_control;
- mux_control_2reg <= mux_control_reg;
- mux_control_3reg <= mux_control_2reg;
- mux_control_4reg <= mux_control_3reg;
- end if;
- end if;
- end process Interval_Number_to_Binary;
-
- Interval_Selection : process (CLK, RESET, mux_control, THERMOCODE_IN)
- begin -- The interval with the 0-1 transition is selected.
- if rising_edge(CLK) then
- if RESET = '1' then
- interval_reg <= (others => '0');
- else
- case mux_control is
- when "000001" => interval_reg <= THERMOCODE_IN(7 downto 0) & '1';
- when "000010" => interval_reg <= THERMOCODE_IN(15 downto 7);
- when "000011" => interval_reg <= THERMOCODE_IN(23 downto 15);
- when "000100" => interval_reg <= THERMOCODE_IN(31 downto 23);
- when "000101" => interval_reg <= THERMOCODE_IN(39 downto 31);
- when "000110" => interval_reg <= THERMOCODE_IN(47 downto 39);
- when "000111" => interval_reg <= THERMOCODE_IN(55 downto 47);
- when "001000" => interval_reg <= THERMOCODE_IN(63 downto 55);
- when "001001" => interval_reg <= THERMOCODE_IN(71 downto 63);
- when "001010" => interval_reg <= THERMOCODE_IN(79 downto 71);
- when "001011" => interval_reg <= THERMOCODE_IN(87 downto 79);
- when "001100" => interval_reg <= THERMOCODE_IN(95 downto 87);
- when "001101" => interval_reg <= THERMOCODE_IN(103 downto 95);
- when "001110" => interval_reg <= THERMOCODE_IN(111 downto 103);
- when "001111" => interval_reg <= THERMOCODE_IN(119 downto 111);
- when "010000" => interval_reg <= THERMOCODE_IN(127 downto 119);
- when "010001" => interval_reg <= THERMOCODE_IN(135 downto 127);
- when "010010" => interval_reg <= THERMOCODE_IN(143 downto 135);
- when "010011" => interval_reg <= THERMOCODE_IN(151 downto 143);
- when "010100" => interval_reg <= THERMOCODE_IN(159 downto 151);
- when "010101" => interval_reg <= THERMOCODE_IN(167 downto 159);
- when "010110" => interval_reg <= THERMOCODE_IN(175 downto 167);
- when "010111" => interval_reg <= THERMOCODE_IN(183 downto 175);
- when "011000" => interval_reg <= THERMOCODE_IN(191 downto 183);
- when "011001" => interval_reg <= THERMOCODE_IN(199 downto 191);
- when "011010" => interval_reg <= THERMOCODE_IN(207 downto 199);
- when "011011" => interval_reg <= THERMOCODE_IN(215 downto 207);
- when "011100" => interval_reg <= THERMOCODE_IN(223 downto 215);
- when "011101" => interval_reg <= THERMOCODE_IN(231 downto 223);
- when "011110" => interval_reg <= THERMOCODE_IN(239 downto 231);
- when "011111" => interval_reg <= THERMOCODE_IN(247 downto 239);
- when "100000" => interval_reg <= THERMOCODE_IN(255 downto 247);
- when "100001" => interval_reg <= THERMOCODE_IN(263 downto 255);
- when "100010" => interval_reg <= THERMOCODE_IN(271 downto 263);
- when "100011" => interval_reg <= THERMOCODE_IN(279 downto 271);
- when "100100" => interval_reg <= THERMOCODE_IN(287 downto 279);
- when "100101" => interval_reg <= THERMOCODE_IN(295 downto 287);
- when "100110" => interval_reg <= THERMOCODE_IN(303 downto 295);
- when others => interval_reg <= (others => '0');
- end case;
- end if;
- end if;
- end process Interval_Selection;
-
- ROM_Encoder_1 : ROM_Encoder
- port map (
- Address => address_i,
- OutClock => CLK,
- OutClockEn => '1',
- Reset => rom_reset_i,
- Q => q_i);
- address_i <= start_2reg & interval_reg;
- rom_reset_i <= rom_reset_reg or RESET;
-
- --purpose : Register the ROM output
- Register_ROM : process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- q_reg <= (others => '0');
- q_2reg <= (others => '0');
- else
- q_reg <= q_i;
- q_2reg <= q_reg;
- end if;
- end if;
- end process Register_ROM;
-
- rom_done_i <= q_2reg(7);
- interval_binary <= q_2reg(2 downto 0);
-
- Binary_Code_Calculation : process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- binary_code_f <= (others => '0');
- binary_code_r <= (others => '0');
- BINARY_CODE_OUT <= (others => '0');
- FINISHED_OUT <= '0';
- BUSY_OUT <= '0';
- conversion_nr <= "00";
- rom_reset_reg <= '0';
- elsif START_IN = '1' then
- conversion_nr <= "00";
- rom_reset_reg <= '0';
- elsif conversion_nr = "11" then
- conversion_nr <= "11";
- rom_reset_reg <= '1';
- BINARY_CODE_OUT <= (others => '0');
- FINISHED_OUT <= '0';
- BUSY_OUT <= '0';
- elsif conversion_nr = "10" then
- binary_code_f <= binary_code_r;
- BINARY_CODE_OUT <= ('0' & binary_code_r) + ('0' & binary_code_f);
- FINISHED_OUT <= '1';
- BUSY_OUT <= '0';
- conversion_nr <= conversion_nr + 1;
- rom_reset_reg <= '1';
- elsif rom_done_i = '1' then
- binary_code_r <= (mux_control_4reg-1) & interval_binary;
- binary_code_f <= binary_code_r;
- BINARY_CODE_OUT <= (others => '0');
- FINISHED_OUT <= '0';
- conversion_nr <= conversion_nr + 1;
- rom_reset_reg <= '0';
- if conversion_nr = "01" then
- BUSY_OUT <= '0';
- else
- BUSY_OUT <= '1';
- end if;
- else
- binary_code_f <= (others => '0');
- binary_code_r <= (others => '0');
- BINARY_CODE_OUT <= (others => '0');
- FINISHED_OUT <= '0';
- BUSY_OUT <= '0';
- rom_reset_reg <= '0';
- end if;
- end if;
- end process Binary_Code_Calculation;
-
-
-
--------------------------------------------------------------------------------
--- DEBUG
--------------------------------------------------------------------------------
- ENCODER_DEBUG(8 downto 0) <= interval_reg;
-
-end behavioral;
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.all;
---use ieee.std_logic_arith.all;
---use ieee.numeric_std.all;
-
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
---library synplify;
---use synplify.attributes.all;
-
-
-entity Encoder_304_ROMsuz is
- port (
- RESET : in std_logic;
- CLK : in std_logic;
- START_IN : in std_logic;
- THERMOCODE_IN : in std_logic_vector(303 downto 0);
- FINISHED_OUT : out std_logic;
- BINARY_CODE_OUT : out std_logic_vector(9 downto 0);
- ENCODER_DEBUG : out std_logic_vector(31 downto 0)
- );
-end Encoder_304_ROMsuz;
-
-architecture Encoder_304_ROMsuz of Encoder_304_ROMsuz is
-
- -- component definitions
- component up_counter
- generic (
- NUMBER_OF_BITS : positive);
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
- UP_IN : in std_logic);
- end component;
---
- component LUT4
- generic(
- INIT : std_logic_vector);
- port (
- A, B, C, D : in std_ulogic;
- Z : out std_ulogic);
- end component;
-
- -- signal declerations
- signal clk_i : std_logic;
- signal rst_i : std_logic;
- signal start_in_i : std_logic;
- signal thermocode_i : std_logic_vector(303 downto 0) := x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
- signal P_lut : std_logic_vector(18 downto 0);
- signal P_one : std_logic_vector(18 downto 0);
- signal mux_control : std_logic_vector(4 downto 0);
- signal interval_tmp : std_logic_vector(17 downto 0);
- signal interval_i : std_logic_vector(17 downto 0);
- signal interval_bc : std_logic_vector(14 downto 0);
- signal interval_bc_norm : std_logic_vector(14 downto 0);
- signal interval_bc_bbl : std_logic_vector(14 downto 0);
- signal interval_binary : std_logic_vector(3 downto 0);
- signal counter_reset_i : std_logic;
- signal counter_up_i : std_logic;
- signal counter_out_i : std_logic_vector(2 downto 0);
- signal binary_code_f : std_logic_vector(8 downto 0);
- signal binary_code_r : std_logic_vector(8 downto 0);
- signal edge_type_i : std_logic; -- 0 => 0-1 edge, 1 => 1-0 edge
-
-begin
-
- clk_i <= CLK;
- rst_i <= RESET;
- start_in_i <= START_IN;
- thermocode_i <= THERMOCODE_IN;
-
- ENCODER_DEBUG <= (others => '0');
-
- --Component instantiations
-
- Process_Counter : up_counter
- generic map (
- NUMBER_OF_BITS => 3)
- port map (
- CLK => clk_i,
- RESET => counter_reset_i,
- COUNT_OUT => counter_out_i,
- UP_IN => counter_up_i);
-
- Interval_Determination_First : LUT4
- generic map (INIT => X"A815")
- port map (A => '1', B => '1', C => thermocode_i(0), D => edge_type_i,
- Z => P_lut(0));
---
- Interval_Determination : for i in 1 to 18 generate
- U : LUT4
- generic map (INIT => X"A815")
- port map (A => thermocode_i(16*i-2), B => thermocode_i(16*i-1), C => thermocode_i(16*i), D => edge_type_i,
- Z => P_lut(i));
- end generate Interval_Determination;
--------------------------------------------------------------------------------
-
- Change_Edge_Type : process (clk_i, rst_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' or counter_out_i = "111" then
- edge_type_i <= '0';
- elsif counter_out_i = "001" then
- edge_type_i <= '1';
- end if;
- end if;
- end process Change_Edge_Type;
-
- Gen_P_one : for i in 0 to 17 generate
- P_one(i) <= P_lut(i) and (not P_lut(i+1));
- end generate Gen_P_one;
-
- P_one_assign : process (edge_type_i, P_lut)
- begin
- if edge_type_i = '0' then
- P_one(18) <= P_lut(18);
- else
- P_one(18) <= '0';
- end if;
- end process P_one_assign;
-
- Interval_Number_to_Binary : process (clk_i, rst_i)
- begin -- The interval number with the 0-1 transition is converted from 1-of-N code to binary
- -- code for the control of the MUX.
- if rising_edge(clk_i) then
- if rst_i = '1' then
- mux_control <= (others => '0');
- else
- mux_control(0) <= P_one(0) or P_one(2) or P_one(4) or P_one(6) or P_one(8) or P_one(10) or
- P_one(12) or P_one(14) or P_one(16) or P_one(18);
- mux_control(1) <= P_one(1) or P_one(2) or P_one(5) or P_one(6) or P_one(9) or P_one(10) or
- P_one(13) or P_one(14) or P_one(17) or P_one(18);
- mux_control(2) <= P_one(3) or P_one(4) or P_one(5) or P_one(6) or P_one(11) or P_one(12) or
- P_one(13) or P_one(14);
- mux_control(3) <= P_one(7) or P_one(8) or P_one(9) or P_one(10) or P_one(11) or P_one(12) or
- P_one(13) or P_one(14);
- mux_control(4) <= P_one(15) or P_one(16) or P_one(17) or P_one(18);
- end if;
- end if;
- end process Interval_Number_to_Binary;
-
- Interval_Selection : process (mux_control, thermocode_i, edge_type_i)
- begin -- The interval with the 0-1 transition is selected.
- case mux_control is
- when "00001" => interval_tmp <= thermocode_i(16 downto 0) & edge_type_i;
- when "00010" => interval_tmp <= thermocode_i(32 downto 15);
- when "00011" => interval_tmp <= thermocode_i(48 downto 31);
- when "00100" => interval_tmp <= thermocode_i(64 downto 47);
- when "00101" => interval_tmp <= thermocode_i(80 downto 63);
- when "00110" => interval_tmp <= thermocode_i(96 downto 79);
- when "00111" => interval_tmp <= thermocode_i(112 downto 95);
- when "01000" => interval_tmp <= thermocode_i(128 downto 111);
- when "01001" => interval_tmp <= thermocode_i(144 downto 127);
- when "01010" => interval_tmp <= thermocode_i(160 downto 143);
- when "01011" => interval_tmp <= thermocode_i(176 downto 159);
- when "01100" => interval_tmp <= thermocode_i(192 downto 175);
- when "01101" => interval_tmp <= thermocode_i(208 downto 191);
- when "01110" => interval_tmp <= thermocode_i(224 downto 207);
- when "01111" => interval_tmp <= thermocode_i(240 downto 223);
- when "10000" => interval_tmp <= thermocode_i(256 downto 239);
- when "10001" => interval_tmp <= thermocode_i(272 downto 255);
- when "10010" => interval_tmp <= thermocode_i(288 downto 271);
- when "10011" => interval_tmp <= (not edge_type_i) & thermocode_i(303 downto 287);
- when others => interval_tmp <= (others => '1');
- end case;
- end process Interval_Selection;
-
- Assign_Interval : process (clk_i, rst_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' then
- interval_i <= (others => '1');
- elsif edge_type_i = '0' then
- interval_i <= interval_tmp;
- else
- interval_i <= not interval_tmp;
- end if;
- end if;
- end process Assign_Interval;
-
- Bubble_Correction_Normal : process (interval_bc_norm, interval_i)
- begin -- The bubble correction is done by detecting the "1100" code pattern
- interval_bc_norm(0) <= interval_i(3) and interval_i(2) and not(interval_i(1)) and not(interval_i(0));
- interval_bc_norm(1) <= interval_i(4) and interval_i(3) and not(interval_i(2)) and not(interval_i(1));
- interval_bc_norm(2) <= interval_i(5) and interval_i(4) and not(interval_i(3)) and not(interval_i(2));
- interval_bc_norm(3) <= interval_i(6) and interval_i(5) and not(interval_i(4)) and not(interval_i(3));
- interval_bc_norm(4) <= interval_i(7) and interval_i(6) and not(interval_i(5)) and not(interval_i(4));
- interval_bc_norm(5) <= interval_i(8) and interval_i(7) and not(interval_i(6)) and not(interval_i(5));
- interval_bc_norm(6) <= interval_i(9) and interval_i(8) and not(interval_i(7)) and not(interval_i(6));
- interval_bc_norm(7) <= interval_i(10) and interval_i(9) and not(interval_i(8)) and not(interval_i(7));
- interval_bc_norm(8) <= interval_i(11) and interval_i(10) and not(interval_i(9)) and not(interval_i(8));
- interval_bc_norm(9) <= interval_i(12) and interval_i(11) and not(interval_i(10)) and not(interval_i(9));
- interval_bc_norm(10) <= interval_i(13) and interval_i(12) and not(interval_i(11)) and not(interval_i(10));
- interval_bc_norm(11) <= interval_i(14) and interval_i(13) and not(interval_i(12)) and not(interval_i(11));
- interval_bc_norm(12) <= interval_i(15) and interval_i(14) and not(interval_i(13)) and not(interval_i(12));
- interval_bc_norm(13) <= interval_i(16) and interval_i(15) and not(interval_i(14)) and not(interval_i(13));
- interval_bc_norm(14) <= interval_i(17) and interval_i(16) and not(interval_i(15)) and not(interval_i(14));
- end process Bubble_Correction_Normal;
-
- Bubble_Correction_Bubble : process (interval_bc_bbl, interval_i)
- begin -- The bubble correction is done by detecting the "1010" code pattern
- interval_bc_bbl(0) <= interval_i(3) and not(interval_i(2)) and interval_i(1) and not(interval_i(0));
- interval_bc_bbl(1) <= interval_i(4) and not(interval_i(3)) and interval_i(2) and not(interval_i(1));
- interval_bc_bbl(2) <= interval_i(5) and not(interval_i(4)) and interval_i(3) and not(interval_i(2));
- interval_bc_bbl(3) <= interval_i(6) and not(interval_i(5)) and interval_i(4) and not(interval_i(3));
- interval_bc_bbl(4) <= interval_i(7) and not(interval_i(6)) and interval_i(5) and not(interval_i(4));
- interval_bc_bbl(5) <= interval_i(8) and not(interval_i(7)) and interval_i(6) and not(interval_i(5));
- interval_bc_bbl(6) <= interval_i(9) and not(interval_i(8)) and interval_i(7) and not(interval_i(6));
- interval_bc_bbl(7) <= interval_i(10) and not(interval_i(9)) and interval_i(8) and not(interval_i(7));
- interval_bc_bbl(8) <= interval_i(11) and not(interval_i(10)) and interval_i(9) and not(interval_i(8));
- interval_bc_bbl(9) <= interval_i(12) and not(interval_i(11)) and interval_i(10) and not(interval_i(9));
- interval_bc_bbl(10) <= interval_i(13) and not(interval_i(12)) and interval_i(11) and not(interval_i(10));
- interval_bc_bbl(11) <= interval_i(14) and not(interval_i(13)) and interval_i(12) and not(interval_i(11));
- interval_bc_bbl(12) <= interval_i(15) and not(interval_i(14)) and interval_i(13) and not(interval_i(12));
- interval_bc_bbl(13) <= interval_i(16) and not(interval_i(15)) and interval_i(14) and not(interval_i(13));
- interval_bc_bbl(14) <= interval_i(17) and not(interval_i(16)) and interval_i(15) and not(interval_i(14));
- end process Bubble_Correction_Bubble;
-
- interval_bc <= interval_bc_bbl or interval_bc_norm;
-
- Interval_Decoding : process (clk_i, rst_i)
- begin -- The decoding of the bubble corrected 1-of-N code is done by the OR gates
- if rising_edge(clk_i) then
- if rst_i = '1' then
- interval_binary <= (others => '0');
- else
- interval_binary(0) <= interval_bc(0) or interval_bc(2) or interval_bc(4) or interval_bc(6) or
- interval_bc(8) or interval_bc(10) or interval_bc(12) or interval_bc(14);
- interval_binary(1) <= interval_bc(1) or interval_bc(2) or interval_bc(5) or interval_bc(6) or
- interval_bc(9) or interval_bc(10) or interval_bc(13) or interval_bc(14);
- interval_binary(2) <= interval_bc(3) or interval_bc(4) or interval_bc(5) or interval_bc(6) or
- interval_bc(11) or interval_bc(12) or interval_bc(13) or interval_bc(14);
- interval_binary(3) <= interval_bc(7) or interval_bc(8) or interval_bc(9) or interval_bc(10) or
- interval_bc(11) or interval_bc(12) or interval_bc(13) or interval_bc(14);
- end if;
- end if;
- end process Interval_Decoding;
-
- Binary_Code_Calculation : process (clk_i, rst_i)
- begin
- if rising_edge(clk_i) then
- if rst_i = '1' then
- binary_code_f <= (others => '0');
- binary_code_r <= (others => '0');
- BINARY_CODE_OUT <= (others => '0');
- FINISHED_OUT <= '0';
- elsif counter_out_i = "010" then
- binary_code_f <= (mux_control-1) & interval_binary;
- elsif counter_out_i = "101" then
- binary_code_r <= (mux_control-1) & interval_binary;
- elsif counter_out_i = "110" then
- BINARY_CODE_OUT <= std_logic_vector(to_unsigned((to_integer(unsigned(binary_code_r)) + to_integer(unsigned(binary_code_f))), 10));
- FINISHED_OUT <= '1';
- else
- BINARY_CODE_OUT <= (others => '0');
- FINISHED_OUT <= '0';
- end if;
- end if;
- end process Binary_Code_Calculation;
-
- Counter_Countrol : process (clk_i, rst_i)
- begin -- The control of the "counter_up_i" signal
- if rising_edge(clk_i) then
- if rst_i = '1' then
- counter_up_i <= '0';
- counter_reset_i <= '1';
- elsif start_in_i = '1' then
- counter_up_i <= '1';
- elsif counter_out_i = "110" then
- counter_up_i <= '0';
- counter_reset_i <= '1';
- else
- counter_reset_i <= '0';
- end if;
- end if;
- end process Counter_Countrol;
-
-end Encoder_304_ROMsuz;
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.4
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 512 -width 32 -depth 512 -rdata_width 32 -regout -no_enable -pe -1 -pf -1 -e
-
--- Fri Nov 11 11:15:59 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity FIFO_32x512_OutReg is
- port (
- Data: in std_logic_vector(31 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(31 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end FIFO_32x512_OutReg;
-
-architecture Structure of FIFO_32x512_OutReg is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_g2b_xor_cluster_1: std_logic;
- signal r_g2b_xor_cluster_1: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal w_gdata_2: std_logic;
- signal w_gdata_3: std_logic;
- signal w_gdata_4: std_logic;
- signal w_gdata_5: std_logic;
- signal w_gdata_6: std_logic;
- signal w_gdata_7: std_logic;
- signal w_gdata_8: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal wptr_3: std_logic;
- signal wptr_4: std_logic;
- signal wptr_5: std_logic;
- signal wptr_6: std_logic;
- signal wptr_7: std_logic;
- signal wptr_8: std_logic;
- signal wptr_9: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal r_gdata_2: std_logic;
- signal r_gdata_3: std_logic;
- signal r_gdata_4: std_logic;
- signal r_gdata_5: std_logic;
- signal r_gdata_6: std_logic;
- signal r_gdata_7: std_logic;
- signal r_gdata_8: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal rptr_3: std_logic;
- signal rptr_4: std_logic;
- signal rptr_5: std_logic;
- signal rptr_6: std_logic;
- signal rptr_7: std_logic;
- signal rptr_8: std_logic;
- signal rptr_9: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal w_gcount_3: std_logic;
- signal w_gcount_4: std_logic;
- signal w_gcount_5: std_logic;
- signal w_gcount_6: std_logic;
- signal w_gcount_7: std_logic;
- signal w_gcount_8: std_logic;
- signal w_gcount_9: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal r_gcount_3: std_logic;
- signal r_gcount_4: std_logic;
- signal r_gcount_5: std_logic;
- signal r_gcount_6: std_logic;
- signal r_gcount_7: std_logic;
- signal r_gcount_8: std_logic;
- signal r_gcount_9: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal w_gcount_r23: std_logic;
- signal w_gcount_r3: std_logic;
- signal w_gcount_r24: std_logic;
- signal w_gcount_r4: std_logic;
- signal w_gcount_r25: std_logic;
- signal w_gcount_r5: std_logic;
- signal w_gcount_r26: std_logic;
- signal w_gcount_r6: std_logic;
- signal w_gcount_r27: std_logic;
- signal w_gcount_r7: std_logic;
- signal w_gcount_r28: std_logic;
- signal w_gcount_r8: std_logic;
- signal w_gcount_r29: std_logic;
- signal w_gcount_r9: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal r_gcount_w23: std_logic;
- signal r_gcount_w3: std_logic;
- signal r_gcount_w24: std_logic;
- signal r_gcount_w4: std_logic;
- signal r_gcount_w25: std_logic;
- signal r_gcount_w5: std_logic;
- signal r_gcount_w26: std_logic;
- signal r_gcount_w6: std_logic;
- signal r_gcount_w27: std_logic;
- signal r_gcount_w7: std_logic;
- signal r_gcount_w28: std_logic;
- signal r_gcount_w8: std_logic;
- signal r_gcount_w29: std_logic;
- signal r_gcount_w9: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal iwcount_3: std_logic;
- signal co0: std_logic;
- signal iwcount_4: std_logic;
- signal iwcount_5: std_logic;
- signal co1: std_logic;
- signal iwcount_6: std_logic;
- signal iwcount_7: std_logic;
- signal co2: std_logic;
- signal iwcount_8: std_logic;
- signal iwcount_9: std_logic;
- signal co4: std_logic;
- signal wcount_9: std_logic;
- signal co3: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal ircount_3: std_logic;
- signal co0_1: std_logic;
- signal ircount_4: std_logic;
- signal ircount_5: std_logic;
- signal co1_1: std_logic;
- signal ircount_6: std_logic;
- signal ircount_7: std_logic;
- signal co2_1: std_logic;
- signal ircount_8: std_logic;
- signal ircount_9: std_logic;
- signal co4_1: std_logic;
- signal rcount_9: std_logic;
- signal co3_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal wcount_r2: std_logic;
- signal wcount_r3: std_logic;
- signal rcount_2: std_logic;
- signal rcount_3: std_logic;
- signal co1_2: std_logic;
- signal wcount_r4: std_logic;
- signal wcount_r5: std_logic;
- signal rcount_4: std_logic;
- signal rcount_5: std_logic;
- signal co2_2: std_logic;
- signal w_g2b_xor_cluster_0: std_logic;
- signal wcount_r7: std_logic;
- signal rcount_6: std_logic;
- signal rcount_7: std_logic;
- signal co3_2: std_logic;
- signal wcount_r8: std_logic;
- signal empty_cmp_clr: std_logic;
- signal rcount_8: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal rcount_w2: std_logic;
- signal rcount_w3: std_logic;
- signal wcount_2: std_logic;
- signal wcount_3: std_logic;
- signal co1_3: std_logic;
- signal rcount_w4: std_logic;
- signal rcount_w5: std_logic;
- signal wcount_4: std_logic;
- signal wcount_5: std_logic;
- signal co2_3: std_logic;
- signal r_g2b_xor_cluster_0: std_logic;
- signal rcount_w7: std_logic;
- signal wcount_6: std_logic;
- signal wcount_7: std_logic;
- signal co3_3: std_logic;
- signal rcount_w8: std_logic;
- signal full_cmp_clr: std_logic;
- signal wcount_8: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "FIFO_32x512_OutReg.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
- attribute GSR of FF_101 : label is "ENABLED";
- attribute GSR of FF_100 : label is "ENABLED";
- attribute GSR of FF_99 : label is "ENABLED";
- attribute GSR of FF_98 : label is "ENABLED";
- attribute GSR of FF_97 : label is "ENABLED";
- attribute GSR of FF_96 : label is "ENABLED";
- attribute GSR of FF_95 : label is "ENABLED";
- attribute GSR of FF_94 : label is "ENABLED";
- attribute GSR of FF_93 : label is "ENABLED";
- attribute GSR of FF_92 : label is "ENABLED";
- attribute GSR of FF_91 : label is "ENABLED";
- attribute GSR of FF_90 : label is "ENABLED";
- attribute GSR of FF_89 : label is "ENABLED";
- attribute GSR of FF_88 : label is "ENABLED";
- attribute GSR of FF_87 : label is "ENABLED";
- attribute GSR of FF_86 : label is "ENABLED";
- attribute GSR of FF_85 : label is "ENABLED";
- attribute GSR of FF_84 : label is "ENABLED";
- attribute GSR of FF_83 : label is "ENABLED";
- attribute GSR of FF_82 : label is "ENABLED";
- attribute GSR of FF_81 : label is "ENABLED";
- attribute GSR of FF_80 : label is "ENABLED";
- attribute GSR of FF_79 : label is "ENABLED";
- attribute GSR of FF_78 : label is "ENABLED";
- attribute GSR of FF_77 : label is "ENABLED";
- attribute GSR of FF_76 : label is "ENABLED";
- attribute GSR of FF_75 : label is "ENABLED";
- attribute GSR of FF_74 : label is "ENABLED";
- attribute GSR of FF_73 : label is "ENABLED";
- attribute GSR of FF_72 : label is "ENABLED";
- attribute GSR of FF_71 : label is "ENABLED";
- attribute GSR of FF_70 : label is "ENABLED";
- attribute GSR of FF_69 : label is "ENABLED";
- attribute GSR of FF_68 : label is "ENABLED";
- attribute GSR of FF_67 : label is "ENABLED";
- attribute GSR of FF_66 : label is "ENABLED";
- attribute GSR of FF_65 : label is "ENABLED";
- attribute GSR of FF_64 : label is "ENABLED";
- attribute GSR of FF_63 : label is "ENABLED";
- attribute GSR of FF_62 : label is "ENABLED";
- attribute GSR of FF_61 : label is "ENABLED";
- attribute GSR of FF_60 : label is "ENABLED";
- attribute GSR of FF_59 : label is "ENABLED";
- attribute GSR of FF_58 : label is "ENABLED";
- attribute GSR of FF_57 : label is "ENABLED";
- attribute GSR of FF_56 : label is "ENABLED";
- attribute GSR of FF_55 : label is "ENABLED";
- attribute GSR of FF_54 : label is "ENABLED";
- attribute GSR of FF_53 : label is "ENABLED";
- attribute GSR of FF_52 : label is "ENABLED";
- attribute GSR of FF_51 : label is "ENABLED";
- attribute GSR of FF_50 : label is "ENABLED";
- attribute GSR of FF_49 : label is "ENABLED";
- attribute GSR of FF_48 : label is "ENABLED";
- attribute GSR of FF_47 : label is "ENABLED";
- attribute GSR of FF_46 : label is "ENABLED";
- attribute GSR of FF_45 : label is "ENABLED";
- attribute GSR of FF_44 : label is "ENABLED";
- attribute GSR of FF_43 : label is "ENABLED";
- attribute GSR of FF_42 : label is "ENABLED";
- attribute GSR of FF_41 : label is "ENABLED";
- attribute GSR of FF_40 : label is "ENABLED";
- attribute GSR of FF_39 : label is "ENABLED";
- attribute GSR of FF_38 : label is "ENABLED";
- attribute GSR of FF_37 : label is "ENABLED";
- attribute GSR of FF_36 : label is "ENABLED";
- attribute GSR of FF_35 : label is "ENABLED";
- attribute GSR of FF_34 : label is "ENABLED";
- attribute GSR of FF_33 : label is "ENABLED";
- attribute GSR of FF_32 : label is "ENABLED";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
-
-begin
- -- component instantiation statements
- AND2_t20: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t19: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t18: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t17: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t16: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t15: XOR2
- port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2);
-
- XOR2_t14: XOR2
- port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3);
-
- XOR2_t13: XOR2
- port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4);
-
- XOR2_t12: XOR2
- port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5);
-
- XOR2_t11: XOR2
- port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6);
-
- XOR2_t10: XOR2
- port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7);
-
- XOR2_t9: XOR2
- port map (A=>wcount_8, B=>wcount_9, Z=>w_gdata_8);
-
- XOR2_t8: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t7: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- XOR2_t6: XOR2
- port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2);
-
- XOR2_t5: XOR2
- port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3);
-
- XOR2_t4: XOR2
- port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4);
-
- XOR2_t3: XOR2
- port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5);
-
- XOR2_t2: XOR2
- port map (A=>rcount_6, B=>rcount_7, Z=>r_gdata_6);
-
- XOR2_t1: XOR2
- port map (A=>rcount_7, B=>rcount_8, Z=>r_gdata_7);
-
- XOR2_t0: XOR2
- port map (A=>rcount_8, B=>rcount_9, Z=>r_gdata_8);
-
- LUT4_23: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27,
- AD1=>w_gcount_r28, AD0=>w_gcount_r29,
- DO0=>w_g2b_xor_cluster_0);
-
- LUT4_22: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23,
- AD1=>w_gcount_r24, AD0=>w_gcount_r25,
- DO0=>w_g2b_xor_cluster_1);
-
- LUT4_21: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r28, AD2=>w_gcount_r29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r8);
-
- LUT4_20: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28,
- AD1=>w_gcount_r29, AD0=>scuba_vlo, DO0=>wcount_r7);
-
- LUT4_19: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26,
- AD1=>w_gcount_r27, AD0=>wcount_r8, DO0=>wcount_r5);
-
- LUT4_18: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25,
- AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4);
-
- LUT4_17: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24,
- AD1=>w_gcount_r25, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r3);
-
- LUT4_16: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r2);
-
- LUT4_15: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r21, AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_14: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1,
- AD1=>w_gcount_r20, AD0=>w_gcount_r21, DO0=>wcount_r0);
-
- LUT4_13: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w26, AD2=>r_gcount_w27,
- AD1=>r_gcount_w28, AD0=>r_gcount_w29,
- DO0=>r_g2b_xor_cluster_0);
-
- LUT4_12: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23,
- AD1=>r_gcount_w24, AD0=>r_gcount_w25,
- DO0=>r_g2b_xor_cluster_1);
-
- LUT4_11: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w28, AD2=>r_gcount_w29, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w8);
-
- LUT4_10: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w27, AD2=>r_gcount_w28,
- AD1=>r_gcount_w29, AD0=>scuba_vlo, DO0=>rcount_w7);
-
- LUT4_9: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26,
- AD1=>r_gcount_w27, AD0=>rcount_w8, DO0=>rcount_w5);
-
- LUT4_8: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25,
- AD1=>r_gcount_w26, AD0=>rcount_w7, DO0=>rcount_w4);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24,
- AD1=>r_gcount_w25, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w3);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>rcount_w2);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w21, AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_g2b_xor_cluster_0, AD2=>r_g2b_xor_cluster_1,
- AD1=>r_gcount_w20, AD0=>r_gcount_w21, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_9, AD2=>rcount_9, AD1=>w_gcount_r29,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_9, AD2=>wcount_9, AD1=>r_gcount_w29,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_0: PDPW16KC
- generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo,
- DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
- ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3,
- ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>wptr_6, ADW7=>wptr_7,
- ADW8=>wptr_8, BE0=>scuba_vhi, BE1=>scuba_vhi, BE2=>scuba_vhi,
- BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, CSW0=>scuba_vhi,
- CSW1=>scuba_vlo, CSW2=>scuba_vlo, ADR0=>scuba_vlo,
- ADR1=>scuba_vlo, ADR2=>scuba_vlo, ADR3=>scuba_vlo,
- ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>rptr_2,
- ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, ADR11=>rptr_6,
- ADR12=>rptr_7, ADR13=>rptr_8, CER=>scuba_vhi, CLKR=>RdClock,
- CSR0=>rden_i, CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset,
- DO0=>Q(18), DO1=>Q(19), DO2=>Q(20), DO3=>Q(21), DO4=>Q(22),
- DO5=>Q(23), DO6=>Q(24), DO7=>Q(25), DO8=>Q(26), DO9=>Q(27),
- DO10=>Q(28), DO11=>Q(29), DO12=>Q(30), DO13=>Q(31),
- DO14=>open, DO15=>open, DO16=>open, DO17=>open, DO18=>Q(0),
- DO19=>Q(1), DO20=>Q(2), DO21=>Q(3), DO22=>Q(4), DO23=>Q(5),
- DO24=>Q(6), DO25=>Q(7), DO26=>Q(8), DO27=>Q(9), DO28=>Q(10),
- DO29=>Q(11), DO30=>Q(12), DO31=>Q(13), DO32=>Q(14),
- DO33=>Q(15), DO34=>Q(16), DO35=>Q(17));
-
- FF_101: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_100: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_99: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_98: FD1P3DX
- port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_3);
-
- FF_97: FD1P3DX
- port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_4);
-
- FF_96: FD1P3DX
- port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_5);
-
- FF_95: FD1P3DX
- port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_6);
-
- FF_94: FD1P3DX
- port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_7);
-
- FF_93: FD1P3DX
- port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_8);
-
- FF_92: FD1P3DX
- port map (D=>iwcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_9);
-
- FF_91: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_90: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_89: FD1P3DX
- port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_88: FD1P3DX
- port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_3);
-
- FF_87: FD1P3DX
- port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_4);
-
- FF_86: FD1P3DX
- port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_5);
-
- FF_85: FD1P3DX
- port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_6);
-
- FF_84: FD1P3DX
- port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_7);
-
- FF_83: FD1P3DX
- port map (D=>w_gdata_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_8);
-
- FF_82: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_9);
-
- FF_81: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_80: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_79: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_78: FD1P3DX
- port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_3);
-
- FF_77: FD1P3DX
- port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_4);
-
- FF_76: FD1P3DX
- port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_5);
-
- FF_75: FD1P3DX
- port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_6);
-
- FF_74: FD1P3DX
- port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_7);
-
- FF_73: FD1P3DX
- port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_8);
-
- FF_72: FD1P3DX
- port map (D=>wcount_9, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_9);
-
- FF_71: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_70: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_69: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_68: FD1P3DX
- port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_3);
-
- FF_67: FD1P3DX
- port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_4);
-
- FF_66: FD1P3DX
- port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_5);
-
- FF_65: FD1P3DX
- port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_6);
-
- FF_64: FD1P3DX
- port map (D=>ircount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_7);
-
- FF_63: FD1P3DX
- port map (D=>ircount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_8);
-
- FF_62: FD1P3DX
- port map (D=>ircount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_9);
-
- FF_61: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_60: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_59: FD1P3DX
- port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_58: FD1P3DX
- port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_3);
-
- FF_57: FD1P3DX
- port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_4);
-
- FF_56: FD1P3DX
- port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_5);
-
- FF_55: FD1P3DX
- port map (D=>r_gdata_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_6);
-
- FF_54: FD1P3DX
- port map (D=>r_gdata_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_7);
-
- FF_53: FD1P3DX
- port map (D=>r_gdata_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_8);
-
- FF_52: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_9);
-
- FF_51: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_50: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_49: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_48: FD1P3DX
- port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_3);
-
- FF_47: FD1P3DX
- port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_4);
-
- FF_46: FD1P3DX
- port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_5);
-
- FF_45: FD1P3DX
- port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_6);
-
- FF_44: FD1P3DX
- port map (D=>rcount_7, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_7);
-
- FF_43: FD1P3DX
- port map (D=>rcount_8, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_8);
-
- FF_42: FD1P3DX
- port map (D=>rcount_9, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_9);
-
- FF_41: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_40: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_39: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_38: FD1S3DX
- port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3);
-
- FF_37: FD1S3DX
- port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4);
-
- FF_36: FD1S3DX
- port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5);
-
- FF_35: FD1S3DX
- port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6);
-
- FF_34: FD1S3DX
- port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7);
-
- FF_33: FD1S3DX
- port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8);
-
- FF_32: FD1S3DX
- port map (D=>w_gcount_9, CK=>RdClock, CD=>Reset, Q=>w_gcount_r9);
-
- FF_31: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_30: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_29: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_28: FD1S3DX
- port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3);
-
- FF_27: FD1S3DX
- port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4);
-
- FF_26: FD1S3DX
- port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5);
-
- FF_25: FD1S3DX
- port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6);
-
- FF_24: FD1S3DX
- port map (D=>r_gcount_7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w7);
-
- FF_23: FD1S3DX
- port map (D=>r_gcount_8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w8);
-
- FF_22: FD1S3DX
- port map (D=>r_gcount_9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w9);
-
- FF_21: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_20: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_19: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_18: FD1S3DX
- port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r23);
-
- FF_17: FD1S3DX
- port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r24);
-
- FF_16: FD1S3DX
- port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r25);
-
- FF_15: FD1S3DX
- port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r26);
-
- FF_14: FD1S3DX
- port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r27);
-
- FF_13: FD1S3DX
- port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r28);
-
- FF_12: FD1S3DX
- port map (D=>w_gcount_r9, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r29);
-
- FF_11: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23);
-
- FF_7: FD1S3DX
- port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24);
-
- FF_6: FD1S3DX
- port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25);
-
- FF_5: FD1S3DX
- port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w7, CK=>WrClock, CD=>rRst, Q=>r_gcount_w27);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w8, CK=>WrClock, CD=>rRst, Q=>r_gcount_w28);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w9, CK=>WrClock, CD=>rRst, Q=>r_gcount_w29);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1,
- NC0=>iwcount_2, NC1=>iwcount_3);
-
- w_gctr_2: CU2
- port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2,
- NC0=>iwcount_4, NC1=>iwcount_5);
-
- w_gctr_3: CU2
- port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3,
- NC0=>iwcount_6, NC1=>iwcount_7);
-
- w_gctr_4: CU2
- port map (CI=>co3, PC0=>wcount_8, PC1=>wcount_9, CO=>co4,
- NC0=>iwcount_8, NC1=>iwcount_9);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1,
- NC0=>ircount_2, NC1=>ircount_3);
-
- r_gctr_2: CU2
- port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1,
- NC0=>ircount_4, NC1=>ircount_5);
-
- r_gctr_3: CU2
- port map (CI=>co2_1, PC0=>rcount_6, PC1=>rcount_7, CO=>co3_1,
- NC0=>ircount_6, NC1=>ircount_7);
-
- r_gctr_4: CU2
- port map (CI=>co3_1, PC0=>rcount_8, PC1=>rcount_9, CO=>co4_1,
- NC0=>ircount_8, NC1=>ircount_9);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2,
- B1=>wcount_r3, CI=>co0_2, GE=>co1_2);
-
- empty_cmp_2: AGEB2
- port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4,
- B1=>wcount_r5, CI=>co1_2, GE=>co2_2);
-
- empty_cmp_3: AGEB2
- port map (A0=>rcount_6, A1=>rcount_7, B0=>w_g2b_xor_cluster_0,
- B1=>wcount_r7, CI=>co2_2, GE=>co3_2);
-
- empty_cmp_4: AGEB2
- port map (A0=>rcount_8, A1=>empty_cmp_set, B0=>wcount_r8,
- B1=>empty_cmp_clr, CI=>co3_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2,
- B1=>rcount_w3, CI=>co0_3, GE=>co1_3);
-
- full_cmp_2: AGEB2
- port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4,
- B1=>rcount_w5, CI=>co1_3, GE=>co2_3);
-
- full_cmp_3: AGEB2
- port map (A0=>wcount_6, A1=>wcount_7, B0=>r_g2b_xor_cluster_0,
- B1=>rcount_w7, CI=>co2_3, GE=>co3_3);
-
- full_cmp_4: AGEB2
- port map (A0=>wcount_8, A1=>full_cmp_set, B0=>rcount_w8,
- B1=>full_cmp_clr, CI=>co3_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of FIFO_32x512_OutReg is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.0
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 10 -data_width 8 -num_rows 1024 -memfile /home/ugur/Projects/encoder/source/rom_encoder.mem -memformat orca -cascade -1 -e
-
--- Thu Nov 24 15:38:57 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity ROM_Encoder is
- port (
- Address: in std_logic_vector(9 downto 0);
- OutClock: in std_logic;
- OutClockEn: in std_logic;
- Reset: in std_logic;
- Q: out std_logic_vector(7 downto 0));
-end ROM_Encoder;
-
-architecture Structure of ROM_Encoder is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component DP16KC
- generic (INITVAL_3F : in String; INITVAL_3E : in String;
- INITVAL_3D : in String; INITVAL_3C : in String;
- INITVAL_3B : in String; INITVAL_3A : in String;
- INITVAL_39 : in String; INITVAL_38 : in String;
- INITVAL_37 : in String; INITVAL_36 : in String;
- INITVAL_35 : in String; INITVAL_34 : in String;
- INITVAL_33 : in String; INITVAL_32 : in String;
- INITVAL_31 : in String; INITVAL_30 : in String;
- INITVAL_2F : in String; INITVAL_2E : in String;
- INITVAL_2D : in String; INITVAL_2C : in String;
- INITVAL_2B : in String; INITVAL_2A : in String;
- INITVAL_29 : in String; INITVAL_28 : in String;
- INITVAL_27 : in String; INITVAL_26 : in String;
- INITVAL_25 : in String; INITVAL_24 : in String;
- INITVAL_23 : in String; INITVAL_22 : in String;
- INITVAL_21 : in String; INITVAL_20 : in String;
- INITVAL_1F : in String; INITVAL_1E : in String;
- INITVAL_1D : in String; INITVAL_1C : in String;
- INITVAL_1B : in String; INITVAL_1A : in String;
- INITVAL_19 : in String; INITVAL_18 : in String;
- INITVAL_17 : in String; INITVAL_16 : in String;
- INITVAL_15 : in String; INITVAL_14 : in String;
- INITVAL_13 : in String; INITVAL_12 : in String;
- INITVAL_11 : in String; INITVAL_10 : in String;
- INITVAL_0F : in String; INITVAL_0E : in String;
- INITVAL_0D : in String; INITVAL_0C : in String;
- INITVAL_0B : in String; INITVAL_0A : in String;
- INITVAL_09 : in String; INITVAL_08 : in String;
- INITVAL_07 : in String; INITVAL_06 : in String;
- INITVAL_05 : in String; INITVAL_04 : in String;
- INITVAL_03 : in String; INITVAL_02 : in String;
- INITVAL_01 : in String; INITVAL_00 : in String;
- GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute MEM_LPC_FILE of ROM_Encoder_0_0_0 : label is "ROM_Encoder.lpc";
- attribute MEM_INIT_FILE of ROM_Encoder_0_0_0 : label is "rom_encoder.mem";
- attribute RESETMODE of ROM_Encoder_0_0_0 : label is "SYNC";
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- ROM_Encoder_0_0_0: DP16KC
- generic map (INITVAL_3F=> "0x00000000800008000081000000008100000000820000000000000000008200000000000000000083",
- INITVAL_3E=> "0x00000000000000000000000000000000000000830000000000000000000000000000000000000084",
- INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000084",
- INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085",
- INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000085",
- INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000086",
- INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000086",
- INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000087",
- INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000087",
- INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_17=> "0x00087000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0F=> "0x00087000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0B=> "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_07=> "0x00086000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_05=> "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_03=> "0x00085000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_02=> "0x00084000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_01=> "0x00084000000000000000000000000000000000000008300000000000000000000000000000000000",
- INITVAL_00=> "0x00083000000000000000000820000000000000000008200000000810000000081000800008000000",
- CSDECODE_B=> "0b111", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG",
- REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, DATA_WIDTH_A=> 18)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo,
- ADA3=>scuba_vlo, ADA4=>Address(0), ADA5=>Address(1),
- ADA6=>Address(2), ADA7=>Address(3), ADA8=>Address(4),
- ADA9=>Address(5), ADA10=>Address(6), ADA11=>Address(7),
- ADA12=>Address(8), ADA13=>Address(9), CEA=>OutClockEn,
- CLKA=>OutClock, OCEA=>OutClockEn, WEA=>scuba_vlo,
- CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>scuba_vlo,
- ADB5=>scuba_vlo, ADB6=>scuba_vlo, ADB7=>scuba_vlo,
- ADB8=>scuba_vlo, ADB9=>scuba_vlo, ADB10=>scuba_vlo,
- ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo,
- CEB=>scuba_vhi, CLKB=>scuba_vlo, OCEB=>scuba_vhi,
- WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>scuba_vlo, DOA0=>Q(0), DOA1=>Q(1),
- DOA2=>Q(2), DOA3=>Q(3), DOA4=>Q(4), DOA5=>Q(5), DOA6=>Q(6),
- DOA7=>Q(7), DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>open, DOB1=>open, DOB2=>open,
- DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
- DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of ROM_Encoder is
- for Structure
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
--- Module Version: 5.0
---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type bram -wp 00 -rp 1100 -addr_width 8 -data_width 4 -num_rows 256 -memfile /home/ugur/Projects/trb3/tdc_test/ipexpress/ROM_FIFO/rom0_mem_file.mem -memformat hex -cascade -1 -e
-
--- Fri Nov 11 12:43:08 2011
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity ROM_FIFO is
- port (
- Address: in std_logic_vector(7 downto 0);
- OutClock: in std_logic;
- OutClockEn: in std_logic;
- Reset: in std_logic;
- Q: out std_logic_vector(3 downto 0));
-end ROM_FIFO;
-
-architecture Structure of ROM_FIFO is
-
- -- internal signal declarations
- signal scuba_vhi: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component DP16KC
- generic (INITVAL_3F : in String; INITVAL_3E : in String;
- INITVAL_3D : in String; INITVAL_3C : in String;
- INITVAL_3B : in String; INITVAL_3A : in String;
- INITVAL_39 : in String; INITVAL_38 : in String;
- INITVAL_37 : in String; INITVAL_36 : in String;
- INITVAL_35 : in String; INITVAL_34 : in String;
- INITVAL_33 : in String; INITVAL_32 : in String;
- INITVAL_31 : in String; INITVAL_30 : in String;
- INITVAL_2F : in String; INITVAL_2E : in String;
- INITVAL_2D : in String; INITVAL_2C : in String;
- INITVAL_2B : in String; INITVAL_2A : in String;
- INITVAL_29 : in String; INITVAL_28 : in String;
- INITVAL_27 : in String; INITVAL_26 : in String;
- INITVAL_25 : in String; INITVAL_24 : in String;
- INITVAL_23 : in String; INITVAL_22 : in String;
- INITVAL_21 : in String; INITVAL_20 : in String;
- INITVAL_1F : in String; INITVAL_1E : in String;
- INITVAL_1D : in String; INITVAL_1C : in String;
- INITVAL_1B : in String; INITVAL_1A : in String;
- INITVAL_19 : in String; INITVAL_18 : in String;
- INITVAL_17 : in String; INITVAL_16 : in String;
- INITVAL_15 : in String; INITVAL_14 : in String;
- INITVAL_13 : in String; INITVAL_12 : in String;
- INITVAL_11 : in String; INITVAL_10 : in String;
- INITVAL_0F : in String; INITVAL_0E : in String;
- INITVAL_0D : in String; INITVAL_0C : in String;
- INITVAL_0B : in String; INITVAL_0A : in String;
- INITVAL_09 : in String; INITVAL_08 : in String;
- INITVAL_07 : in String; INITVAL_06 : in String;
- INITVAL_05 : in String; INITVAL_04 : in String;
- INITVAL_03 : in String; INITVAL_02 : in String;
- INITVAL_01 : in String; INITVAL_00 : in String;
- GSR : in String; WRITEMODE_B : in String;
- WRITEMODE_A : in String; CSDECODE_B : in String;
- CSDECODE_A : in String; REGMODE_B : in String;
- REGMODE_A : in String; DATA_WIDTH_B : in Integer;
- DATA_WIDTH_A : in Integer);
- port (DIA0: in std_logic; DIA1: in std_logic;
- DIA2: in std_logic; DIA3: in std_logic;
- DIA4: in std_logic; DIA5: in std_logic;
- DIA6: in std_logic; DIA7: in std_logic;
- DIA8: in std_logic; DIA9: in std_logic;
- DIA10: in std_logic; DIA11: in std_logic;
- DIA12: in std_logic; DIA13: in std_logic;
- DIA14: in std_logic; DIA15: in std_logic;
- DIA16: in std_logic; DIA17: in std_logic;
- ADA0: in std_logic; ADA1: in std_logic;
- ADA2: in std_logic; ADA3: in std_logic;
- ADA4: in std_logic; ADA5: in std_logic;
- ADA6: in std_logic; ADA7: in std_logic;
- ADA8: in std_logic; ADA9: in std_logic;
- ADA10: in std_logic; ADA11: in std_logic;
- ADA12: in std_logic; ADA13: in std_logic;
- CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic;
- WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic;
- CSA2: in std_logic; RSTA: in std_logic;
- DIB0: in std_logic; DIB1: in std_logic;
- DIB2: in std_logic; DIB3: in std_logic;
- DIB4: in std_logic; DIB5: in std_logic;
- DIB6: in std_logic; DIB7: in std_logic;
- DIB8: in std_logic; DIB9: in std_logic;
- DIB10: in std_logic; DIB11: in std_logic;
- DIB12: in std_logic; DIB13: in std_logic;
- DIB14: in std_logic; DIB15: in std_logic;
- DIB16: in std_logic; DIB17: in std_logic;
- ADB0: in std_logic; ADB1: in std_logic;
- ADB2: in std_logic; ADB3: in std_logic;
- ADB4: in std_logic; ADB5: in std_logic;
- ADB6: in std_logic; ADB7: in std_logic;
- ADB8: in std_logic; ADB9: in std_logic;
- ADB10: in std_logic; ADB11: in std_logic;
- ADB12: in std_logic; ADB13: in std_logic;
- CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic;
- WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic;
- CSB2: in std_logic; RSTB: in std_logic;
- DOA0: out std_logic; DOA1: out std_logic;
- DOA2: out std_logic; DOA3: out std_logic;
- DOA4: out std_logic; DOA5: out std_logic;
- DOA6: out std_logic; DOA7: out std_logic;
- DOA8: out std_logic; DOA9: out std_logic;
- DOA10: out std_logic; DOA11: out std_logic;
- DOA12: out std_logic; DOA13: out std_logic;
- DOA14: out std_logic; DOA15: out std_logic;
- DOA16: out std_logic; DOA17: out std_logic;
- DOB0: out std_logic; DOB1: out std_logic;
- DOB2: out std_logic; DOB3: out std_logic;
- DOB4: out std_logic; DOB5: out std_logic;
- DOB6: out std_logic; DOB7: out std_logic;
- DOB8: out std_logic; DOB9: out std_logic;
- DOB10: out std_logic; DOB11: out std_logic;
- DOB12: out std_logic; DOB13: out std_logic;
- DOB14: out std_logic; DOB15: out std_logic;
- DOB16: out std_logic; DOB17: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute MEM_LPC_FILE of ROM_FIFO_0_0_0 : label is "ROM_FIFO.lpc";
- attribute MEM_INIT_FILE of ROM_FIFO_0_0_0 : label is "rom0_mem_file.mem";
- attribute RESETMODE of ROM_FIFO_0_0_0 : label is "SYNC";
-
-begin
- -- component instantiation statements
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- ROM_FIFO_0_0_0: DP16KC
- generic map (INITVAL_3F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_3A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_39=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_38=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_37=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_36=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_35=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_34=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_33=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_32=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_31=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_30=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_2A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_29=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_28=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_27=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_26=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_25=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_24=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_23=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_22=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_21=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_20=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_0A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_09=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_08=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_07=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_06=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_05=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_04=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
- INITVAL_03=> "0x10010040100601004010080100401006010040100A01004010060100401008010040100601004010",
- INITVAL_02=> "0x0C010040100601004010080100401006010040100A01004010060100401008010040100601004010",
- INITVAL_01=> "0x0E010040100601004010080100401006010040100A01004010060100401008010040100601004010",
- INITVAL_00=> "0x0C010040100601004010080100401006010040100A01004010060100401008010040100601004010",
- CSDECODE_B=> "0b111", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
- WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", REGMODE_B=> "NOREG",
- REGMODE_A=> "NOREG", DATA_WIDTH_B=> 4, DATA_WIDTH_A=> 4)
- port map (DIA0=>scuba_vlo, DIA1=>scuba_vlo, DIA2=>scuba_vlo,
- DIA3=>scuba_vlo, DIA4=>scuba_vlo, DIA5=>scuba_vlo,
- DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo,
- DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo,
- DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo,
- DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo,
- ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>Address(0),
- ADA3=>Address(1), ADA4=>Address(2), ADA5=>Address(3),
- ADA6=>Address(4), ADA7=>Address(5), ADA8=>Address(6),
- ADA9=>Address(7), ADA10=>scuba_vlo, ADA11=>scuba_vlo,
- ADA12=>scuba_vlo, ADA13=>scuba_vlo, CEA=>OutClockEn,
- CLKA=>OutClock, OCEA=>OutClockEn, WEA=>scuba_vlo,
- CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo,
- RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo,
- DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo,
- DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo,
- DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo,
- DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo,
- DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo,
- DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo,
- ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>scuba_vlo,
- ADB5=>scuba_vlo, ADB6=>scuba_vlo, ADB7=>scuba_vlo,
- ADB8=>scuba_vlo, ADB9=>scuba_vlo, ADB10=>scuba_vlo,
- ADB11=>scuba_vlo, ADB12=>scuba_vlo, ADB13=>scuba_vlo,
- CEB=>scuba_vhi, CLKB=>scuba_vlo, OCEB=>scuba_vhi,
- WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo,
- CSB2=>scuba_vlo, RSTB=>scuba_vlo, DOA0=>Q(0), DOA1=>Q(1),
- DOA2=>Q(2), DOA3=>Q(3), DOA4=>open, DOA5=>open, DOA6=>open,
- DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open,
- DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open,
- DOA16=>open, DOA17=>open, DOB0=>open, DOB1=>open, DOB2=>open,
- DOB3=>open, DOB4=>open, DOB5=>open, DOB6=>open, DOB7=>open,
- DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open,
- DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open,
- DOB16=>open, DOB17=>open);
-
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of ROM_FIFO is
- for Structure
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:DP16KC use entity ecp3.DP16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-use ieee.std_logic_arith.all;
-
-entity Reference_Channel is
-
- generic (
- CHANNEL_ID : integer range 0 to 15);
- port (
- RESET_WR : in std_logic;
- RESET_RD : in std_logic;
- CLK_WR : in std_logic;
- CLK_RD : in std_logic;
---
- HIT_IN : in std_logic;
- READ_EN_IN : in std_logic;
- VALID_TMG_TRG_IN : in std_logic;
- SPIKE_DETECTED_IN : in std_logic;
- MULTI_TMG_TRG_IN : in std_logic;
- FIFO_DATA_OUT : out std_logic_vector(31 downto 0);
- FIFO_EMPTY_OUT : out std_logic;
- FIFO_FULL_OUT : out std_logic;
- COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
- TRIGGER_TIME_OUT : out std_logic_vector(10 downto 0); -- coarse time of the timing trigger
- REF_DEBUG_OUT : out std_logic_vector(31 downto 0)
---
--- Channel_DEBUG_01 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_02 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_03 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_04 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_05 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_06 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_07 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_08 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_09 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_10 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_11 : out std_logic_vector(31 downto 0);
--- Channel_DEBUG_12 : out std_logic_vector(31 downto 0)
- );
-
-end Reference_Channel;
-
-architecture Reference_Channel of Reference_Channel is
-
--------------------------------------------------------------------------------
--- Component Declarations
--------------------------------------------------------------------------------
-
- component Adder_304
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- DataA : in std_logic_vector(303 downto 0);
- DataB : in std_logic_vector(303 downto 0);
- ClkEn : in std_logic;
- Result : out std_logic_vector(303 downto 0));
- end component;
---
- component Encoder_304_Bit
- port (
- RESET : in std_logic;
- CLK : in std_logic;
- START_IN : in std_logic;
- THERMOCODE_IN : in std_logic_vector(303 downto 0);
- FINISHED_OUT : out std_logic;
- BINARY_CODE_OUT : out std_logic_vector(9 downto 0);
- BUSY_OUT : out std_logic;
- ENCODER_DEBUG : out std_logic_vector(31 downto 0));
- end component;
---
- --component Encoder_304_ROMsuz
- -- port (
- -- RESET : in std_logic;
- -- CLK : in std_logic;
- -- START_IN : in std_logic;
- -- THERMOCODE_IN : in std_logic_vector(303 downto 0);
- -- FINISHED_OUT : out std_logic;
- -- BINARY_CODE_OUT : out std_logic_vector(9 downto 0);
- -- ENCODER_DEBUG : out std_logic_vector(31 downto 0));
- --end component;
---
- --component Encoder_304_Sngl_ROMsuz
- -- port (
- -- RESET : in std_logic;
- -- CLK : in std_logic;
- -- START_IN : in std_logic;
- -- THERMOCODE_IN : in std_logic_vector(303 downto 0);
- -- FINISHED_OUT : out std_logic;
- -- BINARY_CODE_OUT : out std_logic_vector(9 downto 0);
- -- ENCODER_DEBUG : out std_logic_vector(31 downto 0));
- --end component;
---
- component FIFO_32x512_OutReg
- port (
- Data : in std_logic_vector(31 downto 0);
- WrClock : in std_logic;
- RdClock : in std_logic;
- WrEn : in std_logic;
- RdEn : in std_logic;
- Reset : in std_logic;
- RPReset : in std_logic;
- Q : out std_logic_vector(31 downto 0);
- Empty : out std_logic;
- Full : out std_logic);
- end component;
---
- component bit_sync
- generic (
- DEPTH : integer);
- port (
- RESET : in std_logic;
- CLK0 : in std_logic;
- CLK1 : in std_logic;
- D_IN : in std_logic;
- D_OUT : out std_logic);
- end component;
-
--------------------------------------------------------------------------------
-
--------------------------------------------------------------------------------
--- Signal Declarations
--------------------------------------------------------------------------------
-
- signal data_a_i : std_logic_vector(303 downto 0);
- signal data_b_i : std_logic_vector(303 downto 0);
- signal result_i : std_logic_vector(303 downto 0);
- signal result_reg : std_logic_vector(303 downto 0);
- signal hit_in_i : std_logic;
- signal hit_detect_i : std_logic;
- signal hit_detect_reg : std_logic;
- signal result_2_reg : std_logic;
- signal coarse_cntr_i : std_logic_vector(10 downto 0);
- signal hit_time_stamp_i : std_logic_vector(10 downto 0);
- signal hit_time_stamp_reg : std_logic_vector(10 downto 0);
- signal hit_time_stamp_reg2 : std_logic_vector(10 downto 0);
- signal hit_time_stamp_reg3 : std_logic_vector(10 downto 0);
- signal fine_counter_i : std_logic_vector(9 downto 0);
- signal fine_counter_reg : std_logic_vector(9 downto 0);
- signal encoder_start_i : std_logic;
- signal encoder_busy_i : std_logic;
- signal encoder_finished_i : std_logic;
- signal encoder_debug_i : std_logic_vector(31 downto 0);
- signal fifo_data_out_i : std_logic_vector(31 downto 0);
- signal fifo_data_in_i : std_logic_vector(31 downto 0);
- signal fifo_empty_i : std_logic;
- signal fifo_full_i : std_logic;
- signal fifo_wr_en_i : std_logic;
- signal fifo_rd_en_i : std_logic;
- signal valid_tmg_trg_i : std_logic;
- signal multi_tmg_trg_i : std_logic;
- signal spike_detected_i : std_logic;
- signal ff_array_en_i : std_logic := '1';
-
- type FSM is (IDLE, LOOK_FOR_VALIDITY, ENCODER_FINISHED, VALID_TMG_TRG_ARRIVED);
- signal FSM_CURRENT, FSM_NEXT : FSM;
- signal fifo_wr_en_fsm : std_logic;
- signal fsm_debug_i : std_logic_vector(3 downto 0);
- signal fsm_debug_fsm : std_logic_vector(3 downto 0);
-
- signal hit_buf : std_logic;
- attribute syn_keep : boolean;
- attribute syn_keep of hit_buf : signal is true;
- attribute syn_keep of hit_in_i : signal is true;
- attribute NOMERGE : string;
- attribute NOMERGE of hit_buf : signal is "true";
-
--------------------------------------------------------------------------------
-
-begin
-
- fifo_rd_en_i <= READ_EN_IN;
- coarse_cntr_i <= COARSE_COUNTER_IN;
-
--- -- purpose: Generates a pulse out of the hit signal on order to prevent second transition in the hit signal
--- Hit_Trigger : process (HIT_IN, hit_trig_reset_i, RESET_WR)
--- begin
--- if RESET_WR = '1' or hit_trig_reset_i = '1' then
--- hit_in_i <= '0';
--- elsif rising_edge(HIT_IN) then
--- hit_in_i <= '1';
--- end if;
--- end process Hit_Trigger;
-
- hit_in_i <= HIT_IN;
- hit_buf <= not hit_in_i;
-
- --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21)
- FC : Adder_304
- port map (
- CLK => CLK_WR,
- RESET => RESET_WR,
- DataA => data_a_i,
- DataB => data_b_i,
- ClkEn => '1', -- ff_array_en_i, --'1',
- Result => result_i);
- data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF";
- data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(hit_buf) & x"000000" & "00" & hit_buf;
-
- --FF_Array_Enable : process (hit_detect_i, encoder_busy_i)
- --begin
- -- if hit_detect_i = '1' then
- -- ff_array_en_i <= '0';
- -- elsif encoder_busy_i = '1' then
- -- ff_array_en_i <= '1';
- -- end if;
- --end process FF_Array_Enable;
-
- ----purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) single transition
- --FC : Adder_304
- -- port map (
- -- CLK => CLK_WR,
- -- RESET => RESET_WR,
- -- DataA => data_a_i,
- -- DataB => data_b_i,
- -- ClkEn => '1',
- -- Result => result_i);
- --data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
- --data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000000000" & "000" & hit_in_i;
-
- --purpose: Tapped Delay Line 288 (Carry Chain)
--- FC : Adder_288
--- port map (
--- CLK => CLK_WR,
--- RESET => RESET_WR,
--- DataA => data_a_i,
--- DataB => data_b_i,
--- ClkEn => '1',
--- Result => result_i);
--- data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
--- data_b_i <= x"00000000000000000000000000000000000000000000000000000000000000000000000" & "000" & hit_in_i;
-
- --purpose: Registers the 2nd bit of the carry chain & hit detection bit
- Hit_Register : process (CLK_WR, RESET_WR)
- begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
- result_2_reg <= '0';
- hit_detect_reg <= '0';
- else
- result_2_reg <= result_i(2);
- hit_detect_reg <= hit_detect_i;
- end if;
- end if;
- end process Hit_Register;
-
- --purpose: Detects the hit
- Hit_Detect : process (result_2_reg, result_i)
- begin
- hit_detect_i <= (not result_2_reg) and result_i(2); --result_2_reg and (not result_i(2));
- end process Hit_Detect;
-
- --purpose: Double Synchroniser
- Double_Syncroniser : process (CLK_WR)
- begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
- result_reg <= (others => '1');
- elsif hit_detect_i = '1' then --or hit_trig_reset_i = '1' then
- result_reg <= result_i;
- end if;
- end if;
- end process Double_Syncroniser;
-
--- Channel_DEBUG_01(0) <= result_reg(303);
-
- --purpose: Start Encoder and captures the time stamp of the hit
- Start_Encoder : process (CLK_WR)
- begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
- encoder_start_i <= '0';
- hit_time_stamp_i <= (others => '0');
- hit_time_stamp_reg <= (others => '0');
- hit_time_stamp_reg2 <= (others => '0');
- hit_time_stamp_reg3 <= (others => '0');
- elsif hit_detect_i = '1' then
- encoder_start_i <= '1';
- hit_time_stamp_i <= coarse_cntr_i-1;
- else
- encoder_start_i <= '0';
- hit_time_stamp_reg <= hit_time_stamp_i;
- hit_time_stamp_reg2 <= hit_time_stamp_reg;
- hit_time_stamp_reg3 <= hit_time_stamp_reg2;
- end if;
- end if;
- end process Start_Encoder;
-
- TRIGGER_TIME_OUT <= hit_time_stamp_i; -- coarse time of the timing trigger
-
- --purpose: Encoder
- Encoder : Encoder_304_Bit
- port map (
- RESET => RESET_WR,
- CLK => CLK_WR,
- START_IN => encoder_start_i,
- THERMOCODE_IN => result_reg, -- result_i, -- result_reg,
- FINISHED_OUT => encoder_finished_i,
- BINARY_CODE_OUT => fine_counter_i,
- BUSY_OUT => encoder_busy_i,
- ENCODER_DEBUG => encoder_debug_i);
-
- --Encoder : Encoder_304_ROMsuz
- -- port map (
- -- RESET => RESET_WR,
- -- CLK => CLK_WR,
- -- START_IN => encoder_start_i,
- -- THERMOCODE_IN => result_reg,
- -- FINISHED_OUT => encoder_finished_i,
- -- BINARY_CODE_OUT => fine_counter_i,
- -- ENCODER_DEBUG => encoder_debug_i);
-
- --Encoder : Encoder_304_Sngl_ROMsuz
- -- port map (
- -- RESET => RESET_WR,
- -- CLK => CLK_WR,
- -- START_IN => encoder_start_i,
- -- THERMOCODE_IN => result_reg,
- -- FINISHED_OUT => encoder_finished_i,
- -- BINARY_CODE_OUT => fine_counter_i,
- -- ENCODER_DEBUG => encoder_debug_i);
-
- Register_Binary_Code : process (CLK_WR, RESET_WR)
- begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
- fine_counter_reg <= (others => '0');
- elsif encoder_finished_i = '1' then
- fine_counter_reg <= fine_counter_i;
- end if;
- end if;
- end process Register_Binary_Code;
-
- FIFO : FIFO_32x512_OutReg
- port map (
- Data => fifo_data_in_i,
- WrClock => CLK_WR,
- RdClock => CLK_RD,
- WrEn => fifo_wr_en_i,
- RdEn => fifo_rd_en_i,
- Reset => RESET_RD,
- RPReset => RESET_RD,
- Q => fifo_data_out_i,
- Empty => fifo_empty_i,
- Full => fifo_full_i);
-
- fifo_data_in_i(31) <= '1'; -- data marker
- fifo_data_in_i(30 downto 28) <= "000"; -- reserved bits
- fifo_data_in_i(27 downto 22) <= conv_std_logic_vector(CHANNEL_ID, 6); -- channel number
- fifo_data_in_i(21 downto 12) <= fine_counter_reg; -- fine time from the encoder
- fifo_data_in_i(11) <= '1'; -- rising '1' or falling '0' edge
- fifo_data_in_i(10 downto 0) <= hit_time_stamp_reg3; -- hit time stamp
-
- Register_Outputs : process (CLK_RD, RESET_RD)
- begin
- if rising_edge(CLK_RD) then
- if RESET_RD = '1' then
- FIFO_DATA_OUT <= (others => '1');
- FIFO_EMPTY_OUT <= '0';
- FIFO_FULL_OUT <= '0';
- else
- FIFO_DATA_OUT <= fifo_data_out_i;
- FIFO_EMPTY_OUT <= fifo_empty_i;
- FIFO_FULL_OUT <= fifo_full_i;
- end if;
- end if;
- end process Register_Outputs;
-
- --purpose: FSM for controlling the validity of the timing signal
- FSM_CLK : process (CLK_WR, RESET_WR)
- begin
- if rising_edge(CLK_WR) then
- if RESET_WR = '1' then
- FSM_CURRENT <= IDLE;
- fifo_wr_en_i <= '0';
- fsm_debug_i <= (others => '0');
- else
- FSM_CURRENT <= FSM_NEXT;
- fifo_wr_en_i <= fifo_wr_en_fsm;
- fsm_debug_i <= fsm_debug_fsm;
- end if;
- end if;
- end process FSM_CLK;
-
- FSM_PROC : process (FSM_CURRENT, hit_detect_i, encoder_finished_i, valid_tmg_trg_i, multi_tmg_trg_i,
- spike_detected_i)
- begin
- fifo_wr_en_fsm <= '0';
- fsm_debug_fsm <= (others => '0');
-
- case (FSM_CURRENT) is
- when IDLE =>
- if hit_detect_i = '1' then
- FSM_NEXT <= LOOK_FOR_VALIDITY;
- fsm_debug_fsm <= x"1";
- else
- FSM_NEXT <= IDLE;
- fsm_debug_fsm <= x"2";
- end if;
-
- when LOOK_FOR_VALIDITY =>
- if encoder_finished_i = '1' then
- FSM_NEXT <= ENCODER_FINISHED;
- fsm_debug_fsm <= x"3";
- elsif valid_tmg_trg_i = '1' then
- FSM_NEXT <= VALID_TMG_TRG_ARRIVED;
- fsm_debug_fsm <= x"4";
- elsif multi_tmg_trg_i = '1' then
- FSM_NEXT <= IDLE;
- fsm_debug_fsm <= x"5";
- elsif spike_detected_i = '1' then
- FSM_NEXT <= IDLE;
- fsm_debug_fsm <= x"6";
- else
- FSM_NEXT <= LOOK_FOR_VALIDITY;
- fsm_debug_fsm <= x"7";
- end if;
-
- when ENCODER_FINISHED =>
- if valid_tmg_trg_i = '1' then
- FSM_NEXT <= IDLE;
- fifo_wr_en_fsm <= '1';
- fsm_debug_fsm <= x"8";
- elsif multi_tmg_trg_i = '1' then
- FSM_NEXT <= IDLE;
- fsm_debug_fsm <= x"9";
- elsif spike_detected_i = '1' then
- FSM_NEXT <= IDLE;
- fsm_debug_fsm <= x"A";
- else
- FSM_NEXT <= ENCODER_FINISHED;
- fsm_debug_fsm <= x"B";
- end if;
-
- when VALID_TMG_TRG_ARRIVED =>
- if encoder_finished_i = '1' then
- FSM_NEXT <= IDLE;
- fifo_wr_en_fsm <= '1';
- fsm_debug_fsm <= x"C";
- else
- FSM_NEXT <= VALID_TMG_TRG_ARRIVED;
- fsm_debug_fsm <= x"D";
- end if;
-
- when others =>
- FSM_NEXT <= IDLE;
- end case;
- end process FSM_PROC;
-
- bit_sync_1 : bit_sync
- generic map (
- DEPTH => 3)
- port map (
- RESET => RESET_WR,
- CLK0 => CLK_RD,
- CLK1 => CLK_WR,
- D_IN => VALID_TMG_TRG_IN,
- D_OUT => valid_tmg_trg_i);
- bit_sync_2 : bit_sync
- generic map (
- DEPTH => 3)
- port map (
- RESET => RESET_WR,
- CLK0 => CLK_RD,
- CLK1 => CLK_WR,
- D_IN => SPIKE_DETECTED_IN,
- D_OUT => spike_detected_i);
- bit_sync_3 : bit_sync
- generic map (
- DEPTH => 3)
- port map (
- RESET => RESET_WR,
- CLK0 => CLK_RD,
- CLK1 => CLK_WR,
- D_IN => MULTI_TMG_TRG_IN,
- D_OUT => multi_tmg_trg_i);
-
--------------------------------------------------------------------------------
--- Debug signals
--------------------------------------------------------------------------------
- REF_DEBUG_OUT(3 downto 0) <= fsm_debug_i;
- REF_DEBUG_OUT(4) <= hit_detect_i;
- REF_DEBUG_OUT(5) <= encoder_start_i;
- REF_DEBUG_OUT(6) <= encoder_finished_i;
- REF_DEBUG_OUT(7) <= valid_tmg_trg_i;
- REF_DEBUG_OUT(8) <= fifo_wr_en_i;
- REF_DEBUG_OUT(15 downto 9) <= fine_counter_reg(6 downto 0);
-
-end Reference_Channel;
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use IEEE.NUMERIC_STD.all;
-use STD.TEXTIO.all;
-use IEEE.STD_LOGIC_TEXTIO.all;
-
--- synopsys translate_off
--- library ecp2m;
--- use ecp2m.components.all;
--- synopsys translate_on
-
-entity TDC is
- generic (
- CHANNEL_NUMBER : integer range 0 to 64;
- STATUS_REG_NR : integer range 0 to 6;
- CONTROL_REG_NR : integer range 0 to 6);
- port (
- RESET : in std_logic;
- CLK_TDC : in std_logic;
- CLK_READOUT : in std_logic;
- REFERENCE_TIME : in std_logic;
- HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1);
- TRG_WIN_PRE : in std_logic_vector(10 downto 0);
- TRG_WIN_POST : in std_logic_vector(10 downto 0);
---
- -- Trigger signals from handler
- TRG_DATA_VALID_IN : in std_logic;
- VALID_TIMING_TRG_IN : in std_logic;
- VALID_NOTIMING_TRG_IN : in std_logic;
- INVALID_TRG_IN : in std_logic;
- TMGTRG_TIMEOUT_IN : in std_logic;
- SPIKE_DETECTED_IN : in std_logic;
- MULTI_TMG_TRG_IN : in std_logic;
- SPURIOUS_TRG_IN : in std_logic;
---
- TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
- TRG_CODE_IN : in std_logic_vector(7 downto 0);
- TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
- TRG_TYPE_IN : in std_logic_vector(3 downto 0);
---
- --Response to handler
- TRG_RELEASE_OUT : out std_logic;
- TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0);
- DATA_OUT : out std_logic_vector(31 downto 0);
- DATA_WRITE_OUT : out std_logic;
- DATA_FINISHED_OUT : out std_logic;
---
- TDC_DEBUG : out std_logic_vector(32*2**STATUS_REG_NR-1 downto 0);
- LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0);
- CONTROL_REG_IN : in std_logic_vector(32*2**CONTROL_REG_NR-1 downto 0)
- );
-end TDC;
-
-architecture TDC of TDC is
-
--------------------------------------------------------------------------------
--- Component Declarations
--------------------------------------------------------------------------------
-
- component Reference_Channel
- generic (
- CHANNEL_ID : integer range 0 to 0);
- port (
- RESET_WR : in std_logic;
- RESET_RD : in std_logic;
- CLK_WR : in std_logic;
- CLK_RD : in std_logic;
- HIT_IN : in std_logic;
- READ_EN_IN : in std_logic;
- VALID_TMG_TRG_IN : in std_logic;
- SPIKE_DETECTED_IN : in std_logic;
- MULTI_TMG_TRG_IN : in std_logic;
- FIFO_DATA_OUT : out std_logic_vector(31 downto 0);
- FIFO_EMPTY_OUT : out std_logic;
- FIFO_FULL_OUT : out std_logic;
- COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
- TRIGGER_TIME_OUT : out std_logic_vector(10 downto 0);
- REF_DEBUG_OUT : out std_logic_vector(31 downto 0));
- end component;
---
- component Channel
- generic (
- CHANNEL_ID : integer range 1 to 64);
- port (
- RESET_WR : in std_logic;
- RESET_RD : in std_logic;
- CLK_WR : in std_logic;
- CLK_RD : in std_logic;
- HIT_IN : in std_logic;
- READ_EN_IN : in std_logic;
- FIFO_DATA_OUT : out std_logic_vector(31 downto 0);
- FIFO_EMPTY_OUT : out std_logic;
- FIFO_FULL_OUT : out std_logic;
- COARSE_COUNTER_IN : in std_logic_vector(10 downto 0);
- LOST_HIT_NUMBER : out std_logic_vector(23 downto 0);
- MEASUREMENT_NUMBER : out std_logic_vector(23 downto 0);
- ENCODER_START_NUMBER : out std_logic_vector(23 downto 0);
- Channel_DEBUG_01 : out std_logic_vector(31 downto 0)
- );
- end component;
---
- component ROM_FIFO
- port (
- Address : in std_logic_vector(7 downto 0);
- OutClock : in std_logic;
- OutClockEn : in std_logic;
- Reset : in std_logic;
- Q : out std_logic_vector(3 downto 0));
- end component;
---
- component up_counter
- generic (
- NUMBER_OF_BITS : positive);
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
- UP_IN : in std_logic);
- end component;
---
- component Reset_Generator
- generic (
- RESET_SIGNAL_WIDTH : std_logic_vector(3 downto 0));
- port (
- CLK_IN : in std_logic;
- RESET_OUT : out std_logic);
- end component;
---
- component edge_to_pulse
- port (
- clock : in std_logic;
- en_clk : in std_logic;
- signal_in : in std_logic;
- pulse : out std_logic);
- end component;
---
- component signal_sync
- generic (
- WIDTH : integer;
- DEPTH : integer);
- port (
- RESET : in std_logic;
- CLK0 : in std_logic;
- CLK1 : in std_logic;
- D_IN : in std_logic_vector(WIDTH-1 downto 0);
- D_OUT : out std_logic_vector(WIDTH-1 downto 0));
- end component;
-
--------------------------------------------------------------------------------
--- Signal Declarations
--------------------------------------------------------------------------------
--- Output registers
- signal trg_release_reg : std_logic;
- signal trg_statusbit_reg : std_logic_vector(31 downto 0);
- signal data_out_reg : std_logic_vector(31 downto 0);
- signal data_wr_reg : std_logic;
- signal data_finished_reg : std_logic;
- signal fsm_debug_reg : std_logic_vector(7 downto 0);
- signal logic_analyser_reg : std_logic_vector(15 downto 0);
- signal logic_analyser_2reg : std_logic_vector(15 downto 0);
-
--- Clock - Reset Signals
- signal reset_tdc : std_logic;
-
--- ReadOut Signals
- signal trigger_time_i : std_logic_vector(10 downto 0);
- signal ref_time_coarse : std_logic_vector(10 downto 0);
- signal trg_win_cnt : std_logic_vector(15 downto 0);
- signal trg_win_cnt_up_i : std_logic;
- signal trg_win_end_i : std_logic;
- signal header_error_bits : std_logic_vector(15 downto 0);
- signal trailer_error_bits : std_logic_vector(15 downto 0);
-
- -- FSM Signals
- type FSM is (IDLE, WAIT_FOR_TRG_WIND_END,
- WAIT_FOR_LVL1_TRG_A, WAIT_FOR_LVL1_TRG_B, WAIT_FOR_LVL1_TRG_C,
- SEND_STATUS, SEND_TRG_RELEASE_A, SEND_TRG_RELEASE_B,
- WAIT_FOR_FIFO_NR_A, WAIT_FOR_FIFO_NR_B, WAIT_FOR_FIFO_NR_C,
- WR_HEADER, APPLY_MASK,
- RD_CHANNEL_A, RD_CHANNEL_B, RD_CHANNEL_C);
-
- signal FSM_CURRENT, FSM_NEXT : FSM;
- signal fsm_debug_fsm : std_logic_vector(7 downto 0);
- signal start_trg_win_cnt_i : std_logic;
- signal start_trg_win_cnt_fsm : std_logic;
- signal updt_index_fsm : std_logic;
- signal updt_index_i : std_logic;
- signal updt_mask_fsm : std_logic;
- signal updt_mask_i : std_logic;
- signal rd_en_fsm : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal rd_en_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal data_finished_fsm : std_logic;
- signal data_finished_i : std_logic;
- signal trg_release_fsm : std_logic;
- signal wr_header_fsm : std_logic;
- signal wr_header_i : std_logic;
- signal wr_ch_data_fsm : std_logic;
- signal wr_ch_data_i : std_logic;
- signal wr_ch_data_reg : std_logic;
- signal wr_status_fsm : std_logic;
- signal wr_status_i : std_logic;
- signal wrong_readout_fsm : std_logic;
- signal wrong_readout_i : std_logic;
- signal wr_trailer_fsm : std_logic;
- signal wr_trailer_i : std_logic;
-
--- Other Signals
- signal fifo_full_i : std_logic;
- signal mask_i : std_logic_vector(CHANNEL_NUMBER downto 0);
- signal fifo_nr : integer range 0 to CHANNEL_NUMBER := CHANNEL_NUMBER;
- signal fifo_nr_next : integer range 0 to CHANNEL_NUMBER := CHANNEL_NUMBER;
-
- signal TW_pre : std_logic_vector(10 downto 0);
- signal TW_post : std_logic_vector(10 downto 0);
- signal channel_hit_time : std_logic_vector(10 downto 0);
- signal trg_win_l : std_logic;
- signal trg_win_r : std_logic;
---
- type Std_Logic_8_array is array (0 to (CHANNEL_NUMBER/8-1)) of std_logic_vector(3 downto 0);
- signal fifo_nr_hex : Std_Logic_8_array;
---
- signal coarse_cnt : std_logic_vector(10 downto 0);
- signal channel_full_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal channel_empty_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal channel_empty_reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal channel_empty_2reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal channel_empty_3reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal channel_empty_4reg : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
---
- type channel_data_array is array (0 to CHANNEL_NUMBER) of std_logic_vector(31 downto 0);
- signal channel_data_i : channel_data_array;
- signal channel_data_reg : channel_data_array;
- signal channel_data_2reg : channel_data_array;
- signal channel_data_3reg : channel_data_array;
- signal channel_data_4reg : channel_data_array;
---
- signal hit_in_i : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
-
--------------------------------------------------------------------------------
--- Slow Control Signals
--------------------------------------------------------------------------------
- signal ch_en_i : std_logic_vector(63 downto 0);
-
--------------------------------------------------------------------------------
--- Statistics Signals
--------------------------------------------------------------------------------
- type statistics_array_12 is array (1 to CHANNEL_NUMBER-1) of std_logic_vector(11 downto 0);
- type statistics_array_24 is array (1 to CHANNEL_NUMBER-1) of std_logic_vector(23 downto 0);
- signal trig_number : std_logic_vector(23 downto 0);
- signal valid_tmg_trig_number : std_logic_vector(23 downto 0);
- signal valid_timing_trg_pulse : std_logic;
- signal valid_NOtmg_trig_number : std_logic_vector(23 downto 0);
- signal valid_notiming_trg_pulse : std_logic;
- signal invalid_trig_number : std_logic_vector(23 downto 0);
- signal invalid_trg_pulse : std_logic;
- signal multi_tmg_trig_number : std_logic_vector(23 downto 0);
- signal multi_tmg_trg_pulse : std_logic;
- signal spurious_trig_number : std_logic_vector(23 downto 0);
- signal spurious_trg_pulse : std_logic;
- signal wrong_readout_number : std_logic_vector(23 downto 0);
- signal spike_number : std_logic_vector(23 downto 0);
- signal spike_detected_pulse : std_logic;
- signal idle_i : std_logic;
- signal idle_fsm : std_logic;
- signal idle_time : std_logic_vector(23 downto 0);
- signal readout_i : std_logic;
- signal readout_fsm : std_logic;
- signal readout_time : std_logic_vector(23 downto 0);
- signal wait_i : std_logic;
- signal wait_fsm : std_logic;
- signal wait_time : std_logic_vector(23 downto 0);
- signal empty_channels : std_logic_vector(CHANNEL_NUMBER-1 downto 0);
- signal total_empty_channel : std_logic_vector(23 downto 0);
- signal channel_lost_hits : statistics_array_24;
- signal channel_measurement : statistics_array_24;
- signal channel_encoder_start_number : statistics_array_24;
- signal stop_status_i : std_logic;
-
--------------------------------------------------------------------------------
--- test signals
--------------------------------------------------------------------------------
- signal ref_debug_i : std_logic_vector(31 downto 0);
- type channel_debug_array is array (1 to CHANNEL_NUMBER-1) of std_logic_vector(31 downto 0);
- signal channel_debug_01_i : channel_debug_array;
--- signal fsm_state_reg : std_logic_vector(31 downto 0);
- signal control_reg_200 : std_logic_vector(3 downto 0);
--------------------------------------------------------------------------------
-
-begin
--------------------------------------------------------------------------------
--- The Reset Signal Genaration (Synchronous with the fine time clock)
--------------------------------------------------------------------------------
- The_Reset_Generator : Reset_Generator
- generic map (
- RESET_SIGNAL_WIDTH => x"F")
- port map (
- CLK_IN => CLK_TDC,
- RESET_OUT => reset_tdc);
-
--------------------------------------------------------------------------------
--- COMPONENT INSTANTINIATIONS
--------------------------------------------------------------------------------
- --Reference time measurement
- The_Reference_Time : Reference_Channel
- generic map (
- CHANNEL_ID => 0)
- port map (
- RESET_WR => reset_tdc,
- RESET_RD => RESET,
- CLK_WR => CLK_TDC,
- CLK_RD => CLK_READOUT,
- HIT_IN => REFERENCE_TIME,
- READ_EN_IN => rd_en_i(0),
- VALID_TMG_TRG_IN => VALID_TIMING_TRG_IN,
- SPIKE_DETECTED_IN => SPIKE_DETECTED_IN,
- MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN,
- FIFO_DATA_OUT => channel_data_i(0),
- FIFO_EMPTY_OUT => channel_empty_i(0),
- FIFO_FULL_OUT => channel_full_i(0),
- COARSE_COUNTER_IN => coarse_cnt,
- TRIGGER_TIME_OUT => trigger_time_i,
- REF_DEBUG_OUT => ref_debug_i);
-
- -- Channel enable signals
- GEN_Channel_Enable : for i in 1 to CHANNEL_NUMBER-1 generate
- hit_in_i(i) <= HIT_IN(i) and ch_en_i(i);
- end generate GEN_Channel_Enable;
- ch_en_i <= CONTROL_REG_IN(3*32+31 downto 2*32+0);
-
- -- Channels
- GEN_Channels : for i in 1 to CHANNEL_NUMBER - 1 generate
- Channels : Channel
- generic map (
- CHANNEL_ID => i)
- port map (
- RESET_WR => reset_tdc,
- RESET_RD => RESET,
- CLK_WR => CLK_TDC,
- CLK_RD => CLK_READOUT,
- HIT_IN => hit_in_i(i),
- READ_EN_IN => rd_en_i(i),
- FIFO_DATA_OUT => channel_data_i(i),
- FIFO_EMPTY_OUT => channel_empty_i(i),
- FIFO_FULL_OUT => channel_full_i(i),
- COARSE_COUNTER_IN => coarse_cnt,
- LOST_HIT_NUMBER => channel_lost_hits(i),
- MEASUREMENT_NUMBER => channel_measurement(i),
- ENCODER_START_NUMBER => channel_encoder_start_number(i),
- Channel_DEBUG_01 => channel_debug_01_i(i));
- end generate GEN_Channels;
- channel_data_i(CHANNEL_NUMBER) <= x"FFFFFFFF";
-
- -- Common Coarse counter
- The_Coarse_Counter : up_counter
- generic map (
- NUMBER_OF_BITS => 11)
- port map (
- CLK => CLK_TDC,
- RESET => reset_tdc,
- COUNT_OUT => coarse_cnt,
- UP_IN => '1');
-
--------------------------------------------------------------------------------
--- READOUT
--------------------------------------------------------------------------------
-
--- Reference Time (Coarse)
-
- -- purpose: If the timing trigger is valid, the coarse time of the reference
- -- time is registered in order to be used in trigger window calculations
- Reference_Coarse_Time : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- ref_time_coarse <= (others => '0');
- elsif VALID_TIMING_TRG_IN = '1' then
- ref_time_coarse <= trigger_time_i;
- end if;
- end if;
- end process Reference_Coarse_Time;
--------------------------------------------------------------------------------
-
--- Trigger Window
-
- --purpose: Generates trigger window end signal
- Check_Trg_Win_End_Conrollers : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- trg_win_cnt <= x"0000";
- trg_win_end_i <= '0';
- trg_win_cnt_up_i <= '0';
- elsif start_trg_win_cnt_i = '1' then
- trg_win_cnt <= x"0001";
- trg_win_cnt_up_i <= '1';
- elsif trg_win_cnt = TRG_WIN_POST then
- trg_win_cnt <= x"0000";
- trg_win_end_i <= '1';
- trg_win_cnt_up_i <= '0';
- elsif trg_win_cnt_up_i = '1' then
- trg_win_cnt <= trg_win_cnt + 1;
- else
- trg_win_end_i <= '0';
- end if;
- end if;
- end process Check_Trg_Win_End_Conrollers;
-
- --purpose: Calculates the position of the trigger window edges
- Trg_Win_Calculation : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- TW_pre <= (others => '0');
- TW_post <= (others => '0');
- --channel_hit_time <= (others => '0');
- else
- TW_pre <= ref_time_coarse - TRG_WIN_PRE;
- TW_post <= ref_time_coarse + TRG_WIN_POST;
- end if;
- end if;
- end process Trg_Win_Calculation;
-
- channel_hit_time <= channel_data_i(fifo_nr)(10 downto 0);
-
- --purpose: Controls if the data coming from the channel is greater than the
- --trigger window pre-edge
- Check_Trg_Win_Left : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- trg_win_l <= '0';
- elsif TW_pre <= channel_hit_time then
- trg_win_l <= '1';
- else
- trg_win_l <= '0';
- end if;
- end if;
- end process Check_Trg_Win_Left;
-
- --purpose: Controls if the data coming from the channel is smaller than the
- --trigger window post-edge
- Check_Trg_Win_Right : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- trg_win_r <= '0';
- elsif channel_hit_time <= TW_post then
- trg_win_r <= '1';
- else
- trg_win_r <= '0';
- end if;
- end if;
- end process Check_Trg_Win_Right;
--------------------------------------------------------------------------------
--- Creating mask and Generating the fifo nr to be read
-
- -- purpose: Creats and updates the mask to determine the non-empty FIFOs
- CREAT_MASK : process (CLK_READOUT)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- mask_i <= (others => '1');
- empty_channels <= (others => '1');
- elsif trg_win_end_i = '1' then
- mask_i(CHANNEL_NUMBER-1 downto 0) <= channel_empty_i;
- empty_channels(CHANNEL_NUMBER-1 downto 0) <= channel_empty_i;
- elsif updt_mask_i = '1' then
- mask_i(fifo_nr) <= '1';
- end if;
- end if;
- end process CREAT_MASK;
-
- GEN : for i in 0 to (CHANNEL_NUMBER/8-1) generate
- ROM : ROM_FIFO
- port map (
- Address => mask_i(8*(i+1)-1 downto 8*i),
- OutClock => CLK_READOUT,
- OutClockEn => '1',
- Reset => RESET,
- Q => fifo_nr_hex(i));
- end generate GEN;
-
- -- purpose: Generates number of the FIFO, to be read, in integer
- CON_FIFO_NR_HEX_TO_INT : process (CLK_READOUT)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- fifo_nr_next <= CHANNEL_NUMBER;
- elsif fifo_nr_hex(0)(3) /= '1' then
- fifo_nr_next <= conv_integer("00000" & fifo_nr_hex(0)(2 downto 0));
- --elsif fifo_nr_hex(1)(3) /= '1' then
- -- fifo_nr_next <= conv_integer("00001" & fifo_nr_hex(1)(2 downto 0));
- --elsif fifo_nr_hex(2)(3) /= '1' then
- -- fifo_nr_next <= conv_integer("00010" & fifo_nr_hex(2)(2 downto 0));
- --elsif fifo_nr_hex(3)(3) /= '1' then
- -- fifo_nr_next <= conv_integer("00011" & fifo_nr_hex(3)(2 downto 0));
- --elsif fifo_nr_hex(4)(3) /= '1' then
- -- fifo_nr_next <= conv_integer("00100" & fifo_nr_hex(4)(2 downto 0));
- --elsif fifo_nr_hex(5)(3) /= '1' then
- -- fifo_nr_next <= conv_integer("00101" & fifo_nr_hex(5)(2 downto 0));
- --elsif fifo_nr_hex(6)(3) /= '1' then
- -- fifo_nr_next <= conv_integer("00110" & fifo_nr_hex(6)(2 downto 0));
- --elsif fifo_nr_hex(7)(3) /= '1' then
- -- fifo_nr_next <= conv_integer("00111" & fifo_nr_hex(7)(2 downto 0));
- else
- fifo_nr_next <= CHANNEL_NUMBER;
- end if;
- end if;
- end process CON_FIFO_NR_HEX_TO_INT;
-
- --purpose: Updates the index number for the array signals
- UPDATE_INDEX_NR : process (CLK_READOUT)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- fifo_nr <= CHANNEL_NUMBER;
- elsif updt_index_i = '1' then
- fifo_nr <= fifo_nr_next;
- end if;
- end if;
- end process UPDATE_INDEX_NR;
--------------------------------------------------------------------------------
--- Data Out, Data Write and Data Finished assigning according to the control
--- signals from the readout final-state-machine.
-
- Data_Out_MUX : process (CLK_READOUT, RESET)
- variable i : integer := 0;
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- data_out_reg <= (others => '1');
- data_wr_reg <= '0';
- else
- if wr_header_i = '1' then
- data_out_reg <= "001" & "0000000000000" & header_error_bits;
- data_wr_reg <= '1';
- elsif wr_ch_data_reg = '1' and CONTROL_REG_IN(1*32+31) = '1' then
- if (TW_pre(10) = '1' and ref_time_coarse(10) = '0') or (TW_post(10) = '0' and ref_time_coarse(10) = '1') then
- if (trg_win_l = '0' and trg_win_r = '1') or (trg_win_l = '1' and trg_win_r = '0') then
--- data_out_reg <= "1000" & channel_data_i(fifo_nr)(27 downto 0);
- data_out_reg <= channel_data_reg(fifo_nr);
- data_wr_reg <= '1';
- else
--- data_out_reg <= (others => '1');
- data_wr_reg <= '0';
- end if;
- else
- if (trg_win_l = '1' and trg_win_r = '1') then
--- data_out_reg <= "1000" & channel_data_i(fifo_nr)(27 downto 0);
- data_out_reg <= channel_data_reg(fifo_nr);
- data_wr_reg <= '1';
- else
--- data_out_reg <= (others => '1');
- data_wr_reg <= '0';
- end if;
- end if;
- elsif wr_ch_data_reg = '1' and CONTROL_REG_IN(1*32+31) = '0' then
- data_out_reg <= "1000" & channel_data_reg(fifo_nr)(27 downto 0);
- data_wr_reg <= '1';
- elsif wr_status_i = '1' then
- case i is
- when 0 => data_out_reg <= "010" & "00000" & valid_tmg_trig_number;
- when 1 => data_out_reg <= "010" & "00001" & trig_number;
- when 2 => data_out_reg <= "010" & "00010" & valid_NOtmg_trig_number;
- when 3 => data_out_reg <= "010" & "00011" & invalid_trig_number;
- when 4 => data_out_reg <= "010" & "00100" & multi_tmg_trig_number;
- when 5 => data_out_reg <= "010" & "00101" & spurious_trig_number;
- when 6 => data_out_reg <= "010" & "00110" & wrong_readout_number;
- when 7 => data_out_reg <= "010" & "00111" & spike_number;
- when 8 => data_out_reg <= "010" & "01000" & idle_time;
- when 9 => data_out_reg <= "010" & "01001" & wait_time;
- stop_status_i <= '1';
- when 10 => data_out_reg <= "010" & "01010" & total_empty_channel;
- when others => null;
- end case;
- data_wr_reg <= '1';
- i := i+1;
- elsif wr_trailer_i = '1' then
- data_out_reg <= "011" & "0000000000000" & trailer_error_bits;
- data_wr_reg <= '1';
- else
--- data_out_reg <= (others => '1');
- data_wr_reg <= '0';
- end if;
- end if;
- end if;
- end process Data_Out_MUX;
-
- DATA_OUT <= data_out_reg;
- DATA_WRITE_OUT <= data_wr_reg;
- DATA_FINISHED_OUT <= data_finished_reg;
- TRG_RELEASE_OUT <= trg_release_reg;
- TRG_STATUSBIT_OUT <= trg_statusbit_reg;
-
------------------------------------------------------------------------------
--- Data delay
-
- Delay_Channel_Data : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- channel_data_reg <= (others => x"00000000");
- channel_data_2reg <= (others => x"00000000");
- channel_data_3reg <= (others => x"00000000");
- channel_data_4reg <= (others => x"00000000");
- channel_empty_reg <= (others => '0');
- channel_empty_2reg <= (others => '0');
- channel_empty_3reg <= (others => '0');
- channel_empty_4reg <= (others => '0');
- else
- channel_data_reg <= channel_data_i;
- channel_data_2reg <= channel_data_reg;
- channel_data_3reg <= channel_data_2reg;
- channel_data_4reg <= channel_data_3reg;
- channel_empty_reg <= channel_empty_i;
- channel_empty_2reg <= channel_empty_reg;
- channel_empty_3reg <= channel_empty_2reg;
- channel_empty_4reg <= channel_empty_3reg;
- end if;
- end if;
- end process Delay_Channel_Data;
-
--------------------------------------------------------------------------------
--- Readout Final-State-Machine
--------------------------------------------------------------------------------
-
- --purpose: FSM for writing data
- FSM_CLK : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- FSM_CURRENT <= IDLE;
- fsm_debug_reg <= x"00";
- start_trg_win_cnt_i <= '0';
- updt_index_i <= '0';
- updt_mask_i <= '0';
- rd_en_i <= (others => '0');
- wr_ch_data_i <= '0';
- wr_ch_data_reg <= '0';
- wr_header_i <= '0';
- wr_status_i <= '0';
- data_finished_i <= '0';
- data_finished_reg <= '0';
- trg_release_reg <= '0';
- wrong_readout_i <= '0';
- idle_i <= '0';
- readout_i <= '0';
- wait_i <= '0';
- else
- FSM_CURRENT <= FSM_NEXT;
- fsm_debug_reg <= fsm_debug_fsm;
- start_trg_win_cnt_i <= start_trg_win_cnt_fsm;
- updt_index_i <= updt_index_fsm;
- updt_mask_i <= updt_mask_fsm;
- rd_en_i <= rd_en_fsm;
- wr_ch_data_i <= wr_ch_data_fsm;
- wr_ch_data_reg <= wr_ch_data_i;
- wr_header_i <= wr_header_fsm;
- wr_status_i <= wr_status_fsm;
- data_finished_i <= data_finished_fsm;
- data_finished_reg <= data_finished_i;
- trg_release_reg <= trg_release_fsm;
- wrong_readout_i <= wrong_readout_fsm;
- idle_i <= idle_fsm;
- readout_i <= readout_fsm;
- wait_i <= wait_fsm;
- end if;
- end if;
- end process FSM_CLK;
-
- FSM_PROC : process (FSM_CURRENT, VALID_TIMING_TRG_IN, VALID_NOTIMING_TRG_IN, trg_win_end_i, fifo_nr_next,
- fifo_nr, channel_empty_reg, TRG_DATA_VALID_IN, INVALID_TRG_IN, TMGTRG_TIMEOUT_IN,
- TRG_TYPE_IN, SPURIOUS_TRG_IN, stop_status_i)
- begin
-
- start_trg_win_cnt_fsm <= '0';
- updt_index_fsm <= '0';
- updt_mask_fsm <= '0';
- rd_en_fsm <= (others => '0');
- wr_ch_data_fsm <= '0';
- wr_header_fsm <= '0';
- data_finished_fsm <= '0';
- trg_release_fsm <= '0';
- wrong_readout_fsm <= '0';
- idle_fsm <= '0';
- readout_fsm <= '0';
- wait_fsm <= '0';
- wr_status_fsm <= '0';
-
- case (FSM_CURRENT) is
- when IDLE =>
- if VALID_TIMING_TRG_IN = '1' then
- FSM_NEXT <= WAIT_FOR_TRG_WIND_END;
- start_trg_win_cnt_fsm <= '1';
- fsm_debug_fsm <= x"01";
- elsif VALID_NOTIMING_TRG_IN = '1' then
- if TRG_TYPE_IN = x"E" then
- FSM_NEXT <= SEND_STATUS;
- fsm_debug_fsm <= x"02";
- else
- FSM_NEXT <= SEND_TRG_RELEASE_A;
- fsm_debug_fsm <= x"03";
- end if;
- wr_header_fsm <= '1';
- elsif INVALID_TRG_IN = '1' then
- FSM_NEXT <= SEND_TRG_RELEASE_A;
- fsm_debug_fsm <= x"04";
- else
- FSM_NEXT <= IDLE;
- fsm_debug_fsm <= x"05";
- end if;
- idle_fsm <= '1';
---
- when WAIT_FOR_TRG_WIND_END =>
- if trg_win_end_i = '1' then --or CONTROL_REG_IN(1*32+31) = '0' then
- FSM_NEXT <= WR_HEADER;
- fsm_debug_fsm <= x"06";
- else
- FSM_NEXT <= WAIT_FOR_TRG_WIND_END;
- fsm_debug_fsm <= x"07";
- end if;
- wait_fsm <= '1';
--------------------------------------------------------------------------------
--- Readout process starts
- when WR_HEADER =>
- FSM_NEXT <= WAIT_FOR_FIFO_NR_A;
- wr_header_fsm <= '1';
- fsm_debug_fsm <= x"08";
- readout_fsm <= '1';
-
- when WAIT_FOR_FIFO_NR_A =>
- FSM_NEXT <= WAIT_FOR_FIFO_NR_B;
- updt_index_fsm <= '1';
- fsm_debug_fsm <= x"0A";
- wait_fsm <= '1';
-
- --when WAIT_FOR_FIFO_NR_B =>
- -- FSM_NEXT <= WAIT_FOR_FIFO_NR_C;
- -- updt_mask_fsm <= '1';
- -- fsm_debug_fsm <= x"0B";
- -- wait_fsm <= '1';
-
- when WAIT_FOR_FIFO_NR_B =>
- FSM_NEXT <= APPLY_MASK;
- fsm_debug_fsm <= x"0C";
- wait_fsm <= '1';
-
- when APPLY_MASK =>
- if fifo_nr_next = CHANNEL_NUMBER then
- FSM_NEXT <= WAIT_FOR_LVL1_TRG_A;
- data_finished_fsm <= '1';
- fsm_debug_fsm <= x"0D";
- else
- FSM_NEXT <= RD_CHANNEL_A;
- rd_en_fsm(fifo_nr) <= '1';
- updt_mask_fsm <= '1';
- fsm_debug_fsm <= x"0E";
- end if;
- wait_fsm <= '1';
-
- when RD_CHANNEL_A =>
- FSM_NEXT <= RD_CHANNEL_B;
- rd_en_fsm(fifo_nr) <= '1';
- fsm_debug_fsm <= x"0F";
- readout_fsm <= '1';
-
- when RD_CHANNEL_B =>
- FSM_NEXT <= RD_CHANNEL_C;
- rd_en_fsm(fifo_nr) <= '1';
- fsm_debug_fsm <= x"10";
- readout_fsm <= '1';
-
- when RD_CHANNEL_C =>
- if channel_empty_reg(fifo_nr) = '1' then
- FSM_NEXT <= WAIT_FOR_FIFO_NR_B; -- APPLY_MASK;
- wr_ch_data_fsm <= '0';
- updt_index_fsm <= '1';
- fsm_debug_fsm <= x"11";
- else
- FSM_NEXT <= RD_CHANNEL_C;
- wr_ch_data_fsm <= '1';
- rd_en_fsm(fifo_nr) <= '1';
- fsm_debug_fsm <= x"12";
- end if;
- readout_fsm <= '1';
--------------------------------------------------------------------------------
- when WAIT_FOR_LVL1_TRG_A =>
- if TRG_DATA_VALID_IN = '1' then
- FSM_NEXT <= WAIT_FOR_LVL1_TRG_B;
- fsm_debug_fsm <= x"13";
- elsif TMGTRG_TIMEOUT_IN = '1' then
- FSM_NEXT <= IDLE;
- fsm_debug_fsm <= x"14";
- else
- FSM_NEXT <= WAIT_FOR_LVL1_TRG_A;
- fsm_debug_fsm <= x"15";
- end if;
- wait_fsm <= '1';
---
- when WAIT_FOR_LVL1_TRG_B =>
- FSM_NEXT <= WAIT_FOR_LVL1_TRG_C;
- fsm_debug_fsm <= x"16";
- wait_fsm <= '1';
---
- when WAIT_FOR_LVL1_TRG_C =>
- if SPURIOUS_TRG_IN = '1' then
- wrong_readout_fsm <= '1';
- end if;
- FSM_NEXT <= SEND_TRG_RELEASE_A;
- fsm_debug_fsm <= x"17";
- wait_fsm <= '1';
---
- when SEND_STATUS => -- here the status of the TDC should be sent
- if stop_status_i = '1' then
- FSM_NEXT <= SEND_TRG_RELEASE_A;
- data_finished_fsm <= '1';
- fsm_debug_fsm <= x"18";
- else
- FSM_NEXT <= SEND_STATUS;
- wr_status_fsm <= '1';
- fsm_debug_fsm <= x"19";
- end if;
---
- when SEND_TRG_RELEASE_A =>
- FSM_NEXT <= SEND_TRG_RELEASE_B;
- trg_release_fsm <= '1';
- fsm_debug_fsm <= x"1A";
---
- when SEND_TRG_RELEASE_B =>
- FSM_NEXT <= IDLE;
- fsm_debug_fsm <= x"1B";
---
- when others =>
- FSM_NEXT <= IDLE;
- fsm_debug_fsm <= x"FF";
- end case;
- end process FSM_PROC;
-
--------------------------------------------------------------------------------
--- Header-Trailor Error & Warning Bits
--------------------------------------------------------------------------------
- -- Error, warning bits set in the header
- header_error_bits(15 downto 2) <= (others => '0');
- header_error_bits(0) <= '0';
- --header_error_bits(0) <= lost_hit_i; -- if there is at least one lost hit (can be more if the FIFO is full).
- header_error_bits(1) <= fifo_full_i; -- if the channel FIFO is full.
- --header_error_bits(2) <= fifo_almost_full_i; -- if the channel FIFO is almost full.
-
- -- Error, warning bits set in the trailer
- trailer_error_bits <= (others => '0');
- -- trailer_error_bits (0) <= wrong_readout_i; -- if there is a wrong readout because of a spurious timing trigger.
-
- -- Information bits sent after a status trigger
- -- <= lost_hits_nr_i; -- total number of lost hits.
-
- fifo_full_i <= --channel_full_i(15) or channel_full_i(14) or channel_full_i(13) or channel_full_i(12) or
- --channel_full_i(11) or channel_full_i(10) or channel_full_i(9) or channel_full_i(8) or
- channel_full_i(7) or channel_full_i(6) or channel_full_i(5) or channel_full_i(4) or
- channel_full_i(3) or channel_full_i(2) or channel_full_i(1) or channel_full_i(0);
-
--------------------------------------------------------------------------------
--- Debug and statistics words
--------------------------------------------------------------------------------
-
- edge_to_pulse_1 : edge_to_pulse
- port map (
- clock => CLK_READOUT,
- en_clk => '1',
- signal_in => VALID_TIMING_TRG_IN,
- pulse => valid_timing_trg_pulse);
-
- edge_to_pulse_2 : edge_to_pulse
- port map (
- clock => CLK_READOUT,
- en_clk => '1',
- signal_in => VALID_NOTIMING_TRG_IN,
- pulse => valid_notiming_trg_pulse);
-
- edge_to_pulse_3 : edge_to_pulse
- port map (
- clock => CLK_READOUT,
- en_clk => '1',
- signal_in => INVALID_TRG_IN,
- pulse => invalid_trg_pulse);
-
- edge_to_pulse_4 : edge_to_pulse
- port map (
- clock => CLK_READOUT,
- en_clk => '1',
- signal_in => MULTI_TMG_TRG_IN,
- pulse => multi_tmg_trg_pulse);
-
- edge_to_pulse_5 : edge_to_pulse
- port map (
- clock => CLK_READOUT,
- en_clk => '1',
- signal_in => SPURIOUS_TRG_IN,
- pulse => spurious_trg_pulse);
-
- edge_to_pulse_6 : edge_to_pulse
- port map (
- clock => CLK_READOUT,
- en_clk => '1',
- signal_in => SPIKE_DETECTED_IN,
- pulse => spike_detected_pulse);
-
- -- purpose: Internal trigger number counter (only valid triggers)
- Statistics_Trigger_Number : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- trig_number <= (others => '0');
- elsif valid_timing_trg_pulse = '1' or valid_notiming_trg_pulse = '1' then
- trig_number <= trig_number + 1;
- end if;
- end if;
- end process Statistics_Trigger_Number;
-
- -- purpose: Internal valid timing trigger number counter
- Statistics_Valid_Timing_Trigger_Number : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- valid_tmg_trig_number <= (others => '0');
- elsif valid_timing_trg_pulse = '1' then
- valid_tmg_trig_number <= valid_tmg_trig_number + 1;
- end if;
- end if;
- end process Statistics_Valid_Timing_Trigger_Number;
-
- -- purpose: Internal valid NOtiming trigger number counter
- Statistics_Valid_NoTiming_Trigger_Number : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- valid_NOtmg_trig_number <= (others => '0');
- elsif valid_notiming_trg_pulse = '1' then
- valid_NOtmg_trig_number <= valid_NOtmg_trig_number + 1;
- end if;
- end if;
- end process Statistics_Valid_NoTiming_Trigger_Number;
-
- -- purpose: Internal invalid trigger number counter
- Statistics_Invalid_Trigger_Number : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- invalid_trig_number <= (others => '0');
- elsif invalid_trg_pulse = '1' then
- invalid_trig_number <= invalid_trig_number + 1;
- end if;
- end if;
- end process Statistics_Invalid_Trigger_Number;
-
- -- purpose: Internal multi timing trigger number counter
- Statistics_Multi_Timing_Trigger_Number : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- multi_tmg_trig_number <= (others => '0');
- elsif multi_tmg_trg_pulse = '1' then
- multi_tmg_trig_number <= multi_tmg_trig_number + 1;
- end if;
- end if;
- end process Statistics_Multi_Timing_Trigger_Number;
-
- -- purpose: Internal spurious trigger number counter
- Statistics_Spurious_Trigger_Number : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- spurious_trig_number <= (others => '0');
- elsif spurious_trg_pulse = '1' then
- spurious_trig_number <= spurious_trig_number + 1;
- end if;
- end if;
- end process Statistics_Spurious_Trigger_Number;
-
- -- purpose: Number of wrong readout becasue of spurious trigger
- Statistics_Wrong_Readout_Number : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- wrong_readout_number <= (others => '0');
- elsif wrong_readout_i = '1' then
- wrong_readout_number <= wrong_readout_number + 1;
- end if;
- end if;
- end process Statistics_Wrong_Readout_Number;
-
- -- purpose: Internal spike number counter
- Statistics_Spike_Number : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- spike_number <= (others => '0');
- elsif spike_detected_pulse = '1' then
- spike_number <= spike_number + 1;
- end if;
- end if;
- end process Statistics_Spike_Number;
-
- -- purpose: IDLE time of the TDC readout
- Statistics_Idle_Time : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- idle_time <= (others => '0');
- elsif idle_i = '1' then
- idle_time <= idle_time + 1;
- end if;
- end if;
- end process Statistics_Idle_Time;
-
- -- purpose: Readout and Wait time of the TDC readout
- Statistics_Readout_Wait_Time : process (CLK_READOUT, RESET)
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- readout_time <= (others => '0');
- wait_time <= (others => '0');
- elsif readout_i = '1' then
- readout_time <= readout_time + 1;
- elsif wait_i = '1' then
- wait_time <= wait_time + 1;
- end if;
- end if;
- end process Statistics_Readout_Wait_Time;
-
- -- purpose: Empty channel number
- Statistics_Empty_Channel_Number : process (CLK_READOUT, RESET)
- variable i : integer := CHANNEL_NUMBER;
- begin
- if rising_edge(CLK_READOUT) then
- if RESET = '1' then
- total_empty_channel <= (others => '0');
- i := CHANNEL_NUMBER;
- elsif trg_win_end_i = '1' then
- i := 0;
- elsif i = CHANNEL_NUMBER then
- i := i;
- elsif empty_channels(i) = '1' then
- total_empty_channel <= total_empty_channel + 1;
- i := i + 1;
- else
- i := i + 1;
- end if;
- end if;
- end process Statistics_Empty_Channel_Number;
-
-
--------------------------------------------------------------------------------
--- Logic Analyser Signals
--------------------------------------------------------------------------------
- signal_sync_1 : signal_sync
- generic map (
- WIDTH => 4,
- DEPTH => 4)
- port map (
- RESET => reset_tdc,
- CLK0 => CLK_READOUT,
- CLK1 => CLK_TDC,
- D_IN => CONTROL_REG_IN(3 downto 0),
- D_OUT => control_reg_200);
-
-
--- Logic Analyser and Test Signals
- --REG_LOGIC_ANALYSER_OUTPUT : process (CLK_READOUT, RESET)
- --begin
- -- if rising_edge(CLK_READOUT) then
- -- if RESET = '1' then
- -- logic_analyser_reg <= (others => '0');
- -- elsif CONTROL_REG_IN(3 downto 0) = x"1" then TRBNET connections debugging
- -- logic_analyser_reg(7 downto 0) <= fsm_debug_reg;
- -- logic_analyser_reg(8) <= REFERENCE_TIME;
- -- logic_analyser_reg(9) <= VALID_TIMING_TRG_IN;
- -- logic_analyser_reg(10) <= VALID_NOTIMING_TRG_IN;
- -- logic_analyser_reg(11) <= INVALID_TRG_IN;
- -- logic_analyser_reg(12) <= TRG_DATA_VALID_IN;
- -- logic_analyser_reg(13) <= data_wr_reg;
- -- logic_analyser_reg(14) <= data_finished_reg;
- -- logic_analyser_reg(15) <= trg_release_reg;
- -- elsif CONTROL_REG_IN(3 downto 0) = x"2" then Reference channel debugging
- -- logic_analyser_reg <= ref_debug_i(15 downto 0);
- -- elsif CONTROL_REG_IN(3 downto 0) = x"3" then Hit input debugging
- -- logic_analyser_reg(7 downto 1) <= HIT_IN(7 downto 1);
- -- elsif CONTROL_REG_IN(3 downto 0) = x"4" then -- Hit input debugging
- -- logic_analyser_reg(15 downto 0) <= HIT_IN(31 downto 16);
- -- elsif CONTROL_REG_IN(3 downto 0) = x"5" then -- Hit input debugging
- -- logic_analyser_reg(15 downto 0) <= HIT_IN(47 downto 32);
- -- elsif CONTROL_REG_IN(3 downto 0) = x"6" then -- Hit input debugging
- -- logic_analyser_reg(15 downto 0) <= HIT_IN(63 downto 48);
- -- logic_analyser_reg(15 downto 7) <= (others => '0');
- -- elsif CONTROL_REG_IN(3 downto 0) = x"7" then Data out
- -- logic_analyser_reg(7 downto 0) <= fsm_debug_reg;
- -- logic_analyser_reg(8) <= REFERENCE_TIME;
- -- logic_analyser_reg(13) <= data_wr_reg;
- -- logic_analyser_reg(12 downto 9) <= data_out_reg(25 downto 22);
- -- logic_analyser_reg(14) <= data_out_reg(26);
- -- logic_analyser_reg(15) <= RESET;
-
- -- elsif CONTROL_REG_IN(3 downto 0) = x"8" then Data out
- -- logic_analyser_reg(0) <= HIT_IN(2);
- -- logic_analyser_reg(1) <= CLK_TDC;
- -- logic_analyser_reg(2) <= channel_debug_01_i(2)(1); encoder_start
- -- logic_analyser_reg(3) <= channel_debug_01_i(2)(2); fifo_wr_en
- -- logic_analyser_reg(7 downto 4) <= channel_debug_01_i(2)(6 downto 3); interval register
- -- logic_analyser_reg(12 downto 9) <= channel_debug_01_i(2)(10 downto 7); interval register
- -- logic_analyser_reg(14) <= channel_debug_01_i(2)(11); interval register
- -- logic_analyser_reg(8) <= REFERENCE_TIME;
- -- logic_analyser_reg(13) <= data_wr_reg;
- -- logic_analyser_reg(15) <= RESET;
-
- -- elsif CONTROL_REG_IN(3 downto 0) = x"9" then Data out
- -- logic_analyser_reg(0) <= HIT_IN(3);
- -- logic_analyser_reg(1) <= CLK_TDC;
- -- logic_analyser_reg(2) <= channel_debug_01_i(3)(1); encoder_start
- -- logic_analyser_reg(3) <= channel_debug_01_i(3)(2); fifo_wr_en
- -- logic_analyser_reg(7 downto 4) <= channel_debug_01_i(3)(6 downto 3); interval register
- -- logic_analyser_reg(12 downto 9) <= channel_debug_01_i(3)(10 downto 7); interval register
- -- logic_analyser_reg(14) <= channel_debug_01_i(3)(11); interval register
- -- logic_analyser_reg(8) <= REFERENCE_TIME;
- -- logic_analyser_reg(13) <= data_wr_reg;
- -- logic_analyser_reg(15) <= RESET;
-
- -- end if;
- -- end if;
- --end process REG_LOGIC_ANALYSER_OUTPUT;
-
-
--- REG_LOGIC_ANALYSER_OUTPUT : process (CLK_TDC, reset_tdc)
--- begin
--- if rising_edge(CLK_TDC) then
--- if reset_tdc = '1' then
--- logic_analyser_reg <= (others => '0');
--- logic_analyser_2reg <= (others => '0');
--- elsif CONTROL_REG_IN(3 downto 0) = x"1" then --TRBNET connections debugging
--- logic_analyser_reg(0) <= HIT_IN(3);
--- logic_analyser_reg(1) <= RESET;
--- logic_analyser_reg(2) <= channel_debug_01_i(3)(1); --encoder_start
--- logic_analyser_reg(3) <= channel_debug_01_i(3)(2); --fifo_wr_en
--- logic_analyser_reg(7 downto 4) <= channel_debug_01_i(3)(6 downto 3); --interval register
--- logic_analyser_reg(12 downto 9) <= channel_debug_01_i(3)(10 downto 7); --interval register
--- logic_analyser_reg(14) <= channel_debug_01_i(3)(11); --interval register
--- logic_analyser_reg(8) <= REFERENCE_TIME;
----- logic_analyser_reg(13) <= data_wr_reg;
--- logic_analyser_2reg <= logic_analyser_reg;
--- else
--- logic_analyser_reg <= (others => '0');
--- logic_analyser_2reg <= logic_analyser_reg;
--- end if;
--- end if;
--- end process REG_LOGIC_ANALYSER_OUTPUT;
-
- --LOGIC_ANALYSER_OUT(14 downto 0) <= logic_analyser_2reg(14 downto 0);
- --LOGIC_ANALYSER_OUT(15) <= CLK_TDC;
-
--------------------------------------------------------------------------------
--- STATUS REGISTERS
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--- Register 0x80
--------------------------------------------------------------------------------
- TDC_DEBUG(7 downto 0) <= fsm_debug_reg;
---
--- TDC_DEBUG(15 downto 8) <=
---
--- TDC_DEBUG(23 downto 16) <=
---
--- TDC_DEBUG(27 downto 24) <=
---
--- TDC_DEBUG(31 downto 28) <=
--------------------------------------------------------------------------------
--- Register 0x81
--------------------------------------------------------------------------------
- TDC_DEBUG(1*32+CHANNEL_NUMBER-1 downto 1*32+0) <= channel_empty_i;
--------------------------------------------------------------------------------
--- Register 0x82
--------------------------------------------------------------------------------
--- TDC_DEBUG(2*32+7 downto 2*32+0) <= channel_empty_i(63 downto 32);
--------------------------------------------------------------------------------
--- Register 0x83
--------------------------------------------------------------------------------
- TDC_DEBUG(3*32+31 downto 3*32+0) <= "00000" & TRG_WIN_POST & "00000" & TRG_WIN_PRE;
--------------------------------------------------------------------------------
--- Register 0x84
--------------------------------------------------------------------------------
- TDC_DEBUG(4*32+23 downto 4*32+0) <= trig_number;
--------------------------------------------------------------------------------
--- Register 0x85
--------------------------------------------------------------------------------
- TDC_DEBUG(5*32+23 downto 5*32+0) <= valid_tmg_trig_number;
--------------------------------------------------------------------------------
--- Register 0x86
--------------------------------------------------------------------------------
- TDC_DEBUG(6*32+23 downto 6*32+0) <= valid_NOtmg_trig_number;
--------------------------------------------------------------------------------
--- Register 0x87
--------------------------------------------------------------------------------
- TDC_DEBUG(7*32+23 downto 7*32+0) <= invalid_trig_number;
--------------------------------------------------------------------------------
--- Register 0x88
--------------------------------------------------------------------------------
- TDC_DEBUG(8*32+23 downto 8*32+0) <= multi_tmg_trig_number;
--------------------------------------------------------------------------------
--- Register 0x89
--------------------------------------------------------------------------------
- TDC_DEBUG(9*32+23 downto 9*32+0) <= spurious_trig_number;
--------------------------------------------------------------------------------
--- Register 0x8a
--------------------------------------------------------------------------------
- TDC_DEBUG(10*32+23 downto 10*32+0) <= wrong_readout_number;
--------------------------------------------------------------------------------
--- Register 0x8b
--------------------------------------------------------------------------------
- TDC_DEBUG(11*32+23 downto 11*32+0) <= spike_number;
--------------------------------------------------------------------------------
--- Register 0x8c
--------------------------------------------------------------------------------
- TDC_DEBUG(12*32+23 downto 12*32+0) <= idle_time;
--------------------------------------------------------------------------------
--- Register 0x8d
--------------------------------------------------------------------------------
- TDC_DEBUG(13*32+23 downto 13*32+0) <= wait_time;
--------------------------------------------------------------------------------
--- Register 0x8e
--------------------------------------------------------------------------------
- TDC_DEBUG(14*32+23 downto 14*32+0) <= total_empty_channel;
--------------------------------------------------------------------------------
--- Register 0x8f
--------------------------------------------------------------------------------
- TDC_DEBUG(15*32+23 downto 15*32+0) <= channel_lost_hits(3);
--------------------------------------------------------------------------------
--- Register 0x90
--------------------------------------------------------------------------------
- TDC_DEBUG(16*32+23 downto 16*32+0) <= channel_measurement(3);
--------------------------------------------------------------------------------
--- Register 0x91
--------------------------------------------------------------------------------
- TDC_DEBUG(17*32+23 downto 17*32+0) <= channel_encoder_start_number(3);
--------------------------------------------------------------------------------
--- Register 0x92
--------------------------------------------------------------------------------
- TDC_DEBUG(18*32+23 downto 18*32+0) <= channel_lost_hits(2);
--------------------------------------------------------------------------------
--- Register 0x93
--------------------------------------------------------------------------------
- TDC_DEBUG(19*32+23 downto 19*32+0) <= channel_measurement(2);
--------------------------------------------------------------------------------
--- Register 0x94
--------------------------------------------------------------------------------
- TDC_DEBUG(20*32+23 downto 20*32+0) <= channel_encoder_start_number(2);
-
-end TDC;
+++ /dev/null
---synchronizes a single bit to a different clock domain
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_arith.all;
-use ieee.std_logic_unsigned.all;
-
-entity bit_sync is
- generic(
- DEPTH : integer := 3
- );
- port(
- RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register
- CLK0 : in std_logic; --clock for first FF
- CLK1 : in std_logic; --Clock for other FF
- D_IN : in std_logic; --Data input
- D_OUT : out std_logic --Data output
- );
-end entity;
-
-architecture behavioral of bit_sync is
-
- signal sync_q : std_logic_vector(DEPTH downto 0);
-
- attribute syn_preserve : boolean;
- attribute syn_keep : boolean;
- attribute syn_keep of sync_q : signal is true;
- attribute syn_preserve of sync_q : signal is true;
-
-
-begin
- sync_q(0) <= D_IN;
- D_OUT <= sync_q(DEPTH);
-
- process(CLK0)
- begin
- if rising_edge(CLK0) then
- if RESET = '1' then
- sync_q(1) <= '0';
- else
- sync_q(1) <= sync_q(0);
- end if;
- end if;
- end process;
-
- gen_others : if DEPTH > 1 generate
- gen_flipflops : for i in 2 to DEPTH generate
- process(CLK1)
- begin
- if rising_edge(CLK1) then
- if RESET = '1' then
- sync_q(i) <= '0';
- else
- sync_q(i) <= sync_q(i-1);
- end if;
- end if;
- end process;
- end generate;
- end generate;
-
-end architecture;
+++ /dev/null
--------------------------------------------------------------------------------
--- Title : Reset Generator
--- Project :
--------------------------------------------------------------------------------
--- File : reset_generator.vhd
--- Author : Cahit Ugur
--- Company :
--- Created : 2011-11-09
--- Last update: 2011-11-28
--- Platform :
--- Standard : VHDL'87
--------------------------------------------------------------------------------
--- Description: Generates a synchronous reset signal.
--------------------------------------------------------------------------------
--- Copyright (c) 2011
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 2011-11-09 1.0 ugur Created
--------------------------------------------------------------------------------
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.all;
-use IEEE.STD_LOGIC_ARITH.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
-use IEEE.NUMERIC_STD.all;
-use STD.TEXTIO.all;
-use IEEE.STD_LOGIC_TEXTIO.all;
-
-entity Reset_Generator is
-
- generic (
- RESET_SIGNAL_WIDTH : std_logic_vector(3 downto 0) := x"F"); -- The length of the reset signal
-
- port (
- CLK_IN : in std_logic; -- System clock, that the reset will be synchronous with.
- RESET_OUT : out std_logic); -- Synchronous reset signal
-
-end Reset_Generator;
-
-architecture Behavioral of Reset_Generator is
-
- signal reset_cnt : std_logic_vector(3 downto 0) := x"0"; -- initial value of the reset counter
- signal reset_i : std_logic := '0';
-
-begin -- Behavioral
-
- RESET_PROC : process (CLK_IN)
- begin -- process RESET_PROC
- if (rising_edge(CLK_IN)) then -- rising clock edge
- reset_cnt <= reset_cnt + 1;
- reset_i <= '1';
- if reset_cnt = RESET_SIGNAL_WIDTH then
- reset_cnt <= RESET_SIGNAL_WIDTH;
- reset_i <= '0';
- end if;
- end if;
- end process RESET_PROC;
-
- RESET_OUT <= reset_i when rising_edge(CLK_IN);
-
-end Behavioral;
+++ /dev/null
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb3_components.all;
-use work.version.all;
-
-
-entity trb3_periph is
- port(
- --Clocks
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- --Trigger
- TRIGGER_LEFT : in std_logic; --left side trigger input from fan-out
- TRIGGER_RIGHT : in std_logic; --right side trigger input from fan-out
- --Serdes
- CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 1/(1357), off, 125 MHz possible
- CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 2/(1357), 200 MHz, only in case of problems
- SERDES_INT_TX : out std_logic_vector(3 downto 0);
- SERDES_INT_RX : in std_logic_vector(3 downto 0);
- SERDES_ADDON_TX : out std_logic_vector(11 downto 0);
- SERDES_ADDON_RX : in std_logic_vector(11 downto 0);
- --Inter-FPGA Communication
- FPGA5_COMM : inout std_logic_vector(11 downto 0);
- --Bit 0/1 input, serial link RX active
- --Bit 2/3 output, serial link TX active
- --Connection to ADA AddOn
- SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only
- INP : in std_logic_vector(63 downto 0);
- OUT_L_SCK : out std_logic;
- OUT_L_SDO : out std_logic;
- OUT_L_CS : out std_logic;
- IN_L_SDI : out std_logic;
- OUT_H_SCK : out std_logic;
- OUT_H_SDO : out std_logic;
- OUT_H_CS : out std_logic;
- IN_H_SDI : out std_logic;
- --Flash ROM & Reboot
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_DIN : out std_logic;
- FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
- --Misc
- TEMPSENS : inout std_logic; --Temperature Sensor
- CODE_LINE : in std_logic_vector(1 downto 0);
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
- --Test Connectors
- TEST_LINE : out std_logic_vector(15 downto 0)
- );
- attribute syn_useioff : boolean;
- --no IO-FF for LEDs relaxes timing constraints
- attribute syn_useioff of LED_GREEN : signal is false;
- attribute syn_useioff of LED_ORANGE : signal is false;
- attribute syn_useioff of LED_RED : signal is false;
- attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of TEMPSENS : signal is false;
- attribute syn_useioff of PROGRAMN : signal is false;
- attribute syn_useioff of CODE_LINE : signal is false;
- attribute syn_useioff of TRIGGER_LEFT : signal is false;
- attribute syn_useioff of TRIGGER_RIGHT : signal is false;
- --important signals
- attribute syn_useioff of FLASH_CLK : signal is true;
- attribute syn_useioff of FLASH_CS : signal is true;
- attribute syn_useioff of FLASH_DIN : signal is true;
- attribute syn_useioff of FLASH_DOUT : signal is true;
- attribute syn_useioff of FPGA5_COMM : signal is true;
- attribute syn_useioff of TEST_LINE : signal is true;
- attribute syn_useioff of INP : signal is false;
- attribute syn_useioff of SPARE_LINE : signal is true;
- attribute syn_useioff of OUT_L_SCK : signal is true;
- attribute syn_useioff of OUT_L_SDO : signal is true;
- attribute syn_useioff of OUT_L_CS : signal is true;
- attribute syn_useioff of IN_L_SDI : signal is true;
- attribute syn_useioff of OUT_H_SCK : signal is true;
- attribute syn_useioff of OUT_H_SDO : signal is true;
- attribute syn_useioff of OUT_H_CS : signal is true;
- attribute syn_useioff of IN_H_SDI : signal is true;
-end entity;
-
-
-architecture trb3_periph_arch of trb3_periph is
- --Constants
- constant REGIO_NUM_STAT_REGS : integer := 5;
- constant REGIO_NUM_CTRL_REGS : integer := 2;
-
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
-
- --Clock / Reset
- signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal GSR_N : std_logic;
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
-
- --Media Interface
- signal med_stat_op : std_logic_vector (1*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (1*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (1*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (1*64-1 downto 0);
- signal med_data_out : std_logic_vector (1*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (1*3-1 downto 0);
- signal med_dataready_out : std_logic;
- signal med_read_out : std_logic;
- signal med_data_in : std_logic_vector (1*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (1*3-1 downto 0);
- signal med_dataready_in : std_logic;
- signal med_read_in : std_logic;
-
- --LVL1 channel
- signal timing_trg_received_i : std_logic;
- signal trg_data_valid_i : std_logic;
- signal trg_timing_valid_i : std_logic;
- signal trg_notiming_valid_i : std_logic;
- signal trg_invalid_i : std_logic;
- signal trg_type_i : std_logic_vector(3 downto 0);
- signal trg_number_i : std_logic_vector(15 downto 0);
- signal trg_code_i : std_logic_vector(7 downto 0);
- signal trg_information_i : std_logic_vector(23 downto 0);
- signal trg_int_number_i : std_logic_vector(15 downto 0);
- signal trg_multiple_trg_i : std_logic;
- signal trg_timeout_detected_i : std_logic;
- signal trg_spurious_trg_i : std_logic;
- signal trg_missing_tmg_trg_i : std_logic;
- signal trg_spike_detected_i : std_logic;
-
- --Data channel
- signal fee_trg_release_i : std_logic;
- signal fee_trg_statusbits_i : std_logic_vector(31 downto 0);
- signal fee_data_i : std_logic_vector(31 downto 0);
- signal fee_data_write_i : std_logic;
- signal fee_data_finished_i : std_logic;
- signal fee_almost_full_i : std_logic;
-
- --Slow Control channel
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
- --RegIO
- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-
- --Flash
- signal spictrl_read_en : std_logic;
- signal spictrl_write_en : std_logic;
- signal spictrl_data_in : std_logic_vector(31 downto 0);
- signal spictrl_addr : std_logic;
- signal spictrl_data_out : std_logic_vector(31 downto 0);
- signal spictrl_ack : std_logic;
- signal spictrl_busy : std_logic;
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(5 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_ack : std_logic;
-
- signal spi_bram_addr : std_logic_vector(7 downto 0);
- signal spi_bram_wr_d : std_logic_vector(7 downto 0);
- signal spi_bram_rd_d : std_logic_vector(7 downto 0);
- signal spi_bram_we : std_logic;
-
-
- --FPGA Test
- signal time_counter : unsigned(31 downto 0);
-
- --TDC component
- component TDC
- generic (
- CHANNEL_NUMBER : integer range 0 to 64;
- STATUS_REG_NR : integer range 0 to 6;
- CONTROL_REG_NR : integer range 0 to 6);
- port (
- RESET : in std_logic;
- CLK_TDC : in std_logic;
- CLK_READOUT : in std_logic;
- REFERENCE_TIME : in std_logic;
- HIT_IN : in std_logic_vector(CHANNEL_NUMBER-1 downto 1);
- TRG_WIN_PRE : in std_logic_vector(10 downto 0);
- TRG_WIN_POST : in std_logic_vector(10 downto 0);
- TRG_DATA_VALID_IN : in std_logic;
- VALID_TIMING_TRG_IN : in std_logic;
- VALID_NOTIMING_TRG_IN : in std_logic;
- INVALID_TRG_IN : in std_logic;
- TMGTRG_TIMEOUT_IN : in std_logic;
- SPIKE_DETECTED_IN : in std_logic;
- MULTI_TMG_TRG_IN : in std_logic;
- SPURIOUS_TRG_IN : in std_logic;
- TRG_NUMBER_IN : in std_logic_vector(15 downto 0);
- TRG_CODE_IN : in std_logic_vector(7 downto 0);
- TRG_INFORMATION_IN : in std_logic_vector(23 downto 0);
- TRG_TYPE_IN : in std_logic_vector(3 downto 0);
- TRG_RELEASE_OUT : out std_logic;
- TRG_STATUSBIT_OUT : out std_logic_vector(31 downto 0);
- DATA_OUT : out std_logic_vector(31 downto 0);
- DATA_WRITE_OUT : out std_logic;
- DATA_FINISHED_OUT : out std_logic;
- TDC_DEBUG : out std_logic_vector(32*2**STATUS_REG_NR-1 downto 0);
- LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0);
- CONTROL_REG_IN : in std_logic_vector(32*2**CONTROL_REG_NR-1 downto 0));
- end component;
-
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
- GSR_N <= pll_lock;
-
- THE_RESET_HANDLER : trb_net_reset_handler
- generic map(
- RESET_DELAY => x"FEEE"
- )
- port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
- RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => open
- );
-
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
- THE_MAIN_PLL : pll_in200_out100
- port map(
- CLK => CLK_GPLL_RIGHT,
- CLKOP => clk_100_i,
- CLKOK => clk_200_i,
- LOCK => pll_lock
- );
-
-
----------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
----------------------------------------------------------------------------
- THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
- generic map(
- SERDES_NUM => 1, --number of serdes in quad
- EXT_CLOCK => c_NO, --use internal clock
- USE_200_MHZ => c_YES --run on 200 MHz clock
- )
- port map(
- CLK => clk_200_i,
- SYSCLK => clk_100_i,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
- --Internal Connection
- MED_DATA_IN => med_data_out,
- MED_PACKET_NUM_IN => med_packet_num_out,
- MED_DATAREADY_IN => med_dataready_out,
- MED_READ_OUT => med_read_in,
- MED_DATA_OUT => med_data_in,
- MED_PACKET_NUM_OUT => med_packet_num_in,
- MED_DATAREADY_OUT => med_dataready_in,
- MED_READ_IN => med_read_out,
- REFCLK2CORE_OUT => open,
- --SFP Connection
- SD_RXD_P_IN => SERDES_INT_RX(2),
- SD_RXD_N_IN => SERDES_INT_RX(3),
- SD_TXD_P_OUT => SERDES_INT_TX(2),
- SD_TXD_N_OUT => SERDES_INT_TX(3),
- SD_REFCLK_P_IN => open,
- SD_REFCLK_N_IN => open,
- SD_PRSNT_N_IN => FPGA5_COMM(0),
- SD_LOS_IN => FPGA5_COMM(0),
- SD_TXDIS_OUT => FPGA5_COMM(2),
- -- Status and control port
- STAT_OP => med_stat_op,
- CTRL_OP => med_ctrl_op,
- STAT_DEBUG => med_stat_debug,
- CTRL_DEBUG => (others => '0')
- );
-
----------------------------------------------------------------------------
--- Endpoint
----------------------------------------------------------------------------
- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler
- generic map(
- REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg
- REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg
- ADDRESS_MASK => x"FFFF",
- BROADCAST_BITMASK => x"FF",
- BROADCAST_SPECIAL_ADDR => x"45",
- REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
- REGIO_HARDWARE_VERSION => x"91000001",
- REGIO_INIT_ADDRESS => x"f300",
- REGIO_USE_VAR_ENDPOINT_ID => c_YES,
- CLOCK_FREQUENCY => 125,
- TIMING_TRIGGER_RAW => c_YES,
- --Configure data handler
- DATA_INTERFACE_NUMBER => 1,
- DATA_BUFFER_DEPTH => 13, --13
- DATA_BUFFER_WIDTH => 32,
- DATA_BUFFER_FULL_THRESH => 2**13-800, --2**13-1024
- TRG_RELEASE_AFTER_DATA => c_YES,
- HEADER_BUFFER_DEPTH => 9,
- HEADER_BUFFER_FULL_THRESH => 2**9-16
- )
- port map(
- CLK => clk_100_i,
- RESET => reset_i,
- CLK_EN => '1',
- MED_DATAREADY_OUT => med_dataready_out, -- open, --
- MED_DATA_OUT => med_data_out, -- open, --
- MED_PACKET_NUM_OUT => med_packet_num_out, -- open, --
- MED_READ_IN => med_read_in,
- MED_DATAREADY_IN => med_dataready_in,
- MED_DATA_IN => med_data_in,
- MED_PACKET_NUM_IN => med_packet_num_in,
- MED_READ_OUT => med_read_out, -- open, --
- MED_STAT_OP_IN => med_stat_op,
- MED_CTRL_OP_OUT => med_ctrl_op,
-
- --Timing trigger in
- TRG_TIMING_TRG_RECEIVED_IN => timing_trg_received_i,
- --LVL1 trigger to FEE
- LVL1_TRG_DATA_VALID_OUT => trg_data_valid_i,
- LVL1_VALID_TIMING_TRG_OUT => trg_timing_valid_i,
- LVL1_VALID_NOTIMING_TRG_OUT => trg_notiming_valid_i,
- LVL1_INVALID_TRG_OUT => trg_invalid_i,
-
- LVL1_TRG_TYPE_OUT => trg_type_i,
- LVL1_TRG_NUMBER_OUT => trg_number_i,
- LVL1_TRG_CODE_OUT => trg_code_i,
- LVL1_TRG_INFORMATION_OUT => trg_information_i,
- LVL1_INT_TRG_NUMBER_OUT => trg_int_number_i,
-
- --Information about trigger handler errors
- TRG_MULTIPLE_TRG_OUT => trg_multiple_trg_i,
- TRG_TIMEOUT_DETECTED_OUT => trg_timeout_detected_i,
- TRG_SPURIOUS_TRG_OUT => trg_spurious_trg_i,
- TRG_MISSING_TMG_TRG_OUT => trg_missing_tmg_trg_i,
- TRG_SPIKE_DETECTED_OUT => trg_spike_detected_i,
-
- --Response from FEE
- FEE_TRG_RELEASE_IN(0) => fee_trg_release_i,
- FEE_TRG_STATUSBITS_IN => fee_trg_statusbits_i,
- FEE_DATA_IN => fee_data_i,
- FEE_DATA_WRITE_IN(0) => fee_data_write_i,
- FEE_DATA_FINISHED_IN(0) => fee_data_finished_i,
- FEE_DATA_ALMOST_FULL_OUT(0) => fee_almost_full_i,
-
- -- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00
- REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20
- REGIO_COMMON_STAT_STROBE_OUT => common_stat_reg_strobe,
- REGIO_COMMON_CTRL_STROBE_OUT => common_ctrl_reg_strobe,
- REGIO_STAT_REG_IN => stat_reg, --start 0x80
- REGIO_CTRL_REG_OUT => ctrl_reg, --start 0xc0
- REGIO_STAT_STROBE_OUT => stat_reg_strobe,
- REGIO_CTRL_STROBE_OUT => ctrl_reg_strobe,
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
-
- BUS_ADDR_OUT => regio_addr_out,
- BUS_READ_ENABLE_OUT => regio_read_enable_out,
- BUS_WRITE_ENABLE_OUT => regio_write_enable_out,
- BUS_DATA_OUT => regio_data_out,
- BUS_DATA_IN => regio_data_in,
- BUS_DATAREADY_IN => regio_dataready_in,
- BUS_NO_MORE_DATA_IN => regio_no_more_data_in,
- BUS_WRITE_ACK_IN => regio_write_ack_in,
- BUS_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- BUS_TIMEOUT_OUT => regio_timeout_out,
- ONEWIRE_INOUT => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
-
- TIME_GLOBAL_OUT => global_time,
- TIME_LOCAL_OUT => local_time,
- TIME_SINCE_LAST_TRG_OUT => time_since_last_trg,
- TIME_TICKS_OUT => timer_ticks,
-
- STAT_DEBUG_IPU => open,
- STAT_DEBUG_1 => open,
- STAT_DEBUG_2 => open,
- STAT_DEBUG_DATA_HANDLER_OUT => open,
- STAT_DEBUG_IPU_HANDLER_OUT => open,
- STAT_TRIGGER_OUT => open,
- CTRL_MPLEX => (others => '0'),
- IOBUF_CTRL_GEN => (others => '0'),
- STAT_ONEWIRE => open,
- STAT_ADDR_DEBUG => open,
- DEBUG_LVL1_HANDLER_OUT => open
- );
-
- timing_trg_received_i <= TRIGGER_LEFT;
-
----------------------------------------------------------------------------
--- AddOn
----------------------------------------------------------------------------
- OUT_L_SCK <= '0';
- OUT_L_SDO <= '0';
- OUT_L_CS <= '0';
- OUT_H_SCK <= '0';
- OUT_H_SDO <= '0';
- OUT_H_CS <= '0';
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 2,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", others => x"0000"),
- PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0)
- )
- port map(
- CLK => clk_100_i,
- RESET => reset_i,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- --Bus Handler (SPI CTRL)
- BUS_READ_ENABLE_OUT(0) => spictrl_read_en,
- BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en,
- BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in,
- BUS_ADDR_OUT(0*16) => spictrl_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
- BUS_TIMEOUT_OUT(0) => open,
- BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out,
- BUS_DATAREADY_IN(0) => spictrl_ack,
- BUS_WRITE_ACK_IN(0) => spictrl_ack,
- BUS_NO_MORE_DATA_IN(0) => spictrl_busy,
- BUS_UNKNOWN_ADDR_IN(0) => '0',
- --Bus Handler (SPI Memory)
- BUS_READ_ENABLE_OUT(1) => spimem_read_en,
- BUS_WRITE_ENABLE_OUT(1) => spimem_write_en,
- BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in,
- BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out,
- BUS_DATAREADY_IN(1) => spimem_ack,
- BUS_WRITE_ACK_IN(1) => spimem_ack,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(1) => '0',
-
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
- THE_SPI_MASTER : spi_master
- port map(
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- -- Slave bus
- BUS_READ_IN => spictrl_read_en,
- BUS_WRITE_IN => spictrl_write_en,
- BUS_BUSY_OUT => spictrl_busy,
- BUS_ACK_OUT => spictrl_ack,
- BUS_ADDR_IN(0) => spictrl_addr,
- BUS_DATA_IN => spictrl_data_in,
- BUS_DATA_OUT => spictrl_data_out,
- -- SPI connections
- SPI_CS_OUT => FLASH_CS,
- SPI_SDI_IN => FLASH_DOUT,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SCK_OUT => FLASH_CLK,
- -- BRAM for read/write data
- BRAM_A_OUT => spi_bram_addr,
- BRAM_WR_D_IN => spi_bram_wr_d,
- BRAM_RD_D_OUT => spi_bram_rd_d,
- BRAM_WE_OUT => spi_bram_we,
- -- Status lines
- STAT => open
- );
-
--- data memory for SPI accesses
- THE_SPI_MEMORY : spi_databus_memory
- port map(
- CLK_IN => clk_100_i,
- RESET_IN => reset_i,
- -- Slave bus
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_ACK_OUT => spimem_ack,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
- -- state machine connections
- BRAM_ADDR_IN => spi_bram_addr,
- BRAM_WR_D_OUT => spi_bram_wr_d,
- BRAM_RD_D_IN => spi_bram_rd_d,
- BRAM_WE_IN => spi_bram_we,
- -- Status lines
- STAT => open
- );
-
----------------------------------------------------------------------------
--- Reboot FPGA
----------------------------------------------------------------------------
- THE_FPGA_REBOOT : fpga_reboot
- port map(
- CLK => clk_100_i,
- RESET => reset_i,
- DO_REBOOT => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN
- );
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
- LED_GREEN <= not med_stat_op(9);
- LED_ORANGE <= not med_stat_op(10);
- LED_RED <= not INP(0);
- LED_YELLOW <= not med_stat_op(11);
-
----------------------------------------------------------------------------
--- Test Connector
----------------------------------------------------------------------------
-
--- TEST_LINE(15 downto 0) <= time_counter(15 downto 0);
- ---------------------------------------------------------------------------
- -- Test Circuits
- ---------------------------------------------------------------------------
- process
- begin
- wait until rising_edge(clk_100_i);
- time_counter <= time_counter + 1;
- end process;
-
- -------------------------------------------------------------------------------
- -- TDC
- -------------------------------------------------------------------------------
-
- THE_TDC : TDC
- generic map (
- CHANNEL_NUMBER => 8, -- Number of TDC channels
- STATUS_REG_NR => REGIO_NUM_STAT_REGS,
- CONTROL_REG_NR => REGIO_NUM_CTRL_REGS)
- port map (
- RESET => reset_i,
- CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement
- CLK_READOUT => clk_100_i, -- Clock for the readout
- REFERENCE_TIME => timing_trg_received_i, -- Reference time input
- HIT_IN => INP(6 downto 0), -- Channel start signals
- TRG_WIN_PRE => ctrl_reg(42 downto 32), --"00000000000", -- Pre-Trigger window width
- TRG_WIN_POST => ctrl_reg(58 downto 48), --"00001100100", -- Post-Trigger window width
- --
- -- Trigger signals from handler
- TRG_DATA_VALID_IN => trg_data_valid_i, -- trig data valid signal from trbnet
- VALID_TIMING_TRG_IN => trg_timing_valid_i, -- valid timing trigger signal from trbnet
- VALID_NOTIMING_TRG_IN => trg_notiming_valid_i, -- valid notiming signal from trbnet
- INVALID_TRG_IN => trg_invalid_i, -- invalid trigger signal from trbnet
- TMGTRG_TIMEOUT_IN => trg_timeout_detected_i, -- timing trigger timeout signal from trbnet
- SPIKE_DETECTED_IN => trg_spike_detected_i,
- MULTI_TMG_TRG_IN => trg_multiple_trg_i,
- SPURIOUS_TRG_IN => trg_spurious_trg_i,
- --
- TRG_NUMBER_IN => trg_number_i, -- LVL1 trigger information package
- TRG_CODE_IN => trg_code_i, --
- TRG_INFORMATION_IN => trg_information_i, --
- TRG_TYPE_IN => trg_type_i, -- LVL1 trigger information package
- --
- --Response to handler
- TRG_RELEASE_OUT => fee_trg_release_i, -- trigger release signal
- TRG_STATUSBIT_OUT => fee_trg_statusbits_i, -- status information of the tdc
- DATA_OUT => fee_data_i, -- tdc data
- DATA_WRITE_OUT => fee_data_write_i, -- data valid signal
- DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal
- --
- TDC_DEBUG => stat_reg,
- LOGIC_ANALYSER_OUT => TEST_LINE,
- CONTROL_REG_IN => ctrl_reg);
-
-end architecture;
+++ /dev/null
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_ARITH.ALL;
-use IEEE.STD_LOGIC_UNSIGNED.ALL;
-
-entity up_counter is
-
- generic (
- NUMBER_OF_BITS : positive);
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- COUNT_OUT : out std_logic_vector(NUMBER_OF_BITS-1 downto 0);
- UP_IN : in std_logic);
-
-end up_counter;
-
-architecture up_counter of up_counter is
-
-signal counter: std_logic_vector (NUMBER_OF_BITS-1 downto 0);
-
-begin
-
- COUNTER_PROC : process (CLK, RESET)
- begin
- if rising_edge(CLK) then
- if RESET = '1' then
- counter <= (others => '0');
- elsif UP_IN = '1' then
- counter <= counter + 1;
- else
- counter <= counter;
- end if;
- end if;
- end process COUNTER_PROC;
-
- COUNT_OUT <= counter;
-
-end up_counter;
jspc29 / trb3.git / commitdiff