]> jspc29.x-matter.uni-frankfurt.de Git - trbnet.git/commitdiff
*** empty log message ***
authorhadeshyp <hadeshyp>
Mon, 8 Jun 2009 16:35:11 +0000 (16:35 +0000)
committerhadeshyp <hadeshyp>
Mon, 8 Jun 2009 16:35:11 +0000 (16:35 +0000)
media_interfaces/trb_net16_med_ecp_sfp.vhd
media_interfaces/trb_net16_med_ecp_sfp_4.vhd
trb_net16_regIO.vhd
trb_net_std.vhd

index 1115a193122bfec1865970239cc10983a20b7519..0177f2197da43dfe247fc178ae1d0a8d6f4f7a8b 100644 (file)
@@ -652,7 +652,7 @@ port map( read_clock_in    => clock,
       empty_out      => fifo_rx_empty
     );
 
-fifo_rx_reset <= RESET;
+fifo_rx_reset <= RESET or not rx_allow_q;
 fifo_rx_rd_en <= '1';
 
 -- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
@@ -725,7 +725,7 @@ port map( read_clock_in    => ff_txhalfclk,
       empty_out      => fifo_tx_empty
     );
 
-fifo_tx_reset <= reset;
+fifo_tx_reset <= reset or not tx_allow_q;
 fifo_tx_din   <= med_packet_num_in(2) & med_packet_num_in(0)& med_data_in;
 fifo_tx_wr_en <= med_dataready_in and tx_allow_q;
 fifo_tx_rd_en <= tx_allow;
index bf4261d6d6bbb18275bd10e06413e1839b389277..69b746270802f70d3abbf92ec9763145b4479e6f 100644 (file)
@@ -700,7 +700,7 @@ begin
         empty_out       => fifo_rx_empty(i)
         );
 
-    fifo_rx_reset(i) <= RESET;
+    fifo_rx_reset(i) <= RESET or not rx_allow_q(i);
     fifo_rx_rd_en(i) <= '1';
 
   -- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
@@ -777,7 +777,7 @@ begin
         empty_out       => fifo_tx_empty(i)
         );
 
-    fifo_tx_reset(i) <= reset;
+    fifo_tx_reset(i) <= reset or not tx_allow_q(i);
     fifo_tx_din(i*18+17 downto i*18)   <= med_packet_num_in(i*3+2) & med_packet_num_in(i*3+0)& med_data_in(i*16+15 downto i*16);
     fifo_tx_wr_en(i) <= med_dataready_in(i) and tx_allow(i);
     fifo_tx_rd_en(i) <= tx_allow_q(i);
index 1fc04e4ca4a3cee6fa0206bdc7d55687626fe9f3..8211a080cdd71737ab43bb694d81194d4ee2dab6 100644 (file)
@@ -228,6 +228,7 @@ architecture trb_net16_regIO_arch of trb_net16_regIO is
   signal time_since_last_trg_i  : std_logic_vector(31 downto 0) := (others => '0');
   signal local_time_i  : std_logic_vector(7 downto 0) := (others => '0');
   signal us_tick_i     : std_logic := '0';
+  signal global_time_write, next_global_time_write : std_logic;
 
 
 begin
@@ -328,6 +329,7 @@ begin
       next_addr_counter_enable <= addr_counter_enable;
       next_API_READ_OUT <= '1';
       next_dat_data_counter <= dat_data_counter;
+      next_global_time_write <= '0';
 
       case current_state is
         when IDLE =>
@@ -408,11 +410,8 @@ begin
                 next_state <= SEND_REPLY_SHORT_TRANSFER;
                 next_dont_understand <= '1';
               end if;
-            elsif API_DATA_IN(7 downto 5) = "001" or API_DATA_IN(7 downto 6) = "11" then   --ctrl address
-               next_state <= REG_WRITE;    --ctrl register
             else
-              next_state <= SEND_REPLY_SHORT_TRANSFER;
-              next_dont_understand <= '1';
+               next_state <= REG_WRITE;    --ctrl register
             end if;
           end if;
 
@@ -434,11 +433,20 @@ begin
               when c_F2 =>
                 next_Reg_low <= API_DATA_IN;
                 if or_all(address(15 downto 8)) = '0' then
-                  if address(7 downto 6) = "11" then
-                    next_REGISTERS_OUT_write_enable <= reg_enable_pattern(2**NUM_CTRL_REGS-1 downto 0);
-                  else
-                    next_COMMON_REGISTERS_OUT_write_enable <= reg_enable_pattern(std_COMCTRLREG-1 downto 0);
-                  end if;
+                  case address(7 downto 4) is
+                    when x"C" | x"D" | x"E" | x"F" =>
+                      next_REGISTERS_OUT_write_enable <= reg_enable_pattern(2**NUM_CTRL_REGS-1 downto 0);
+                    when x"2" | x"3" =>
+                      next_COMMON_REGISTERS_OUT_write_enable <= reg_enable_pattern(std_COMCTRLREG-1 downto 0);
+                    when x"5" =>
+                      if address(3 downto 0) = x"0" then
+                        next_global_time_write <= '1';
+                      else
+                        next_unknown <= '1';
+                      end if;
+                    when others =>
+                      next_unknown <= '1';
+                  end case;
                   next_state   <= SEND_REPLY_SHORT_TRANSFER; --REG_READ;
                 else
                   next_DAT_WRITE_ENABLE_OUT <= '1';
@@ -701,6 +709,7 @@ begin
           unknown <= '0';
           nomoredata <= '0';
           buf_API_READ_OUT <= '0';
+          global_time_write <= '0';
         else
           current_state <= next_state;
           buf_API_SEND_OUT <= next_API_SEND_OUT;
@@ -722,6 +731,7 @@ begin
           timeout <= next_timeout;
           unknown <= next_unknown;
           nomoredata <= next_nomoredata;
+          global_time_write <= next_global_time_write;
           dat_data_counter <= next_dat_data_counter;
         end if;
       end if;
@@ -900,7 +910,7 @@ begin
       if rising_edge(CLK) then
 --         global_time(15 downto 0) <= next_global_time(15 downto 0);
 --         global_time_overflow <= '0';
-        if COMMON_REGISTERS_OUT_write_enable(2) = '1' then
+        if global_time_write = '1'  then
           global_time_i <= saved_Reg_high & saved_Reg_low;
         elsif us_tick_i = '1' then
           global_time_i <= global_time_i + 1;
index 069f27d95bbdb8e6c29cff1da4ca103e519ad010..0bddca8b74242fdca07bfa1b9789842adb8f7449 100644 (file)
@@ -101,7 +101,7 @@ package trb_net_std is
 --common registers
   --maximum: 4, because of regio implementation
   constant std_COMSTATREG  : integer := 2;
-  constant std_COMCTRLREG  : integer := 3;
+  constant std_COMCTRLREG  : integer := 2;
     --needed address width for common registers
   constant std_COMneededwidth : integer := 2;
   constant c_REGIO_ADDRESS_WIDTH : integer := 16;