signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal ctrlbus_tx, bustools_tx, busgbeip_tx, busgbereg_tx, bus_master_in : CTRLBUS_TX;
- signal ctrlbus_rx, bustools_rx, busgbeip_rx, busgbereg_rx, bus_master_out : CTRLBUS_RX;
+ signal ctrlbus_tx, bustools_tx, bus_master_in : CTRLBUS_TX;
+ signal ctrlbus_rx, bustools_rx, bus_master_out : CTRLBUS_RX;
signal bus_master_active : std_logic;
signal timer : TIMERS;
signal tick_ms_int : std_logic;
signal tick_us_int : std_logic;
-
+
+ signal reboot_int : std_logic;
+
begin
---------------------------------------------------------------------------
-- Status
PCS_AN_READY_OUT => open,
LINK_ACTIVE_OUT => link_active,
- TICK_MS_IN => tick_us_int,
+ TICK_MS_IN => tick_ms_int,
-- Debug
STATUS_OUT => status(7 downto 0),
DEBUG_OUT => open --debug(63 downto 0)
CLK => clk_sys,
RESET => reset_i,
--
--- FIFO_FULL_IN(0 downto 0) => dl_tx_fifofull(0 downto 0),
+-- FIFO_FULL_IN(0 downto 0) => dl_tx_fifofull(0 downto 0), -- not needed, only SCTRL at the moment
FIFO_FULL_OUT => ul_rx_fifofull,
FRAME_AVAIL_IN => ul_rx_frame_avail,
FRAME_REQ_OUT => ul_rx_frame_req,
---------------------------------------------------------------------------
GBE: entity work.gbe_wrapper_fifo
generic map(
- LINK_HAS_READOUT => '0',
LINK_HAS_SLOWCTRL => '1',
LINK_HAS_DHCP => '1',
LINK_HAS_ARP => '1',
CLK_125_IN => clk_sys,
RESET => reset_i,
GSR_N => reset_n_i,
- -- Trigger
- TRIGGER_IN => '0',
-- we connect to FIFO interface directly
-- FIFO interface TX (transmit frames)
FIFO_DATA_OUT => dl_rx_data(0)(8 downto 0),
GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num,
GSC_REPLY_READ_OUT => gsc_reply_read,
GSC_BUSY_IN => gsc_busy,
- -- readout
- BUS_IP_RX => busgbeip_rx,
- BUS_IP_TX => busgbeip_tx,
- BUS_REG_RX => busgbereg_rx,
- BUS_REG_TX => busgbereg_tx,
-- Forwarder
FWD_DST_MAC_IN => fwd_mac_int,
FWD_DST_IP_IN => fwd_ip_int,
-------------------------------------------------------------------------------
THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
generic map(
- PORT_NUMBER => 3,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"8100", 2 => x"8300", others => x"0000"),
- PORT_ADDR_MASK => (0 => 12, 1 => 8, 2 => 8, others => 0),
+ PORT_NUMBER => 1,
+ PORT_ADDRESSES => (0 => x"d000", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 12, others => 0),
PORT_MASK_ENABLE => 1
)
port map(
REGIO_RX => ctrlbus_rx,
REGIO_TX => ctrlbus_tx,
BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED
- BUS_RX(1) => busgbeip_rx,
- BUS_RX(2) => busgbereg_rx,
BUS_TX(0) => bustools_tx,
- BUS_TX(1) => busgbeip_tx,
- BUS_TX(2) => busgbereg_tx,
STAT_DEBUG => open
);
FLASH_IN => flash_miso_i,
FLASH_OUT => flash_mosi_i,
PROGRAMN => PROGRAMN,
- REBOOT_IN => common_ctrl_reg(15),
+ REBOOT_IN => reboot_int,
-- I2C
SDA_INOUT => SFP_MOD_2, --open, --I2C_SDA,
SCL_INOUT => SFP_MOD_1, --open, --SI2C_SCL,
DEBUG_OUT => open
);
+ reboot_int <= common_ctrl_reg(15) or reboot_from_gbe;
+
-- led_off <= additional_reg(0);
-- FlashROM external connections