*** empty log message ***

diff --git a/testbenches/tb_handler_lvl1.vhd b/testbenches/tb_handler_lvl1.vhd
new file mode 100755 (executable)
index 0000000..09faaf5
--- /dev/null
+++ b/testbenches/tb_handler_lvl1.vhd
@@ -0,0 +1,337 @@
+LIBRARY ieee;\r
+USE ieee.std_logic_1164.ALL;\r
+USE ieee.numeric_std.ALL;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+\r
+ENTITY testbench IS\r
+END testbench;\r
+\r
+ARCHITECTURE behavior OF testbench IS \r
+\r
+       COMPONENT handler_lvl1\r
+       GENERIC(\r
+               TIMING_TRIGGER_RAW           : integer range 0 to 1 := c_YES\r
+       );\r
+       PORT(\r
+               RESET : IN std_logic;\r
+               CLOCK : IN std_logic;\r
+               LVL1_TIMING_TRG_IN : IN std_logic;\r
+               LVL1_PSEUDO_TMG_TRG_IN : IN std_logic;\r
+               LVL1_TRG_RECEIVED_IN : IN std_logic;\r
+               LVL1_TRG_TYPE_IN : IN std_logic_vector(3 downto 0);\r
+               LVL1_TRG_NUMBER_IN : IN std_logic_vector(15 downto 0);\r
+               LVL1_TRG_CODE_IN : IN std_logic_vector(7 downto 0);\r
+               LVL1_TRG_INFORMATION_IN : IN std_logic_vector(23 downto 0);\r
+               LVL1_INT_TRG_RESET_IN : IN std_logic;\r
+               LVL1_INT_TRG_LOAD_IN : IN std_logic;\r
+               LVL1_INT_TRG_COUNTER_IN : IN std_logic_vector(15 downto 0);\r
+               LVL1_ERROR_PATTERN_IN : IN std_logic_vector(31 downto 0);\r
+               LVL1_TRG_RELEASE_IN : IN std_logic;\r
+               TRG_ENABLE_IN : IN std_logic;\r
+               TRG_INVERT_IN : IN std_logic;          \r
+               LVL1_ERROR_PATTERN_OUT : OUT std_logic_vector(31 downto 0);\r
+               LVL1_TRG_RELEASE_OUT : OUT std_logic;\r
+               LVL1_INT_TRG_NUMBER_OUT : OUT std_logic_vector(15 downto 0);\r
+               LVL1_TRG_DATA_VALID_OUT : OUT std_logic;\r
+               LVL1_VALID_TIMING_TRG_OUT : OUT std_logic;\r
+               LVL1_VALID_NOTIMING_TRG_OUT : OUT std_logic;\r
+               LVL1_INVALID_TRG_OUT : OUT std_logic;\r
+               LVL1_MULTIPLE_TRG_OUT : OUT std_logic;\r
+               LVL1_DELAY_OUT : OUT std_logic_vector(15 downto 0);\r
+               STATUS_OUT : OUT std_logic_vector(31 downto 0);\r
+               DEBUG_OUT : OUT std_logic_vector(15 downto 0)\r
+               );\r
+       END COMPONENT;\r
+\r
+       SIGNAL RESET :  std_logic;\r
+       SIGNAL CLOCK :  std_logic;\r
+       SIGNAL LVL1_TIMING_TRG_IN :  std_logic;\r
+       SIGNAL LVL1_PSEUDO_TMG_TRG_IN :  std_logic;\r
+       SIGNAL LVL1_TRG_RECEIVED_IN :  std_logic;\r
+       SIGNAL LVL1_TRG_TYPE_IN :  std_logic_vector(3 downto 0);\r
+       SIGNAL LVL1_TRG_NUMBER_IN :  std_logic_vector(15 downto 0);\r
+       SIGNAL LVL1_TRG_CODE_IN :  std_logic_vector(7 downto 0);\r
+       SIGNAL LVL1_TRG_INFORMATION_IN :  std_logic_vector(23 downto 0);\r
+       SIGNAL LVL1_ERROR_PATTERN_OUT :  std_logic_vector(31 downto 0);\r
+       SIGNAL LVL1_TRG_RELEASE_OUT :  std_logic;\r
+       SIGNAL LVL1_INT_TRG_NUMBER_OUT :  std_logic_vector(15 downto 0);\r
+       SIGNAL LVL1_INT_TRG_RESET_IN :  std_logic;\r
+       SIGNAL LVL1_INT_TRG_LOAD_IN :  std_logic;\r
+       SIGNAL LVL1_INT_TRG_COUNTER_IN :  std_logic_vector(15 downto 0);\r
+       SIGNAL LVL1_TRG_DATA_VALID_OUT :  std_logic;\r
+       SIGNAL LVL1_VALID_TIMING_TRG_OUT :  std_logic;\r
+       SIGNAL LVL1_VALID_NOTIMING_TRG_OUT :  std_logic;\r
+       SIGNAL LVL1_INVALID_TRG_OUT :  std_logic;\r
+       SIGNAL LVL1_MULTIPLE_TRG_OUT :  std_logic;\r
+       SIGNAL LVL1_DELAY_OUT :  std_logic_vector(15 downto 0);\r
+       SIGNAL LVL1_ERROR_PATTERN_IN :  std_logic_vector(31 downto 0);\r
+       SIGNAL LVL1_TRG_RELEASE_IN :  std_logic;\r
+       SIGNAL STATUS_OUT :  std_logic_vector(31 downto 0);\r
+       SIGNAL TRG_ENABLE_IN :  std_logic;\r
+       SIGNAL TRG_INVERT_IN :  std_logic;\r
+       SIGNAL DEBUG_OUT :  std_logic_vector(15 downto 0);\r
+\r
+BEGIN\r
+\r
+-- Please check and add your generic clause manually\r
+       uut: handler_lvl1 \r
+       GENERIC MAP(\r
+               TIMING_TRIGGER_RAW => 1\r
+       )\r
+       PORT MAP(\r
+               RESET => RESET,\r
+               CLOCK => CLOCK,\r
+               LVL1_TIMING_TRG_IN => LVL1_TIMING_TRG_IN,\r
+               LVL1_PSEUDO_TMG_TRG_IN => LVL1_PSEUDO_TMG_TRG_IN,\r
+               LVL1_TRG_RECEIVED_IN => LVL1_TRG_RECEIVED_IN,\r
+               LVL1_TRG_TYPE_IN => LVL1_TRG_TYPE_IN,\r
+               LVL1_TRG_NUMBER_IN => LVL1_TRG_NUMBER_IN,\r
+               LVL1_TRG_CODE_IN => LVL1_TRG_CODE_IN,\r
+               LVL1_TRG_INFORMATION_IN => LVL1_TRG_INFORMATION_IN,\r
+               LVL1_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_OUT,\r
+               LVL1_TRG_RELEASE_OUT => LVL1_TRG_RELEASE_OUT,\r
+               LVL1_INT_TRG_NUMBER_OUT => LVL1_INT_TRG_NUMBER_OUT,\r
+               LVL1_INT_TRG_RESET_IN => LVL1_INT_TRG_RESET_IN,\r
+               LVL1_INT_TRG_LOAD_IN => LVL1_INT_TRG_LOAD_IN,\r
+               LVL1_INT_TRG_COUNTER_IN => LVL1_INT_TRG_COUNTER_IN,\r
+               LVL1_TRG_DATA_VALID_OUT => LVL1_TRG_DATA_VALID_OUT,\r
+               LVL1_VALID_TIMING_TRG_OUT => LVL1_VALID_TIMING_TRG_OUT,\r
+               LVL1_VALID_NOTIMING_TRG_OUT => LVL1_VALID_NOTIMING_TRG_OUT,\r
+               LVL1_INVALID_TRG_OUT => LVL1_INVALID_TRG_OUT,\r
+               LVL1_MULTIPLE_TRG_OUT => LVL1_MULTIPLE_TRG_OUT,\r
+               LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN,\r
+               LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN,\r
+               LVL1_DELAY_OUT => LVL1_DELAY_OUT,\r
+               STATUS_OUT => STATUS_OUT,\r
+               TRG_ENABLE_IN => TRG_ENABLE_IN,\r
+               TRG_INVERT_IN => TRG_INVERT_IN,\r
+               DEBUG_OUT => DEBUG_OUT\r
+       );\r
+\r
+THE_CLOCK_GEN: process\r
+begin\r
+       CLOCK <= '0'; wait for 5.0 ns;\r
+       CLOCK <= '1'; wait for 5.0 ns;\r
+end process THE_CLOCK_GEN;\r
+\r
+THE_TESTBENCH: process\r
+begin\r
+       -----------------------------------------------------------\r
+       -- Setup signals\r
+       -----------------------------------------------------------\r
+       reset <= '0';\r
+       lvl1_timing_trg_in <= '0'; -- real timing trigger\r
+       lvl1_pseudo_tmg_trg_in <= '0'; -- one clock pulse form TRB \r
+       lvl1_trg_received_in <= '0';\r
+       lvl1_trg_type_in <= x"0";\r
+       lvl1_trg_number_in <= x"0000";\r
+       lvl1_trg_code_in <= x"00";\r
+       lvl1_trg_information_in <= x"000000";\r
+       lvl1_int_trg_reset_in <= '0';\r
+       lvl1_int_trg_load_in <= '0';\r
+       lvl1_int_trg_counter_in <= x"0000";\r
+       lvl1_error_pattern_in <= x"0000_0000";\r
+       lvl1_trg_release_in <= '0';\r
+       trg_enable_in <= '0';\r
+       trg_invert_in <= '0';\r
+\r
+       -----------------------------------------------------------\r
+       -- Reset the whole stuff\r
+       -----------------------------------------------------------\r
+       wait until rising_edge(clock);\r
+       reset <= '1';\r
+       wait until rising_edge(clock);\r
+       wait until rising_edge(clock);\r
+       reset <= '0';\r
+       wait for 100 ns;\r
+       \r
+       -----------------------------------------------------------\r
+       -- Tests may start now\r
+       -----------------------------------------------------------\r
+\r
+       -- enable trigger\r
+       wait until rising_edge(clock);\r
+       trg_enable_in <= '1';\r
+       wait for 100 ns;\r
+\r
+       -----------------------------------------------------------\r
+\r
+       -- ONE TRIGGER (timing)\r
+\r
+       -- receive one normal timing trigger\r
+       wait for 3 ns;\r
+       lvl1_timing_trg_in <= '1';\r
+       wait for 111 ns;\r
+       lvl1_timing_trg_in <= '0';      \r
+       wait for 1000 ns;\r
+\r
+       -- LVL1 packet is there\r
+       wait until rising_edge(clock);\r
+       lvl1_trg_type_in <= x"1";\r
+       lvl1_trg_number_in <= x"0000";\r
+       lvl1_trg_code_in <= x"ab";\r
+       lvl1_trg_information_in <= x"000000";\r
+       wait until rising_edge(clock);\r
+       lvl1_trg_received_in <= '1';\r
+\r
+       wait for 211 ns;        \r
+       wait until rising_edge(clock);\r
+       lvl1_trg_release_in <= '1';     \r
+       wait until rising_edge(clock);\r
+       lvl1_trg_release_in <= '0';     \r
+\r
+       wait until falling_edge(lvl1_trg_release_out);\r
+       wait until rising_edge(clock);\r
+       lvl1_trg_received_in <= '0';\r
+       lvl1_trg_type_in <= x"0";\r
+       lvl1_trg_number_in <= x"0000";\r
+       lvl1_trg_code_in <= x"00";\r
+       lvl1_trg_information_in <= x"000000";\r
+\r
+       wait for 555 ns;\r
+\r
+       -----------------------------------------------------------\r
+\r
+       -- ONE TRIGGER (timing)\r
+\r
+       -- receive one normal timing trigger\r
+       wait for 3 ns;\r
+       lvl1_timing_trg_in <= '1';\r
+       wait for 111 ns;\r
+       lvl1_timing_trg_in <= '0';      \r
+       \r
+       wait for 300 ns;\r
+       lvl1_timing_trg_in <= '1';\r
+       wait for 111 ns;\r
+       lvl1_timing_trg_in <= '0';      \r
+       wait for 200 ns;\r
+\r
+       -- LVL1 packet is there\r
+       wait until rising_edge(clock);\r
+       lvl1_trg_type_in <= x"1";\r
+       lvl1_trg_number_in <= x"0001";\r
+       lvl1_trg_code_in <= x"71";\r
+       lvl1_trg_information_in <= x"000000";\r
+       wait until rising_edge(clock);\r
+       lvl1_trg_received_in <= '1';\r
+\r
+       wait for 211 ns;        \r
+       wait until rising_edge(clock);\r
+       lvl1_trg_release_in <= '1';     \r
+       wait until rising_edge(clock);\r
+       lvl1_trg_release_in <= '0';     \r
+\r
+       wait until falling_edge(lvl1_trg_release_out);\r
+       wait until rising_edge(clock);\r
+       lvl1_trg_received_in <= '0';\r
+       lvl1_trg_type_in <= x"0";\r
+       lvl1_trg_number_in <= x"0000";\r
+       lvl1_trg_code_in <= x"00";\r
+       lvl1_trg_information_in <= x"000000";\r
+\r
+       wait for 555 ns;\r
+\r
+       -----------------------------------------------------------\r
+       -- ONE TRIGGER (timing, wrong counter on LVL1)\r
+\r
+       -- receive one normal timing trigger\r
+       wait for 3 ns;\r
+       lvl1_timing_trg_in <= '1';\r
+       wait for 111 ns;\r
+       lvl1_timing_trg_in <= '0';      \r
+       wait for 1000 ns;\r
+\r
+       -- LVL1 packet is there\r
+       wait until rising_edge(clock);\r
+       lvl1_trg_type_in <= x"1";\r
+       lvl1_trg_number_in <= x"dead";\r
+       lvl1_trg_code_in <= x"cc";\r
+       lvl1_trg_information_in <= x"000000";\r
+       wait until rising_edge(clock);\r
+       lvl1_trg_received_in <= '1';\r
+\r
+       wait for 211 ns;        \r
+       wait until rising_edge(clock);\r
+       lvl1_trg_release_in <= '1';     \r
+       wait until rising_edge(clock);\r
+       lvl1_trg_release_in <= '0';     \r
+\r
+       wait until falling_edge(lvl1_trg_release_out);\r
+       wait until rising_edge(clock);\r
+       lvl1_trg_received_in <= '0';\r
+       lvl1_trg_type_in <= x"0";\r
+       lvl1_trg_number_in <= x"0000";\r
+       lvl1_trg_code_in <= x"00";\r
+       lvl1_trg_information_in <= x"000000";\r
+\r
+       wait for 555 ns;\r
+\r
+       -----------------------------------------------------------\r
+       -- ONE TRIGGER (timing, missing LVL1)\r
+\r
+       -- receive one normal timing trigger\r
+       wait for 3 ns;\r
+       lvl1_timing_trg_in <= '1';\r
+       wait for 111 ns;\r
+       lvl1_timing_trg_in <= '0';      \r
+       wait for 1000 ns;\r
+\r
+       wait for 6 us;\r
+\r
+       -----------------------------------------------------------\r
+\r
+       -- ONE TRIGGER (timingtriggerless)\r
+       \r
+       -- LVL1 packet is there\r
+       wait until rising_edge(clock);\r
+       lvl1_trg_type_in <= x"9";\r
+       lvl1_trg_number_in <= x"0002";\r
+       lvl1_trg_code_in <= x"f0";\r
+       lvl1_trg_information_in <= x"000080";\r
+       wait until rising_edge(clock);\r
+       lvl1_trg_received_in <= '1';\r
+\r
+       wait for 211 ns;        \r
+       wait until rising_edge(clock);\r
+       lvl1_trg_release_in <= '1';     \r
+       wait until rising_edge(clock);\r
+       lvl1_trg_release_in <= '0';     \r
+\r
+       wait until falling_edge(lvl1_trg_release_out);\r
+       wait until rising_edge(clock);\r
+       lvl1_trg_received_in <= '0';\r
+       lvl1_trg_type_in <= x"0";\r
+       lvl1_trg_number_in <= x"0000";\r
+       lvl1_trg_code_in <= x"00";\r
+       lvl1_trg_information_in <= x"000000";\r
+\r
+       wait for 555 ns;\r
+\r
+       -----------------------------------------------------------\r
+\r
+       wait;\r
+       \r
+       -----------------------------------------------------------\r
+               \r
+       -- receive one TRB fake trigger\r
+       wait until rising_edge(clock);\r
+       lvl1_pseudo_tmg_trg_in <= '1';\r
+       wait until rising_edge(clock);\r
+       lvl1_pseudo_tmg_trg_in <= '0';\r
+       wait for 300 ns;\r
+\r
+       -- receive one spike\r
+       wait for 3 ns;\r
+       lvl1_timing_trg_in <= '1';\r
+       wait for 17 ns;\r
+       lvl1_timing_trg_in <= '0';      \r
+       wait for 300 ns;\r
+       \r
+       -- Stay a while.... stay forever!!! Muahahah!!!!\r
+       wait;\r
+end process THE_TESTBENCH;\r
+\r
+END;\r