*** empty log message ***

diff --git a/main.tex b/main.tex
index 16092d15ae11fb8be4b2d936c5b297c67e414e78..7b9f7541931fba91d6b01764493994d1cc80dc22 100755 (executable)
--- a/main.tex
+++ b/main.tex
@@ -64,17 +64,17 @@
 \usepackage{remreset}
 \makeatletter\@removefromreset{footnote}{chapter}\makeatother
 
-\lstset{ %language = VHDL, 
+\lstset{ language = VHDL, 
          numbers =left, 
          stepnumber =1, 
          frame =single,
          captionpos=b,
          breaklines=true
-        % basicstyle=\footnotesize,
-         %identifierstyle=\footnotesize,
-         stringstyle=\footnotesize,
-         numberstyle=\footnotesize,
-         fontadjust=true}
+         basicstyle=\small,
+         identifierstyle=\small,
+         stringstyle=\small,
+         numberstyle=\small,
+         fontadjust=false}
 
 \begin{document}
 \newcounter{line}

diff --git a/regio.png b/regio.png
new file mode 100755 (executable)
index 0000000..5965fa7
Binary files /dev/null and b/regio.png differ

diff --git a/slowcontrol.tex b/slowcontrol.tex
index 2894a445c6e6f4c436d50337c6b628ae414109e8..f7f681788cd919d3f526ed58e6a4b046f67fced2 100755 (executable)
--- a/slowcontrol.tex
+++ b/slowcontrol.tex
@@ -1,6 +1,60 @@
-The slowcontrol endpoint (``RegIO'') allows to read and write data from and to the endpoints. For this purpose it uses 16 bit wide addresses and 32 bit wide data words along with read/write strobe signals for all operations.
+\label{RegIO}
+The RegIO component handles all data received on the slow control channel. Its structure is depicted in figure \ref{fig:regio}. It provides status registers that are common for all boards, user defineable
+status and control registers, and stores information about the hardware. As already mentioned, these common registers are needed to provide a universal monitoring tool for all parts of the detector.
+
+Each register has one 16Bit address assigned as shown in Table~\ref{regioaddressmap}.
+Each address corresponds to one 32 Bit register or data word.
+
+To access all registers and other information, a simple command structure is
+defined. The protocol is quite simple: For each access a 64 bit data word
+is sent as shown in Table~\ref{RegIO:protocol}. The \netname{dtype} of the
+packets carries the desired operation, followed by the first 16 bit word with
+the register address and, in case of a write access, 32 bits of data.
+Altogether there are four different operations implemented: Single and multiple reads and writes from
+or to the same (or ascending) address. The multiple access is only supported on the internal
+data port and can be used to read data from a FIFO.
+
+\begin{figure}
+       \centering
+               \includegraphics[scale=.8]{regio.png}
+       \caption[Register read / write controller]{Implementation of the
+register read / write and address controllers. Data received from the
+application interface is interpreted by a central controller that access
+various registers as requested. An address controller manages the network
+addresses and the board ID.}
+       \label{fig:regio}
+\end{figure}
+
+
+\begin{table}
+\begin{center}
+  \begin{tabular}[c]{|c|c|c|c|c|c|}
+  \hline
+  \textsc{Dtype} & \textsc{Description} & F0 & F1 & F2 & F3 \\ 
+  \hline\hline
+  8 & read register & address & 0 & 0 & reserved\\
+  9 & write register & address & data(31..16) & data(15..0) & reserved \\
+  A & read multiple & address & config* & 0 & reserved \\
+  B & write multiple & address & config* & 0 & reserved \\
+    &                & 0  & data(31..16) & data(15..0) & reserved \\
+  F & network administration & \multicolumn{4}{c|}{see
+section about addresses} \\
+  \hline
+  \end{tabular}
+  \caption{[Register read/write protocol]Register read/write protocol. The config word for multiple accesses has the highest bit selecting between fixed (0) addresses and ascending (1) addresses. The lower 15 bit on the read operation select the maximum number of read accesses to be made. A multiple write always consists of one starting word containing address and mode followed by an arbitrary number of data packets.}
+  \label{RegIO:protocol}
+\end{center}
+\end{table} 
+
+
+Internally it also has logic to readout the 1-wire temperature logic and to assign network addresses. Other features include a global timer and configurable easy-to-use status and control registers. Additional, more complex logic can be connected to the internal data bus.
+
+
+
+
+
+
 
-Internally it also has logic to readout the 1-wire temperature logic and to assign network addresses. Other features include a global timer and configurable easy-to-use status and control registers. Additional, more complex logic can be connected to an internal data bus.
 
 
 
@@ -23,21 +77,23 @@ Common_Stat_Reg_Strobe(std_comstatreg-1 downto 0)
 Common_Ctrl_Reg_Strobe(std_comctrlreg-1 downto 0)
 Stat_Reg_Strobe(2**(num_stat_regs)-1 downto 0)
 Ctrl_Reg_Strobe(2**(num_ctrl_regs)-1 downto 0)
-\end{lstlisting} 
+\end{lstlisting}
 
 
-\paragraph{Onewire} 
+\paragraph{Onewire}
 The temperature sensor on each board is connected to the following ports. In case no temperature sensor is connected directly, the generic setting \genericname{Regio\_Use\_1wire\_Interface} has to be set accordingly.
 
 \begin{description}
- \item[Regio\_Onewire\_Inout] Direct connection to a 1-wire temperature sensor
- \item[Regio\_Onewire\_Monitor\_Out] Outputs a copy of the signals on the 1-wire bus. Used to transport information to another FPGA.
- \item[Regio\_Onewire\_Monitor\_In] The corresponding input to monitor traffic on a 1-wire bus if no sensor is connected directly to the fpga.
+ \item[\portname{Regio\_Onewire\_Inout}] Direct connection to a 1-wire temperature sensor
+ \item[\portname{Regio\_Onewire\_Monitor\_Out}] Outputs a copy of the signals on the 1-wire bus. Used to transport information to another FPGA.
+ \item[\portname{Regio\_Onewire\_Monitor\_In}] The corresponding input to monitor traffic on a 1-wire bus if no sensor is connected directly to the fpga.
 \end{description}
 
 
 
 \paragraph{Timers}
+The timers give a rough information on the current time. The global time can be set using normal slow control accesses. That means, it has an inherent ambiguity of about 200 ns plus a drift of up to 20ppm compared to other boards. The additional timer ticks can be used to simplify other parts of the logic, e.g. as clock enable signal for slowly running parts of the design.
+
 \begin{description}
  \item[\portname{Global\_Time\_Out}] The global time measured in microseconds. This time will be synchronized on all boards from time to time to keep descrepancies between the boards low. E.g. used for marking debugging and status information.
  \item[\portname{Local\_Time\_Out}] The local time is used to measure in the sub-microsecond range. It counts with the internal clock frequency (standard: 100 MHz) and is reset each microsecond.
@@ -55,7 +111,7 @@ An access cycle on the internal data bus consists of two actions: First, RegIO s
  \item[\portname{Regio\_Addr\_Out}] (16 bit) address port. Address is valid when either of \portname{read\_enable} and \portname{write\_enable} is high.
  \item[\portname{Regio\_Read\_Enable\_Out}] Read enable strobe.
  \item[\portname{Regio\_Write\_Enable\_Out}] Write enable strobe.
- \item[\portname{Regio\_Data\_Out}] (32 bit) Data output of regIO, input to the user. Valid when \portname{write\_enable} is high. 
+ \item[\portname{Regio\_Data\_Out}] (32 bit) Data output of regIO, input to the user. Valid when \portname{write\_enable} is high.
  \item[\portname{Regio\_Data\_In}] (32 bit) Data input to regIO, output from the user. Valid when \portname{dataready\_in} is high.
  \item[\portname{Regio\_Dataready\_In}] User signal to show that \portname{data\_in} is valid. May only be used after a strobe on \portname{read\_enable}.
  \item[\portname{Regio\_No\_More\_Data\_In}] User signal. After a read strobe: User has no more data to read from this address. After a write strobe: User is not able to handle more data on this address now.
@@ -72,78 +128,74 @@ An access cycle on the internal data bus consists of two actions: First, RegIO s
  \item[\portname{Regio\_Init\_Ctrl\_Regs}] The initial value of all control registers. This generic has a fixed size of 8x32 bits
  \item[\portname{Regio\_Use\_Dat\_Port}] Selects to have an internal data port to connect own registers to in the address space above 0x0100
  \item[\portname{Regio\_Use\_1wire\_Interface}] Set to \constname{c\_Yes} means a temperature sensor is connected, \constname{c\_\-Mon\-itor} means there is a 1-wire data stream sent by another FPGA, \constname{c\_No} means temperature and unique id are written using some user supplied logic.
-\end{description}
+ \item[\portname{Use\_Dat\_Port}] The internal data port can be switched off if not in use. Hence, all accesses to addresses above 0x100 will be automatically answered by RegIO.
+ \item[\portname{Init\_Address}] The network address the board is given initially. (note: does not work using Synplify under Linux)
+ \item[\portname{Init\_Endpoint\_Id}] The endpoint ID. On boards with two or more FPGAs this is usually the FPGA number according to the boards schematics. Boards with only one FPGA use 1 here. Basic Rule: Each FPGA connected to the same temperature sensore has to have a different endpoint ID to be indentifieable.
+ \item[\portname{Compile\_Time}] The UNIX timestamp when the design has been compiled. Must be set by hand or using our standard compile script.
+ \item[\portname{Hardware\_Version}] These 32bit give information about the type of hardware. The upper 16 bit are defined in table \ref{HardwareInformation}, the lower 16 bits are free to use.
 
 
-\subsection{RegIo Bus Handler}
-If you want to connect several registers or function blocks to the internal data bus, you can use the RegIO Bus Handler. This special entity (\filename{trb\_net16\_regio\_bus\_handler}) simplifies to generate several address sub-spaces on the internal data bus. It is configured using three generic values as shown in this listing:
+\end{description}
 
-\lstset { caption ={Configuration of RegIO Bus Handler}}
-\begin{lstlisting}
-The_Regio_Bus_Handler : trb_net16_regio_bus_handler
- generic map(
-  Port_Number => 2,
-  Port_Addresses => (0=>x"A000", 1=>x"8000", others=>x"0000"),
-  Port_Addr_Mask => (0=>8,       1=>6,       others=>0)
-  )
-\end{lstlisting} 
 
-This setting introduces two address spaces: One starting at 0xA000 with a size of 2**8 addresses, i.e. from 0xA000 to 0xA0FF, and one starting at 0x8000 with 2**6 addresses, i.e. from 0x8000 to 0x803F.
+
+\subsection{RegIo Bus Handler}
+If you want to connect several registers or function blocks to the internal data bus, you can use the RegIO Bus Handler. This special entity (\filename{trb\_net16\_regio\_bus\_handler}) simplifies to generate several address sub-spaces on the internal data bus. It is configured using three generic values as shown in the listing below. These settings introduce two address spaces: One starting at 0xA000 with a size of 2**8 addresses, i.e. from 0xA000 to 0xA0FF, and one starting at 0x8000 with 2**6 addresses, i.e. from 0x8000 to 0x803F.
 
 The behaviour on the data busses is identical to the original RegIO interface. Connecting to the different address spaces can be done in a convenient form as shown in the following piece of code:
 
 \lstset { caption ={Excerpt from the regio\_bus\_handler used in MDC OEP.}}
 \begin{lstlisting}
-  THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler
-    generic map(
-      PORT_NUMBER => 6,
-      PORT_ADDRESSES => 
-          (0 => x"A000", 1 => x"8000",  others => x"0000"),
-      PORT_ADDR_MASK => 
-          (0 => 8,       1 => 6,        others => 0)
-      )
-    port map(
-      clk                   => clk_100,
-      reset                 => reset_internal,
-    --I/O to RegIO
-      dat_addr_in           => regio_addr_out,
-      dat_data_in           => regio_data_out,
-      dat_data_out          => regio_data_in,
-      dat_read_enable_in    => regio_read_enable_out,
-      dat_write_enable_in   => regio_write_enable_out,
-      dat_timeout_in        => regio_timeout_out,
-      dat_dataready_out     => regio_dataready_in,
-      dat_write_ack_out     => regio_write_ack_in,
-      dat_no_more_data_out  => regio_no_more_data_in,
-      dat_unknown_addr_out  => regio_unknown_addr_in,
-    --Bus Handler (Threshold memory)
-      bus_read_enable_out(0)              => thresh_mem_read,
-      bus_write_enable_out(0)             => thresh_mem_write,
-      bus_data_out(0*32+15 downto 0*32)   => thresh_mem_data,
-      bus_data_out(0*32+31 downto 0*32+16)=> open,
-      bus_addr_out(0*16+8 downto 0*16)    => thresh_mem_addr,
-      bus_addr_out(0*16+15 downto 0*16+9) => open,
-      bus_timeout_out(0)                  => open,
-      bus_data_in(0*32+15 downto 0*32)    => thresh_mem_data_out,
-      bus_data_in(0*32+31 downto 0*32+16) => x"0000",
-      bus_dataready_in(0)                 => last_reg_regio_read,
-      bus_write_ack_in(0)                 => reg_regio_write,
-      bus_no_more_data_in(0)              => '0',
-      bus_unknown_addr_in(0)              => '0',
-    --Bus Handler (ADC)
-      bus_read_enable_out(1)              => adc_read,
-      bus_write_enable_out(1)             => adc_write,
-      bus_data_out(1*32+31 downto 1*32)   => adc_data_in,
-      bus_addr_out(1*16+5 downto 1*16)    => adc_addr,
-      bus_addr_out(1*16+15 downto 1*16+6) => open,
-      bus_timeout_out(1)                  => adc_timeout,
-      bus_data_in(1*32+31 downto 1*32)    => adc_data_out,
-      bus_dataready_in(1)                 => adc_dataready,
-      bus_write_ack_in(1)                 => adc_write_ack,
-      bus_no_more_data_in(1)              => adc_no_more_data,
-      bus_unknown_addr_in(1)              => adc_unknown_addr,
-      [...]
-\end{lstlisting} 
+THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler
+generic map(
+  PORT_NUMBER => 6,
+  PORT_ADDRESSES =>
+      (0 => x"A000", 1 => x"8000",  others => x"0000"),
+  PORT_ADDR_MASK =>
+      (0 => 8,       1 => 6,        others => 0)
+  )
+port map(
+  clk                   => clk_100,
+  reset                 => reset_internal,
+--I/O to RegIO
+  dat_addr_in           => regio_addr_out,
+  dat_data_in           => regio_data_out,
+  dat_data_out          => regio_data_in,
+  dat_read_enable_in    => regio_read_enable_out,
+  dat_write_enable_in   => regio_write_enable_out,
+  dat_timeout_in        => regio_timeout_out,
+  dat_dataready_out     => regio_dataready_in,
+  dat_write_ack_out     => regio_write_ack_in,
+  dat_no_more_data_out  => regio_no_more_data_in,
+  dat_unknown_addr_out  => regio_unknown_addr_in,
+--Bus Handler (Threshold memory)
+  bus_read_enable_out(0)              => thresh_mem_read,
+  bus_write_enable_out(0)             => thresh_mem_write,
+  bus_data_out(0*32+15 downto 0*32)   => thresh_mem_data,
+  bus_data_out(0*32+31 downto 0*32+16)=> open,
+  bus_addr_out(0*16+8 downto 0*16)    => thresh_mem_addr,
+  bus_addr_out(0*16+15 downto 0*16+9) => open,
+  bus_timeout_out(0)                  => open,
+  bus_data_in(0*32+15 downto 0*32)    => thresh_mem_data_out,
+  bus_data_in(0*32+31 downto 0*32+16) => x"0000",
+  bus_dataready_in(0)                 => last_reg_regio_read,
+  bus_write_ack_in(0)                 => reg_regio_write,
+  bus_no_more_data_in(0)              => '0',
+  bus_unknown_addr_in(0)              => '0',
+--Bus Handler (ADC)
+  bus_read_enable_out(1)              => adc_read,
+  bus_write_enable_out(1)             => adc_write,
+  bus_data_out(1*32+31 downto 1*32)   => adc_data_in,
+  bus_addr_out(1*16+5 downto 1*16)    => adc_addr,
+  bus_addr_out(1*16+15 downto 1*16+6) => open,
+  bus_timeout_out(1)                  => adc_timeout,
+  bus_data_in(1*32+31 downto 1*32)    => adc_data_out,
+  bus_dataready_in(1)                 => adc_dataready,
+  bus_write_ack_in(1)                 => adc_write_ack,
+  bus_no_more_data_in(1)              => adc_no_more_data,
+  bus_unknown_addr_in(1)              => adc_unknown_addr,
+  [...]
+\end{lstlisting}
 
 
 
@@ -235,3 +287,46 @@ The first common control register consists of strobe signals for dummy timing tr
 \label{CommonCtrlReg0}
 \end{center}
 \end{table}
+
+\paragraph{Hardware Information (0x42)}
+This register holds information about the type of hardware. The upper 16 bit define the hardware type, the lower 16 bit are kept free to mark minor differences in the hardware setup such as optional patch wires used in the design. Design variants can also be marked using these bits. Their definition is given in the section dealing with detector specific features. The upper 16 bit are defined in table \ref{HardwareInformation}
+
+\begin{table}[htbp]
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|X|}
+\hline
+\textbf{Value (hex)} &  \textbf{Description} \\
+\hline
+\hline
+1110 & MDC AddOn version 1 FPGA 1 \\
+1120 & MDC AddOn version 1 FPGA 2 \\
+1130 & MDC AddOn version 1 FPGA 3 \\
+1210 & MDC AddOn version 2 FPGA 1 -- 4\\
+1250 & MDC AddOn version 2 FPGA 5 \\
+2100 & MDC OEP version 1 \\
+2200 & MDC OEP version 2 \\
+2300 & MDC OEP version 3 \\
+3100 & RICH ADCM version 1 \\
+3200 & RICH ADCM version 2 \\
+3300 & RICH ADCM version 3 \\
+4100 & Shower AddOn version 1 \\
+4210 & Shower AddOn version 2 FPGA 1 \\
+4220 & Shower AddOn version 2 FPGA 2 \\
+4230 & Shower AddOn version 2 FPGA 3 \\
+5100 & CTS AddOn FPGA 1 \\
+5200 & CTS AddOn FPGA 2 \\
+6100 & Hub AddOn version 1 \\
+6210 & Hub AddOn version 2 FPGA 1 \\
+6220 & Hub AddOn version 2 FPGA 2 without GbE\\
+6221 & Hub AddOn version 2 FPGA 2 with GbE\\
+7300 & PEXOR version 3 \\
+8000 & TRB (purpose not defined)\\
+8100 & TOF TRB \\
+8200 & Start/Veto TRB \\
+8300 & RPC TRB \\
+\hline
+\end{tabularx}
+\caption{Upper 16 bit in register 0x42 marking the hardware the design is belonging to. The value can be set by a generic value of the TrbNet endpoint. The lower 16bit are not globally defined.}
+\label{HardwareInformation}
+\end{center}
+\end{table}

diff --git a/software.tex b/software.tex
index 26d933b016a99d96474760b5accb2f16b4e8468c..be1f30e78555e3dd85680c9f3640b91d41e832ab 100755 (executable)
--- a/software.tex
+++ b/software.tex
@@ -22,7 +22,7 @@ Currently, there are three main software tools for accessing TrbNet: trbcmd, trb
 Placeholders are defined as follows:
 \begin{description}
  \item[\$addr] TrbNet address, 16bit long, preceded by \verb|ax| prefix in the form, example: \verb|ax1234| or system name (\$system)
- \item[\$channel] A value identifying a TrbNet channel. Usually either 0,1 or 3.
+ \item[\$channel] A value identifying a TrbNet channel. Usually either 0,1 or 3. Verbose names trigger, ipu, control can also be used.
  \item[\$read] A keyword, one of \verb|read| and \verb|get|
  \item[\$port] A value identifying one port of a hub. Usually a number between 0 and 12.
  \item[\$select] A keyword, one of \verb|select|, \verb|set| and \verb|switch|
@@ -105,8 +105,8 @@ Gives back information about hub ports on which a timeout occured. Standard outp
 Example output: \verb|Timeout on hub f123 channel 0 port 7| \\
 The raw option gives the same information but as one 32bit value per channel and board with one bit set for each port with a timeout.
 
-\paragraph*{\$read hub packets} optional: \verb|$addr|, \verb|raw|, \verb|port $port| \\
-Reads the amount of packets received on IPU and slow control channel on the given hub and port or for all ports if now port number is given. The raw option outputs one 32bit number, lower 16bit are the packet counter on IPU, upper 16 bit are the packet counter on the slow control channel.
+\paragraph*{\$read hub packets channel \$channel} optional: \verb|$addr|, \verb|raw|, \verb|port $port| \\
+Reads the amount of packets received on IPU and slow control channel on the given hub and port or for all ports if no port number is given. The raw option outputs one 32bit number for each channel.
 
 \paragraph*{\$read hub waiting (channel \$channel)?} optional: \verb|$addr|, \verb|raw| \\
 Shows all ports and channels on the addressed hubs that are currently waiting for a reply (more precisely: waiting for a TRM in the reply channel). Although channel can be chosen freely, the value read on channel 3 is accurate, but all connected channels will always be marked as waiting. This is the case since there actually is a transfer going on - namely this request itself. If no channel is selected, information from all channels 0 and 1 is shown. The output is either in plain text (standard) or in raw format.