trigger generation logic for Hades Start Detector

diff --git a/32PinAddOn/trb3_periph_32PinAddOn.vhd b/32PinAddOn/trb3_periph_32PinAddOn.vhd
index ae0dc5d67c0bd9ee1e910ee93309ec66f456c4ac..2943200156f643e572dae85a487debc250bd108c 100644 (file)
--- a/32PinAddOn/trb3_periph_32PinAddOn.vhd
+++ b/32PinAddOn/trb3_periph_32PinAddOn.vhd
@@ -364,7 +364,7 @@ begin
       REGIO_NUM_STAT_REGS       => REGIO_NUM_STAT_REGS,
       REGIO_NUM_CTRL_REGS       => REGIO_NUM_CTRL_REGS,
       ADDRESS_MASK              => x"FFFF",
-      BROADCAST_BITMASK         => x"FF",
+      BROADCAST_BITMASK         => x"48",
       BROADCAST_SPECIAL_ADDR    => BROADCAST_SPECIAL_ADDR,
       REGIO_COMPILE_TIME        => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME, 32)),
       REGIO_HARDWARE_VERSION    => HARDWARE_INFO,
@@ -483,7 +483,7 @@ begin
     generic map(
       PORT_NUMBER    => 10,
       PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", 9 => x"a000", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 3, 9 => 4, others => 0)
+      PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 3, 9 => 6, others => 0)
       )
     port map(
       CLK   => clk_100_i,

diff --git a/base/code/input_to_trigger_logic.vhd b/base/code/input_to_trigger_logic.vhd
index d37ee77b9e954bae1403cf81cf7e425729f5ae69..8b595c80d1480e1b15149a7cf43e0e29fbf083cf 100644 (file)
--- a/base/code/input_to_trigger_logic.vhd
+++ b/base/code/input_to_trigger_logic.vhd
@@ -1,7 +1,7 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
-
+use work.trb_net_std.all;
 
 
 entity input_to_trigger_logic is
@@ -30,17 +30,41 @@ end entity;
 
 architecture input_to_trigger_logic_arch of input_to_trigger_logic is
 
- 
+type reg_t is array(0 to OUTPUTS-1) of std_logic_vector(31 downto 0);
+signal enable : reg_t;
+signal invert : reg_t;
 
 begin
 
-OUTPUT <= INPUT(OUTPUTS-1 downto 0);
 
-THE_CONTROL : process begin
+THE_CONTROL : process 
+  variable tmp : integer range 0 to 15;
+begin
   wait until rising_edge(CLK);
-  
-  
+  ACK_OUT  <= '0';
+  NACK_OUT <= '0';
+  tmp := to_integer(unsigned(ADDR_IN(5 downto 2)));
+  if WRITE_IN = '1' then
+    ACK_OUT <= '1';
+    case ADDR_IN(1 downto 0) is
+      when "00"   => enable(tmp) <= DATA_IN;
+      when "01"   => invert(tmp) <= DATA_IN;
+      when others => NACK_OUT <= '1'; ACK_OUT <= '0';
+    end case;
+  elsif READ_IN = '1' then
+    ACK_OUT <= '1';
+    case ADDR_IN(1 downto 0) is
+      when "00"   => DATA_OUT <= enable(tmp);
+      when "01"   => DATA_OUT <= invert(tmp);
+      when others => DATA_OUT <= (others => '0');
+    end case;
+  end if;
 end process;
 
+gen_outs : for i in 0 to OUTPUTS-1 generate
+  OUTPUT(i) <= or_all((INPUT xor invert(i)(INPUTS-1 downto 0)) and enable(i)(INPUTS-1 downto 0));
+end generate;
+
+
 
 end architecture;
\ No newline at end of file