CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0);
CFG_AUTO_THROTTLE_IN : in std_logic;
CFG_THROTTLE_PAUSE_IN : in std_logic_vector(15 downto 0);
+ CFG_IP_IN : in std_logic_vector(31 downto 0);
-- Forwarder
FWD_DST_MAC_IN : in std_logic_vector(47 downto 0);
CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN,
CFG_AUTO_THROTTLE_IN => '0', --CFG_AUTO_THROTTLE_IN,
CFG_THROTTLE_PAUSE_IN => (others => '0'), --CFG_THROTTLE_PAUSE_IN,
+ CFG_IP_IN => CFG_IP_IN,
FWD_DST_MAC_IN => FWD_DST_MAC_IN,
FWD_DST_IP_IN => FWD_DST_IP_IN,
BUS_REG_RX : in CTRLBUS_RX;
BUS_REG_TX : out CTRLBUS_TX;
+ FORCE_IP_L0_IN : in std_logic_vector(31 downto 0) := (others => '0');
+ FORCE_IP_L1_IN : in std_logic_vector(31 downto 0) := (others => '0');
+ FORCE_IP_L2_IN : in std_logic_vector(31 downto 0) := (others => '0');
+ FORCE_IP_L3_IN : in std_logic_vector(31 downto 0) := (others => '0');
+
-- Forwarder
FWD_DST_MAC_IN : in std_logic_vector(48 * NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
FWD_DST_IP_IN : in std_logic_vector(32 * NUMBER_OF_GBE_LINKS - 1 downto 0) := (others => '0');
signal issue_reboot : std_logic_vector(3 downto 0);
+ signal cfg_ip_l0, cfg_ip_l1, cfg_ip_l2, cfg_ip_l3 : std_logic_vector(31 downto 0);
+ signal fxd_ip_l0, fxd_ip_l1, fxd_ip_l2, fxd_ip_l3 : std_logic_vector(31 downto 0);
+
+
begin
mac_impl_gen : if DO_SIMULATION = 0 generate
mac_0 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
INCLUDE_DHCP => LINK_HAS_DHCP(3),
INCLUDE_ARP => LINK_HAS_ARP(3),
INCLUDE_PING => LINK_HAS_PING(3),
- INCLUDE_FWD => LINK_HAS_FWD(3),
+ INCLUDE_FWD => LINK_HAS_FWD(3),
FRAME_BUFFER_SIZE => 1,
READOUT_BUFFER_SIZE => 4,
SLOWCTRL_BUFFER_SIZE => 2,
CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
+CFG_IP_IN => fxd_ip_l3,
+
FWD_DST_MAC_IN => FWD_DST_MAC_IN(4 * 48 - 1 downto 3 * 48),
FWD_DST_IP_IN => FWD_DST_IP_IN(4 * 32 - 1 downto 3 * 32),
FWD_DST_UDP_IN => FWD_DST_UDP_IN(4 * 16 - 1 downto 3 * 16),
CFG_MAX_REPLY_SIZE_IN => cfg_max_reply,
CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
+
+CFG_IP_IN => fxd_ip_l2,
+
FWD_DST_MAC_IN => FWD_DST_MAC_IN(3 * 48 - 1 downto 2 * 48),
FWD_DST_IP_IN => FWD_DST_IP_IN(3 * 32 - 1 downto 2 * 32),
FWD_DST_UDP_IN => FWD_DST_UDP_IN(3 * 16 - 1 downto 2 * 16),
CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
+CFG_IP_IN => fxd_ip_l1,
+
FWD_DST_MAC_IN => FWD_DST_MAC_IN(2 * 48 - 1 downto 1 * 48),
FWD_DST_IP_IN => FWD_DST_IP_IN(2 * 32 - 1 downto 1 * 32),
FWD_DST_UDP_IN => FWD_DST_UDP_IN(2 * 16 - 1 downto 1 * 16),
CFG_AUTO_THROTTLE_IN => cfg_autothrottle,
CFG_THROTTLE_PAUSE_IN => cfg_throttle_pause,
+CFG_IP_IN => fxd_ip_l0,
+
FWD_DST_MAC_IN => FWD_DST_MAC_IN(1 * 48 - 1 downto 0 * 48),
FWD_DST_IP_IN => FWD_DST_IP_IN(1 * 32 - 1 downto 0 * 32),
FWD_DST_UDP_IN => FWD_DST_UDP_IN(1 * 16 - 1 downto 0 * 16),
);
end generate dummy_ipu_gen;
+ process(CLK_SYS_IN)
+ begin
+ if rising_edge(CLK_SYS_IN) then
+ if (FORCE_IP_L0_IN /= x"0000_0000") then
+ fxd_ip_l0 <= FORCE_IP_L0_IN;
+ else
+ fxd_ip_l0 <= cfg_ip_l0;
+ end if;
+ end if;
+ end process;
+
+ process(CLK_SYS_IN)
+ begin
+ if rising_edge(CLK_SYS_IN) then
+ if (FORCE_IP_L1_IN /= x"0000_0000") then
+ fxd_ip_l1 <= FORCE_IP_L1_IN;
+ else
+ fxd_ip_l1 <= cfg_ip_l1;
+ end if;
+ end if;
+ end process;
+
+ process(CLK_SYS_IN)
+ begin
+ if rising_edge(CLK_SYS_IN) then
+ if (FORCE_IP_L2_IN /= x"0000_0000") then
+ fxd_ip_l2 <= FORCE_IP_L2_IN;
+ else
+ fxd_ip_l2 <= cfg_ip_l2;
+ end if;
+ end if;
+ end process;
+
+ process(CLK_SYS_IN)
+ begin
+ if rising_edge(CLK_SYS_IN) then
+ if (FORCE_IP_L3_IN /= x"0000_0000") then
+ fxd_ip_l3 <= FORCE_IP_L3_IN;
+ else
+ fxd_ip_l3 <= cfg_ip_l3;
+ end if;
+ end if;
+ end process;
+
setup_imp_gen : if (DO_SIMULATION = 0) generate
SETUP : gbe_setup
port map(
GBE_MAX_SINGLE_SUB_OUT => cfg_max_single_sub,
GBE_AUTOTHROTTLE_OUT => cfg_autothrottle,
GBE_THROTTLE_PAUSE_OUT => cfg_throttle_pause,
+
+ GBE_IP_L0_OUT => cfg_ip_l0,
+ GBE_IP_L1_OUT => cfg_ip_l1,
+ GBE_IP_L2_OUT => cfg_ip_l2,
+ GBE_IP_L3_OUT => cfg_ip_l3,
+
MONITOR_RX_BYTES_IN => sum_rx_bytes,
MONITOR_RX_FRAMES_IN => sum_rx_frames,
MONITOR_TX_BYTES_IN => sum_tx_bytes,
cfg_max_single_sub <= x"fff0";
cfg_throttle_pause <= x"0000";
+ cfg_ip_l0 <= (others => '0');
+ cfg_ip_l1 <= (others => '0');
+ cfg_ip_l2 <= (others => '0');
+ cfg_ip_l3 <= (others => '0');
+
end generate;
NOSCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL = "0000") generate
CFG_AUTO_THROTTLE_IN : in std_logic;
CFG_THROTTLE_PAUSE_IN : in std_logic_vector(15 downto 0);
+ CFG_IP_IN : in std_logic_vector(31 downto 0);
+
MAKE_RESET_OUT : out std_logic;
-- Forwarder
CFG_MAX_REPLY_SIZE_IN => CFG_MAX_REPLY_SIZE_IN,
CFG_AUTO_THROTTLE_IN => CFG_AUTO_THROTTLE_IN,
CFG_THROTTLE_PAUSE_IN => CFG_THROTTLE_PAUSE_IN,
+ CFG_IP_IN => CFG_IP_IN,
FWD_DST_MAC_IN => FWD_DST_MAC_IN,
FWD_DST_IP_IN => FWD_DST_IP_IN,
link_next_state <= INACTIVE;
else
if (wait_ctr = x"0000_1000") then
- if (incl_dhcp = '1') then
- link_next_state <= GET_ADDRESS;
- else
+ --if (incl_dhcp = '1') then
+ -- link_next_state <= GET_ADDRESS;
+ --else
link_next_state <= ACTIVE;
- end if;
+ --end if;
else
link_next_state <= WAIT_FOR_BOOT;
end if;
-- link_ok <= '0';
-- end if;
- if (link_current_state = GET_ADDRESS) then
+ --if (link_current_state = GET_ADDRESS) then
+ if (incl_dhcp = '1') then
dhcp_start <= '1';
else
dhcp_start <= '0';
CFG_MAX_REPLY_SIZE_IN : in std_logic_vector(31 downto 0);
CFG_AUTO_THROTTLE_IN : in std_logic;
CFG_THROTTLE_PAUSE_IN : in std_logic_vector(15 downto 0);
+ CFG_IP_IN : in std_logic_vector(31 downto 0);
-- Forwarder
FWD_DST_MAC_IN : in std_logic_vector(47 downto 0);
-- END OF INTERFACE
MY_IP_OUT => my_ip,
+ CFG_IP_IN => CFG_IP_IN,
DHCP_START_IN => DHCP_START_IN,
DHCP_DONE_OUT => DHCP_DONE_OUT,
DEBUG_OUT => MONITOR_SELECT_GEN_DBG_OUT(2 * 64 - 1 downto 1 * 64) --PROTOS_DEBUG_OUT(1 * 32 - 1 downto 0 * 32)
GBE_MAX_QUEUE_OUT : out std_logic_vector(15 downto 0);
GBE_MAX_SUBS_IN_QUEUE_OUT : out std_logic_vector(15 downto 0);
GBE_MAX_SINGLE_SUB_OUT : out std_logic_vector(15 downto 0);
+
+ GBE_IP_L0_OUT : out std_logic_vector(31 downto 0);
+ GBE_IP_L1_OUT : out std_logic_vector(31 downto 0);
+ GBE_IP_L2_OUT : out std_logic_vector(31 downto 0);
+ GBE_IP_L3_OUT : out std_logic_vector(31 downto 0);
MONITOR_RX_BYTES_IN : in std_logic_vector(31 downto 0);
MONITOR_RX_FRAMES_IN : in std_logic_vector(31 downto 0);
signal dummy_mode : std_logic;
signal autothrottle : std_logic;
signal throttle_pause : std_logic_vector(15 downto 0);
+
+signal ip_l0 : std_logic_vector(31 downto 0);
+signal ip_l1 : std_logic_vector(31 downto 0);
+signal ip_l2 : std_logic_vector(31 downto 0);
+signal ip_l3 : std_logic_vector(31 downto 0);
begin
DUMMY_TRIGGERED_MODE_OUT <= dummy_mode;
GBE_AUTOTHROTTLE_OUT <= autothrottle;
GBE_THROTTLE_PAUSE_OUT <= throttle_pause;
+ GBE_IP_L0_OUT <= ip_l0;
+ GBE_IP_L1_OUT <= ip_l1;
+ GBE_IP_L2_OUT <= ip_l2;
+ GBE_IP_L3_OUT <= ip_l3;
end if;
end process OUT_PROC;
dummy_mode <= '0';
autothrottle <= '0';
throttle_pause <= x"0000";
+ ip_l0 <= x"0000_0000";
+ ip_l1 <= x"0000_0000";
+ ip_l2 <= x"0000_0000";
+ ip_l3 <= x"0000_0000";
elsif (BUS_WRITE_EN_IN = '1') then
when x"14" =>
autothrottle <= BUS_DATA_IN(0);
throttle_pause <= BUS_DATA_IN(31 downto 16);
+
+
+ when x"15" =>
+ ip_l0 <= BUS_DATA_IN;
+ when x"16" =>
+ ip_l1 <= BUS_DATA_IN;
+ when x"17" =>
+ ip_l2 <= BUS_DATA_IN;
+ when x"18" =>
+ ip_l3 <= BUS_DATA_IN;
+
when x"ff" =>
dummy_mode <= dummy_mode;
autothrottle <= autothrottle;
throttle_pause <= throttle_pause;
+ ip_l0 <= ip_l0;
+ ip_l1 <= ip_l1;
+ ip_l2 <= ip_l2;
+ ip_l3 <= ip_l3;
end case;
else
reset_values <= '0';
when 20 =>
data_out(0) <= autothrottle;
data_out(31 downto 16) <= throttle_pause;
+
+ when 21 => data_out <= ip_l0;
+ when 22 => data_out <= ip_l1;
+ when 23 => data_out <= ip_l2;
+ when 24 => data_out <= ip_l3;
-- Histogram of sctrl data sizes
when 96 to 127 =>
GBE_AUTOTHROTTLE_OUT : out std_logic;
GBE_THROTTLE_PAUSE_OUT : out std_logic_vector(15 downto 0);
+
+ GBE_IP_L0_OUT : out std_logic_vector(31 downto 0);
+ GBE_IP_L1_OUT : out std_logic_vector(31 downto 0);
+ GBE_IP_L2_OUT : out std_logic_vector(31 downto 0);
+ GBE_IP_L3_OUT : out std_logic_vector(31 downto 0);
MONITOR_RX_BYTES_IN : in std_logic_vector(31 downto 0);
MONITOR_RX_FRAMES_IN : in std_logic_vector(31 downto 0);
-- END OF INTERFACE
MY_IP_OUT : out std_logic_vector(31 downto 0);
+ CFG_IP_IN : in std_logic_vector(31 downto 0);
DHCP_START_IN : in std_logic;
DHCP_DONE_OUT : out std_logic;
-- debug
SENT_FRAMES_OUT : out std_logic_vector(15 downto 0);
-- END OF INTERFACE
- MY_IP_OUT : out std_logic_vector(31 downto 0);
+ MY_IP_OUT : out std_logic_vector(31 downto 0);
+ CFG_IP_IN : in std_logic_vector(31 downto 0);
DHCP_START_IN : in std_logic;
DHCP_DONE_OUT : out std_logic;
--*****************
-- setting of global variable for IP address
--g_MY_IP <= saved_true_ip when main_current_state = ESTABLISHED else (others => '0');
-my_ip <= saved_true_ip when main_current_state = ESTABLISHED else (others => '0');
+
+process(CLK)
+begin
+ if rising_edge(CLK) then
+ if (main_current_state = ESTABLISHED) then
+ my_ip(31 downto 24) <= saved_true_ip(7 downto 0);
+ my_ip(23 downto 16) <= saved_true_ip(15 downto 8);
+ my_ip(15 downto 8) <= saved_true_ip(23 downto 16);
+ my_ip(7 downto 0) <= saved_true_ip(31 downto 24);
+ elsif (CFG_IP_IN /= x"0000_0000") then
+ my_ip(31 downto 24) <= CFG_IP_IN(7 downto 0);
+ my_ip(23 downto 16) <= CFG_IP_IN(15 downto 8);
+ my_ip(15 downto 8) <= CFG_IP_IN(23 downto 16);
+ my_ip(7 downto 0) <= CFG_IP_IN(31 downto 24);
+ else
+ my_ip <= x"0a0a_0a0a";
+ end if;
+ end if;
+end process;
+--my_ip <= saved_true_ip when main_current_state = ESTABLISHED else (others => '0');
+
MY_IP_OUT <= my_ip;
--
--*****************