fixed link breakdown in reset due to (2n+1) K_NULL to being sent

diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
index 6b7aa5d537475cdc255bd547e9ef502652dbfe97..1ca036699d19c8215c2baa436d9bc93ec3687d53 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd
@@ -77,7 +77,6 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is
 
   signal tx_data            : std_logic_vector(4*8-1 downto 0);
   signal tx_k               : std_logic_vector(3 downto 0);
-  signal tx_cd              : std_logic_vector(3 downto 0);  
   signal rx_data            : std_logic_vector(4*8-1 downto 0);
   signal rx_k               : std_logic_vector(3 downto 0);
   signal rx_error           : std_logic_vector(3 downto 0);
@@ -117,8 +116,6 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is
   type u8_arr is array (0 to 3) of unsigned(7 downto 0);
   signal cv_cnt, cv_cnt_sys : u8_arr;
 
-  signal tx_ref_clk_i       : std_logic;
-
   signal powerup_ch         : std_logic_vector(3 downto 0);
   signal link_rx_ready_i    : std_logic_vector(3 downto 0);
   signal link_rx_null_i     : std_logic_vector(3 downto 0);
@@ -130,9 +127,11 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is
   signal rx_dlm_i           : std_logic_vector(3 downto 0);
   signal tx_rst_i           : std_logic_vector(3 downto 0);
 
-  signal pll_lol_i          : std_logic;
+  signal lb_sel_i           : std_logic_vector(3 downto 0);
+  signal lb_start_i         : std_logic;
+  signal lb_start_qsys      : std_logic;
   
-  signal quad_mode : integer range 0 to 100;
+  signal quad_mode          : integer range 0 to 100;
 
 begin
 
@@ -167,10 +166,10 @@ begin
 -- TX ref clock
 -- output only if a slave port is available in QUAD
 -------------------------------------------------
-  MASTER_CLK_OUT <= clk_rx_full(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE))  else
-                    clk_rx_full(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE))  else
-                    clk_rx_full(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE))  else
-                    clk_rx_full(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE))  else
+  MASTER_CLK_OUT <= clk_rx_full(0) when (IS_MODE(0) = c_IS_SLAVE)  else
+                    clk_rx_full(1) when (IS_MODE(1) = c_IS_SLAVE)  else
+                    clk_rx_full(2) when (IS_MODE(2) = c_IS_SLAVE)  else
+                    clk_rx_full(3) when (IS_MODE(3) = c_IS_SLAVE)  else
                     '0';
 
 -------------------------------------------------
@@ -190,10 +189,10 @@ begin
 -------------------------------------------------
 -- stable RX recovered clock available
 -------------------------------------------------      
-  TX_CLK_AVAIL_OUT <= link_rx_ready_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else
-                      link_rx_ready_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else
-                      link_rx_ready_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else
-                      link_rx_ready_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else
+  TX_CLK_AVAIL_OUT <= link_rx_ready_i(0) when (IS_MODE(0) = c_IS_SLAVE) else
+                      link_rx_ready_i(1) when (IS_MODE(1) = c_IS_SLAVE) else
+                      link_rx_ready_i(2) when (IS_MODE(2) = c_IS_SLAVE) else
+                      link_rx_ready_i(3) when (IS_MODE(3) = c_IS_SLAVE) else
                       '1';
   
 -------------------------------------------------      
@@ -216,16 +215,16 @@ begin
 -- reset komma receive
 -- output only if a slave port is available in QUAD
 -------------------------------------------------      
-  RX_RST_OUT <= rx_rst_i(0) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else
-                rx_rst_i(1) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else
-                rx_rst_i(2) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else
-                rx_rst_i(3) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else
+  RX_RST_OUT <= rx_rst_i(0) when (IS_MODE(0) = c_IS_SLAVE) else
+                rx_rst_i(1) when (IS_MODE(1) = c_IS_SLAVE) else
+                rx_rst_i(2) when (IS_MODE(2) = c_IS_SLAVE) else
+                rx_rst_i(3) when (IS_MODE(3) = c_IS_SLAVE) else
                 '0';
 
-  RX_RST_WORD_OUT <= rx_rst_word_i(0*8+7 downto 0*8) when ((quad_mode >= 8) and (IS_MODE(0) = c_IS_SLAVE)) else
-                     rx_rst_word_i(1*8+7 downto 1*8) when ((quad_mode >= 8) and (IS_MODE(1) = c_IS_SLAVE)) else
-                     rx_rst_word_i(2*8+7 downto 2*8) when ((quad_mode >= 8) and (IS_MODE(2) = c_IS_SLAVE)) else
-                     rx_rst_word_i(3*8+7 downto 3*8) when ((quad_mode >= 8) and (IS_MODE(3) = c_IS_SLAVE)) else
+  RX_RST_WORD_OUT <= rx_rst_word_i(0*8+7 downto 0*8) when (IS_MODE(0) = c_IS_SLAVE) else
+                     rx_rst_word_i(1*8+7 downto 1*8) when (IS_MODE(1) = c_IS_SLAVE) else
+                     rx_rst_word_i(2*8+7 downto 2*8) when (IS_MODE(2) = c_IS_SLAVE) else
+                     rx_rst_word_i(3*8+7 downto 3*8) when (IS_MODE(3) = c_IS_SLAVE) else
                      x"00";
 
 -------------------------------------------------      
@@ -244,9 +243,33 @@ begin
   wap_requested_i(2*4+3 downto 2*4) <= WAP_REQUESTED_IN when (IS_MODE(2) = c_IS_MASTER) else x"0";
   wap_requested_i(3*4+3 downto 3*4) <= WAP_REQUESTED_IN when (IS_MODE(3) = c_IS_MASTER) else x"0";
 
--------------------------------------------------      
+-------------------------------------------------
+-- loopback select
+-------------------------------------------------
+  lb_sel_i(0) <= '1' when (IS_MODE(0) = c_IS_SLAVE) else '0';
+  lb_sel_i(1) <= '1' when (IS_MODE(1) = c_IS_SLAVE) else '0';
+  lb_sel_i(2) <= '1' when (IS_MODE(2) = c_IS_SLAVE) else '0';
+  lb_sel_i(3) <= '1' when (IS_MODE(3) = c_IS_SLAVE) else '0';
+
+  lb_start_i  <= rx_rst_i(0) when (IS_MODE(0) = c_IS_SLAVE) else
+                 rx_rst_i(1) when (IS_MODE(1) = c_IS_SLAVE) else
+                 rx_rst_i(2) when (IS_MODE(2) = c_IS_SLAVE) else
+                 rx_rst_i(3) when (IS_MODE(3) = c_IS_SLAVE) else
+                 '0';
+
+  THE_LB_START_SYNC: entity pulse_sync
+  port map(
+    CLK_A_IN        => MASTER_CLK_IN,
+    RESET_A_IN      => '0',
+    PULSE_A_IN      => lb_start_i,
+    CLK_B_IN        => SYSCLK,
+    RESET_B_IN      => '0',
+    PULSE_B_OUT     => lb_start_qsys
+  );
+         
+-------------------------------------------------
 -- Serdes
--------------------------------------------------     
+-------------------------------------------------
 gen_SERDES: if LINK_SPEED = 125 generate
   THE_SERDES: entity work.serdes_sync_all_125M_RS
     port map(
@@ -650,6 +673,9 @@ end generate;
       -- WAP
       WA_POS_OUT  => wa_position_i,
       WA_REQ_IN   => wap_req_all_q(2),
+      -- Loopback hack
+      LB_START_IN => '0', --lb_start_qsys,
+      LB_SEL_IN   => (others => '0'), --lb_sel_i,
       --Slowcontrol
       BUS_RX      => BUS_RX,
       BUS_TX      => BUS_TX,

diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd
index 880c3a588c1f6a6b72eb71a500eeb9c69d651b1e..0f7c652057d20c9235f592b87776202dcb02b50f 100644 (file)
--- a/media_interfaces/sync/med_sync_control_RS.vhd
+++ b/media_interfaces/sync/med_sync_control_RS.vhd
@@ -77,8 +77,6 @@ architecture med_sync_control_arch of med_sync_control_RS is
   signal reset_i                  : std_logic;
   signal link_tx_ready_i          : std_logic;
   signal link_rx_ready_i          : std_logic;
-  signal link_half_done_i         : std_logic;
-  signal link_full_done_i         : std_logic;
 
   signal media_med2int_i          : MED2INT;
 

diff --git a/media_interfaces/sync/rx_control_RS.vhd b/media_interfaces/sync/rx_control_RS.vhd
index 4852d4650253e8cff81dde9a27f78e0d632fe89f..bedea8cfa3e46c4f3e5d38aaf07c935fcf941251 100644 (file)
--- a/media_interfaces/sync/rx_control_RS.vhd
+++ b/media_interfaces/sync/rx_control_RS.vhd
@@ -78,6 +78,7 @@ architecture rx_control_arch of rx_control_RS is
   signal ctr_idle0           : unsigned(8 downto 0);\r
   signal idle0_detected      : std_logic;\r
 \r
+  signal link_rx_null_i      : std_logic;\r
   signal link_active_i       : std_logic;\r
   signal link_active_qrx     : std_logic;\r
   signal link_active_qsys    : std_logic;\r
@@ -179,6 +180,7 @@ begin
     sync_k_i                <= '0';\r
     ce_idle0_ctr            <= '0';\r
     rst_idle0_ctr           <= '0';\r
+    link_rx_null_i          <= '0';\r
 \r
     case rx_state is\r
       when SLEEP =>\r
@@ -186,6 +188,7 @@ begin
         rx_state_bits         <= x"1";\r
         rx_data(7 downto 0)   <= reg_rx_data_in;\r
         rst_idle0_ctr         <= '1';\r
+        link_rx_null_i        <= '1';\r
         if( (reg_rx_k_in = '1') and (reg_rx_data_in = K_IDLE) and (link_rx_ready_qrx = '1') ) then\r
           rx_state            <= WAIT_1;\r
           sync_k_i            <= '1';\r
@@ -306,6 +309,8 @@ begin
   \r
   LINK_ACTIVE_OUT    <= link_active_qrx;\r
   \r
+  LINK_RX_NULL_OUT   <= link_rx_null_i;\r
+  \r
 ----------------------------------------------------------------------\r
 -- Debug and Status\r
 ---------------------------------------------------------------------- \r

diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd
index 022cc7fb803ccfcf01a9eb2168591f15a4c197b9..980da1781f76afb6b0438d342e428b182f2b9046 100644 (file)
--- a/media_interfaces/sync/sci_reader_RS.vhd
+++ b/media_interfaces/sync/sci_reader_RS.vhd
@@ -23,6 +23,9 @@ entity sci_reader_RS is
     -- WAP stuff
     WA_POS_OUT       : out std_logic_vector(15 downto 0);
     WA_REQ_IN        : in  std_logic;
+    -- Loopback hack
+    LB_START_IN      : in  std_logic;
+    LB_SEL_IN        : in  std_logic_vector(3 downto 0);
     --Slowcontrol
     BUS_RX           : in  CTRLBUS_RX;
     BUS_TX           : out CTRLBUS_TX;    
@@ -34,6 +37,8 @@ end entity;
 
 architecture sci_reader_arch of sci_reader_RS is
 
+--type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH,
+--                  W_RL, W_RL_WAIT, W_RL_WAIT2, W_RL_FINISH, W_RLS, W_RLS_WAIT, W_RLS_WAIT2, W_RLS_FINISH);
 type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
 
 signal sci_state         : sci_ctrl;
@@ -84,6 +89,9 @@ begin
         elsif( (sci_timer(sci_timer'left) = '1') and (WA_REQ_IN = '1') ) then
           sci_timer     <= (others => '0');
           sci_state     <= GET_WA;
+--        elsif( LB_START_IN = '1' ) then
+--          sci_state     <= W_RL;
+--          next_sci_wr   <= '1';
         end if;      
       when SCTRL =>
         if( sci_reg_i = '1' ) then
@@ -103,9 +111,43 @@ begin
       when SCTRL_FINISH =>
         BUS_TX.data(7 downto 0) <= SCI_RDDATA;
         BUS_TX.ack      <= '1';
---        next_sci_wr     <= '0';
         SCI_RD          <= '0';
         sci_state       <= IDLE;
+
+      ----------------------------------------
+      ----------------------------------------
+--      when W_RL =>
+--        SCI_SEL         <= '0' & LB_SEL_IN; 
+--        SCI_ADDR        <= b"010001"; -- x"11" for ECP3
+--        SCI_WRDATA      <= x"21"; -- set source of TX data
+--        SCI_RD          <= '0';
+--        sci_state       <= W_RL_WAIT;
+--      when W_RL_WAIT =>
+--        next_sci_wr     <= '0';
+--        sci_state       <= W_RL_WAIT2;
+--      when W_RL_WAIT2 =>
+--        sci_state       <= W_RL_FINISH;
+--      when W_RL_FINISH =>
+--        next_sci_wr     <= '1';
+--        sci_state       <= W_RLS;
+--      when W_RLS =>
+--        SCI_ADDR        <= b"010100"; -- x"14" for ECP3
+--        SCI_WRDATA      <= x"69"; -- enable feedback
+--        SCI_RD          <= '0';
+--        sci_state       <= W_RLS_WAIT;
+--      when W_RLS_WAIT =>
+--        next_sci_wr     <= '0';
+--        sci_state       <= W_RLS_WAIT2;
+--      when W_RLS_WAIT2 =>
+--        sci_state       <= W_RLS_FINISH;
+--      when W_RLS_FINISH =>
+--        SCI_SEL         <= (others => '0');
+--        SCI_ADDR        <= (others => '0');
+--        SCI_WRDATA      <= (others => '0');
+--        sci_state       <= IDLE;
+      ----------------------------------------
+      ----------------------------------------
+      
       when GET_WA =>
         if( ((cnt = 4) and (FPGA_TYPE = 3)) or ((cnt = 2) and (FPGA_TYPE = 5)) ) then
           cnt           := 0;

diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd
index 0b8d056b2eebf2b4e4726e1a1db656467e3e1126..898f8464d927f3593167872f457b3d3538a627d2 100644 (file)
--- a/media_interfaces/sync/tx_control_RS.vhd
+++ b/media_interfaces/sync/tx_control_RS.vhd
@@ -42,7 +42,7 @@ end entity;
 architecture arch of tx_control_RS is\r
 \r
   type state_t is (IDLE, SEND_IDLE_L, SEND_IDLE_H, SEND_DATA_L, SEND_DATA_H, \r
-                   SEND_DLM_L, SEND_DLM_H, SEND_RST_L, SEND_RST_H);\r
+                   SEND_DLM_L, SEND_DLM_H, SEND_RST_L, SEND_RST_H, SEND_NULL_L, SEND_NULL_H);\r
   signal current_state           : state_t;\r
   signal state_bits              : std_logic_vector(3 downto 0);\r
   \r
@@ -296,19 +296,32 @@ begin
             current_state     <= SEND_RST_H;\r
             debug_sending_rst <= '1';\r
 \r
-           when SEND_RST_H =>\r
+          when SEND_RST_H =>\r
             word_sync_i <= '1';\r
             tx_data_i   <= send_rst_word_i;\r
 \r
+          when SEND_NULL_L =>\r
+            tx_data_i     <= K_NULL;\r
+            tx_k_i        <= '1';\r
+            current_state <= SEND_NULL_H;\r
+            \r
+          when SEND_NULL_H =>\r
+            word_sync_i <= '1';\r
+            tx_data_i   <= K_NULL;\r
+            tx_k_i      <= '1'; -- EXCEPTION\r
+          \r
           when others =>\r
             current_state <= SEND_IDLE_L;\r
 \r
         end case;\r
 \r
         if( (current_state = SEND_IDLE_H) or (current_state = SEND_DATA_H) or\r
-                      (current_state = SEND_DLM_H)  or (current_state = SEND_RST_H) ) then\r
-          if   ( (link_tx_ready_qtx = '0') or (link_tx_null_qtx = '1') ) then\r
+                      (current_state = SEND_DLM_H) or (current_state = SEND_RST_H) or (current_state = SEND_NULL_H)) then\r
+--          if   ( (link_tx_ready_qtx = '0') or (link_tx_null_qtx = '1') ) then\r
+          if   ( link_tx_ready_qtx = '0' ) then\r
             current_state     <= IDLE;\r
+          elsif( link_tx_null_qtx = '1' ) then\r
+            current_state     <= SEND_NULL_L;\r
           elsif( send_dlm_i = '1' ) then\r
             current_state     <= SEND_DLM_L;\r
           elsif( send_rst_i = '1' ) then\r
@@ -322,19 +335,24 @@ begin
         end if;\r
       end if;\r
     end if;\r
+  end process THE_DATA_CONTROL_FSM;\r
 \r
+  THE_DATA_CONTROL_ASYNC: process( current_state, ram_empty, link_active_qtx, send_dlm_i, send_rst_i, link_tx_null_qtx, CLEAR ) \r
+  begin\r
     --async because of oreg.\r
-    if ((current_state = SEND_IDLE_H) or (current_state = SEND_DATA_H) or (current_state = SEND_DLM_H) or (current_state = SEND_RST_H)) \r
-         and (ram_empty = '0') and (link_active_qtx = '1') and (send_dlm_i = '0') and (send_rst_i = '0') then\r
+    -- read from RAM if the NEXT state will be "send data"\r
+    if ((current_state = SEND_IDLE_H) or (current_state = SEND_DATA_H) or \r
+                   (current_state = SEND_DLM_H) or (current_state = SEND_RST_H) or (current_state = SEND_NULL_H))\r
+         and (ram_empty = '0') and (link_active_qtx = '1') and (send_dlm_i = '0') and (send_rst_i = '0') and (link_tx_null_qtx = '0') then\r
       ram_read <= '1';\r
     else \r
       ram_read <= '0';\r
     end if;\r
-    if (CLEAR = '1') then\r
+    if( CLEAR = '1' ) then\r
       ram_read <= '0';\r
     end if;\r
 \r
-  end process THE_DATA_CONTROL_FSM;\r
+  end process THE_DATA_CONTROL_ASYNC;\r
 \r
 ----------------------------------------------------------------------\r
 --\r