updates to sync media interface for dirich modules

diff --git a/media_interfaces/ecp3_sfp/serdes_sync_3.ipx b/media_interfaces/ecp3_sfp/serdes_sync_3.ipx
index 25ef4138646ad0192a7edaf387a829bb38e8fc76..bc6c9e7442d94069606bd1a945f297da8cbd5deb 100644 (file)
--- a/media_interfaces/ecp3_sfp/serdes_sync_3.ipx
+++ b/media_interfaces/ecp3_sfp/serdes_sync_3.ipx
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_3" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2015 07 13 11:27:08.351" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_3" module="PCS" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2016 06 09 17:16:34.159" version="8.2" type="Module" synthesis="synplify" source_format="VHDL">
   <Package>
-               <File name="serdes_sync_3.lpc" type="lpc" modified="2015 07 13 11:27:01.000"/>
-               <File name="serdes_sync_3.pp" type="pp" modified="2015 07 13 11:27:01.000"/>
-               <File name="serdes_sync_3.sym" type="sym" modified="2015 07 13 11:27:02.000"/>
-               <File name="serdes_sync_3.tft" type="tft" modified="2015 07 13 11:27:01.000"/>
-               <File name="serdes_sync_3.txt" type="pcs_module" modified="2015 07 13 11:27:01.000"/>
-               <File name="serdes_sync_3.vhd" type="top_level_vhdl" modified="2015 07 13 11:27:01.000"/>
+               <File name="serdes_sync_3.lpc" type="lpc" modified="2016 06 09 17:16:31.000"/>
+               <File name="serdes_sync_3.pp" type="pp" modified="2016 06 09 17:16:31.000"/>
+               <File name="serdes_sync_3.sym" type="sym" modified="2016 06 09 17:16:31.000"/>
+               <File name="serdes_sync_3.tft" type="tft" modified="2016 06 09 17:16:31.000"/>
+               <File name="serdes_sync_3.txt" type="pcs_module" modified="2016 06 09 17:16:31.000"/>
+               <File name="serdes_sync_3.vhd" type="top_level_vhdl" modified="2016 06 09 17:16:31.000"/>
   </Package>
 </DiamondModule>

diff --git a/media_interfaces/ecp3_sfp/serdes_sync_3.lpc b/media_interfaces/ecp3_sfp/serdes_sync_3.lpc
index 9218950e63381c1963690b4c7d8d356edf8bc200..f93a954f393977e5ec64b037a26aa5c44a869772 100644 (file)
--- a/media_interfaces/ecp3_sfp/serdes_sync_3.lpc
+++ b/media_interfaces/ecp3_sfp/serdes_sync_3.lpc
@@ -1,8 +1,8 @@
 [Device]
 Family=latticeecp3
 PartType=LFE3-150EA
-PartName=LFE3-150EA-6FN1156C
-SpeedGrade=6
+PartName=LFE3-150EA-8FN1156C
+SpeedGrade=8
 Package=FPBGA1156
 OperatingCondition=COM
 Status=P
@@ -16,8 +16,8 @@ CoreRevision=8.2
 ModuleName=serdes_sync_3
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=07/13/2015
-Time=11:27:01
+Date=06/09/2016
+Time=17:16:31
 
 [Parameters]
 Verilog=0
@@ -58,7 +58,7 @@ _tx_data_width3=8
 _tx_fifo0=DISABLED
 _tx_fifo1=ENABLED
 _tx_fifo2=ENABLED
-_tx_fifo3=DISABLED
+_tx_fifo3=ENABLED
 _tx_ficlk_rate0=200
 _tx_ficlk_rate1=200
 _tx_ficlk_rate2=200

diff --git a/media_interfaces/ecp3_sfp/serdes_sync_3.txt b/media_interfaces/ecp3_sfp/serdes_sync_3.txt
index 9ba59876b0f0893750ecfcc973bdfa8aaa930b8f..637bc0ac9b41318fa67679f9720210d31535fd2f 100644 (file)
--- a/media_interfaces/ecp3_sfp/serdes_sync_3.txt
+++ b/media_interfaces/ecp3_sfp/serdes_sync_3.txt
@@ -19,7 +19,7 @@ CH3_RX_DATA_RATE        "FULL"
 CH3_TX_DATA_RATE        "FULL"
 CH3_TX_DATA_WIDTH       "8"
 CH3_RX_DATA_WIDTH        "8"
-CH3_TX_FIFO       "DISABLED"
+CH3_TX_FIFO       "ENABLED"
 CH3_RX_FIFO        "DISABLED"
 CH3_TDRV      "0"
 #CH3_TX_FICLK_RATE      200

diff --git a/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.cst b/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.cst
deleted file mode 100644 (file)
index d7c6234..0000000
--- a/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.cst
+++ /dev/null
@@ -1,3 +0,0 @@
-Date=01/04/2016
-Time=14:14:21
-

diff --git a/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.lpc b/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.lpc
index 82b9eaeb9614b3da40ee74d90358b0faca5b5ce8..ae65b70c9ef719fcfc9f526cb1db83ac0ba3d895 100644 (file)
--- a/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.lpc
+++ b/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.lpc
@@ -11,11 +11,11 @@ CoreName=PCS
 CoreRevision=8.2
 CoreStatus=Demo
 CoreType=LPM
-Date=01/04/2016
+Date=06/20/2016
 ModuleName=serdes_sync_0
 ParameterFileVersion=1.0
 SourceFormat=vhdl
-Time=14:14:21
+Time=14:03:36
 VendorName=Lattice Semiconductor Corporation
 [Parameters]
 ;ACHARA=0 00H
@@ -23,7 +23,7 @@ VendorName=Lattice Semiconductor Corporation
 ;ACHARM=0 00H
 ;RXMCAENABLE=Disabled
 CDRLOLACTION=Full Recalibration
-CDRLOLRANGE=0
+CDRLOLRANGE=3
 CDR_MAX_RATE=2
 CDR_MULT=10X
 CDR_REF_RATE=200.0000
@@ -50,7 +50,7 @@ RX8B10B=Enabled
 RXCOMMAA=1100000100
 RXCOMMAB=0011111000
 RXCOMMAM=1111111100
-RXCOUPLING=DC
+RXCOUPLING=AC
 RXCTC=Disabled
 RXCTCBYTEN=0 00H
 RXCTCBYTEN1=0 00H

diff --git a/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.sbx b/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.sbx
index 8011d197b7cd73e5de76e75006b9e4a681d3aa1d..d436362c4cc97fd154a3d2e0ff3b76e378de13aa 100644 (file)
--- a/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.sbx
+++ b/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.sbx
@@ -53,8 +53,8 @@
             <lattice:device>LFE5UM-85F-8BG381C</lattice:device>
             <lattice:synthesis>synplify</lattice:synthesis>
             <lattice:date>2016-01-04.02:14:28 PM</lattice:date>
-            <lattice:modified>2016-01-04.02:14:28 PM</lattice:modified>
-            <lattice:diamond>3.6.0.83.4</lattice:diamond>
+            <lattice:modified>2016-06-20.02:03:40 PM</lattice:modified>
+            <lattice:diamond>3.7.1.502</lattice:diamond>
             <lattice:language>VHDL</lattice:language>
             <lattice:attributes>
                 <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
@@ -133,7 +133,7 @@
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>Date</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">01/04/2016</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">06/20/2016</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>ModuleName</lattice:lpckey>
@@ -149,7 +149,7 @@
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>Time</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">14:14:21</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">14:03:36</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>VendorName</lattice:lpckey>
@@ -178,7 +178,7 @@
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>CDRLOLRANGE</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">3</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>CDR_MAX_RATE</lattice:lpckey>
@@ -286,7 +286,7 @@
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>RXCOUPLING</lattice:lpckey>
-                    <lattice:lpcvalue lattice:resolve="constant">DC</lattice:lpcvalue>
+                    <lattice:lpcvalue lattice:resolve="constant">AC</lattice:lpcvalue>
                 </lattice:lpcentry>
                 <lattice:lpcentry>
                     <lattice:lpckey>RXCTC</lattice:lpckey>

diff --git a/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.vhd b/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.vhd
index 175f81eb89745843cf19891f49b237fd73b021c9..1004ff65dfa8aa4f1b38b6468efa9f37c6049f46 100644 (file)
--- a/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.vhd
+++ b/media_interfaces/ecp5/serdes_sync_0/serdes_sync_0.vhd
@@ -80,16 +80,16 @@ architecture v1 of serdes_sync_0 is
             PDIFF_DIV11_VAL_LOCK: integer := 0;
             PDIFF_DIV11_VAL_UNLOCK: integer := 0;
             PPCLK_DIV11_TC: integer := 0);
-        port (sli_rst: in std_logic;   -- /d/jspc29/lattice/diamond/3.6_x64/ispfpga/sa5p00/data/sll_core_template.v(73)
-            sli_refclk: in std_logic;   -- /d/jspc29/lattice/diamond/3.6_x64/ispfpga/sa5p00/data/sll_core_template.v(74)
-            sli_pclk: in std_logic;   -- /d/jspc29/lattice/diamond/3.6_x64/ispfpga/sa5p00/data/sll_core_template.v(75)
-            sli_div2_rate: in std_logic;   -- /d/jspc29/lattice/diamond/3.6_x64/ispfpga/sa5p00/data/sll_core_template.v(76)
-            sli_div11_rate: in std_logic;   -- /d/jspc29/lattice/diamond/3.6_x64/ispfpga/sa5p00/data/sll_core_template.v(77)
-            sli_gear_mode: in std_logic;   -- /d/jspc29/lattice/diamond/3.6_x64/ispfpga/sa5p00/data/sll_core_template.v(78)
-            slo_plol: out std_logic   -- /d/jspc29/lattice/diamond/3.6_x64/ispfpga/sa5p00/data/sll_core_template.v(81)
+        port (sli_rst: in std_logic;   -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/sll_core_template.v(73)
+            sli_refclk: in std_logic;   -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/sll_core_template.v(74)
+            sli_pclk: in std_logic;   -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/sll_core_template.v(75)
+            sli_div2_rate: in std_logic;   -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/sll_core_template.v(76)
+            sli_div11_rate: in std_logic;   -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/sll_core_template.v(77)
+            sli_gear_mode: in std_logic;   -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/sll_core_template.v(78)
+            slo_plol: out std_logic   -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/sll_core_template.v(81)
         );
         
-    end component serdes_sync_0sll_core; -- syn_black_box=1    -- /d/jspc29/lattice/diamond/3.6_x64/ispfpga/sa5p00/data/sll_core_template.v(57)
+    end component serdes_sync_0sll_core; -- syn_black_box=1    -- /d/jspc29/lattice/diamond/3.7_x64/ispfpga/sa5p00/data/sll_core_template.v(57)
     signal n48,n47,n1,n2,n3,n4,rx_pclk_c,tx_pclk_c,n5,n6,n7,n8,n9,
         n10,n11,n12,n13,n14,n15,n16,n17,n18,n19,n20,n21,n22,n23,
         n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,
@@ -108,7 +108,7 @@ begin
     tx_pclk <= tx_pclk_c;
     DCU0_inst: component DCUA generic map (D_MACROPDB=>"0b1",D_IB_PWDNB=>"0b1",
         D_XGE_MODE=>"0b0",D_LOW_MARK=>"0d4",D_HIGH_MARK=>"0d12",D_BUS8BIT_SEL=>"0b0",
-        D_CDR_LOL_SET=>"0b00",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
+        D_CDR_LOL_SET=>"0b11",D_TXPLL_PWDNB=>"0b1",D_BITCLK_LOCAL_EN=>"0b1",
         D_BITCLK_ND_EN=>"0b0",D_BITCLK_FROM_ND_EN=>"0b0",D_SYNC_LOCAL_EN=>"0b1",
         D_SYNC_ND_EN=>"0b0",CH0_UC_MODE=>"0b1",CH0_PCIE_MODE=>"0b0",CH0_RIO_MODE=>"0b0",
         CH0_WA_MODE=>"0b0",CH0_INVERT_RX=>"0b0",CH0_INVERT_TX=>"0b0",CH0_PRBS_SELECTION=>"0b0",
@@ -121,7 +121,7 @@ begin
         CH0_MATCH_4_ENABLE=>"0b1",CH0_MIN_IPG_CNT=>"0b11",CH0_CC_MATCH_1=>"0x1BC",
         CH0_CC_MATCH_2=>"0x11C",CH0_CC_MATCH_3=>"0x11C",CH0_CC_MATCH_4=>"0x11C",
         CH0_UDF_COMMA_MASK=>"0x0ff",CH0_UDF_COMMA_A=>"0x083",CH0_UDF_COMMA_B=>"0x07C",
-        CH0_RX_DCO_CK_DIV=>"0b000",CH0_RCV_DCC_EN=>"0b1",CH0_TPWDNB=>"0b1",
+        CH0_RX_DCO_CK_DIV=>"0b000",CH0_RCV_DCC_EN=>"0b0",CH0_TPWDNB=>"0b1",
         CH0_RATE_MODE_TX=>"0b0",CH0_RTERM_TX=>"0d19",CH0_TX_CM_SEL=>"0b00",
         CH0_TDRV_PRE_EN=>"0b0",CH0_TDRV_SLICE0_SEL=>"0b00",CH0_TDRV_SLICE1_SEL=>"0b00",
         CH0_TDRV_SLICE2_SEL=>"0b01",CH0_TDRV_SLICE3_SEL=>"0b01",CH0_TDRV_SLICE4_SEL=>"0b01",

diff --git a/media_interfaces/med_ecp3_sfp_sync_4.vhd b/media_interfaces/med_ecp3_sfp_sync_4.vhd
index 464459518df8f7aa4255f17390760ccb0964e1e8..5249f009e39694c321b6a1d2d29de230e6f1bbdd 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_4.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_4.vhd
@@ -108,8 +108,8 @@ begin
 
 clk_200_ref <= CLK_REF_FULL;
 
-SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE);   --slave only switches on when RX is ready
-
+-- SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE);   --slave only switches on when RX is ready
+SD_TXDIS_OUT <= (others => RESET);
 -------------------------------------------------      
 -- Serdes
 -------------------------------------------------      

diff --git a/media_interfaces/med_ecp5_sfp_sync.vhd b/media_interfaces/med_ecp5_sfp_sync.vhd
index 73db43eb4028633ff822afe23697fd6e8b5ac8a1..25567397d9b6becf37279fd67d0d060df11b35c3 100644 (file)
--- a/media_interfaces/med_ecp5_sfp_sync.vhd
+++ b/media_interfaces/med_ecp5_sfp_sync.vhd
@@ -107,7 +107,8 @@ begin
 
 clk_200_ref <= CLK_REF_FULL;
 
-SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE);   --slave only switches on when RX is ready
+-- SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE);   --slave only switches on when RX is ready
+SD_TXDIS_OUT <= RESET;
 
 -- gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
 --   clk_200_i        <= clk_rx_full;
@@ -262,7 +263,7 @@ THE_SCI_READER : entity work.sci_reader
 -- STAT_DEBUG(7)            <= '0';
 -- STAT_DEBUG(15 downto 8)  <= stat_fsm_reset_i(7 downto 0);
 -- STAT_DEBUG(15 downto 0) <= debug_tx_control_i(31 downto 16);
-STAT_DEBUG(15 downto 0) <= debug_rx_control_i(15 downto 0);
+STAT_DEBUG(31 downto 0) <= debug_rx_control_i(31 downto 0);
  
 stat_med(0) <= rst_qd; 
 stat_med(1) <= rx_pcs_rst;

diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd
index e5e9c6f8d30e799324674beae8fdfe1552ac8498..c58eef898cb41f75f295eb269078751285df84c3 100644 (file)
--- a/media_interfaces/sync/med_sync_control.vhd
+++ b/media_interfaces/sync/med_sync_control.vhd
@@ -80,6 +80,7 @@ signal got_link_ready_i       : std_logic;
 signal make_link_reset_i      : std_logic;
 signal send_link_reset_i      : std_logic;
 signal make_link_reset_real_i : std_logic := '0';
+signal make_link_reset_sys_i  : std_logic := '0';
 signal send_link_reset_real_i : std_logic := '0';
 
 signal reset_i, rst_n, rst_n_tx : std_logic;
@@ -89,7 +90,7 @@ begin
 
 rst_n_tx  <= not (CLEAR or make_link_reset_real_i);
 rst_n     <= not (CLEAR or sd_los_i or make_link_reset_real_i);
-reset_i   <=     (CLEAR or sd_los_i or make_link_reset_real_i);
+reset_i   <=     (RESET or sd_los_i or make_link_reset_real_i);
 
 
 media_med2int_i.clk_half <= CLK_RXHALF;
@@ -240,8 +241,10 @@ MEDIA_MED2INT <= media_med2int_i;
 -------------------------------------------------   
 led_ok <= rx_allow and tx_allow when rising_edge(CLK_SYS); 
 led_rx <= (media_med2int_i.dataready or led_rx)  and not timer(20) when rising_edge(CLK_SYS);
+-- led_tx <= '1' when DEBUG_TX_CONTROL(13 downto 10) = x"c" else '0'; --
 led_tx <= (MEDIA_INT2MED.dataready or led_tx or sd_los_i)  and not timer(20) when rising_edge(CLK_SYS);
 led_dlm <= (led_dlm or rx_dlm_i) and not timer(20) when rising_edge(CLK_SYS);
+-- led_dlm <= '1' when DEBUG_RX_CONTROL(3 downto 0) = x"f" else '0';
 
 ROC_TIMER : process begin
   wait until rising_edge(CLK_SYS);
@@ -270,21 +273,24 @@ STAT_RESET(31 downto 19) <= (others => '0');
 
 
 gen_link_reset : if IS_SYNC_SLAVE = 1 generate
-  link_reset_pulse : pulse_sync port map(CLK_RXI,'0',make_link_reset_i,
-                                         CLK_SYS,'0',make_link_reset_real_i);
+  link_reset_pulse : signal_sync port map(RESET => '0',CLK0 => CLK_RXI,CLK1 => CLK_SYS,
+                                          D_IN(0)  => make_link_reset_i, 
+                                          D_OUT(0) => make_link_reset_sys_i);
   link_reset_send  : signal_sync port map(RESET => '0',CLK0 => CLK_RXI,CLK1 => CLK_SYS,
                                           D_IN(0)  => send_link_reset_i, 
                                           D_OUT(0) => send_link_reset_real_i);
 end generate;
 
+make_link_reset_real_i <= make_link_reset_sys_i when IS_SYNC_SLAVE = 0 else
+                          make_link_reset_sys_i or sd_los_i when IS_SYNC_SLAVE = 1;
 
 sd_los_i <= SFP_LOS when rising_edge(CLK_SYS);
 
 media_med2int_i.stat_op(15) <= send_link_reset_real_i when rising_edge(CLK_SYS);
 media_med2int_i.stat_op(14) <= '0';
 media_med2int_i.stat_op(13) <= make_link_reset_real_i when rising_edge(CLK_SYS); --make trbnet reset
-media_med2int_i.stat_op(12) <= led_dlm or last_led_dlm;
-media_med2int_i.stat_op(11) <= led_tx or last_led_tx;
+media_med2int_i.stat_op(12) <= led_dlm  when rising_edge(CLK_SYS); -- or last_led_dlm;
+media_med2int_i.stat_op(11) <= led_tx; -- or last_led_tx;
 media_med2int_i.stat_op(10) <= led_rx or last_led_rx;
 media_med2int_i.stat_op(9)  <= led_ok;
 media_med2int_i.stat_op(8 downto 4) <= (others => '0');

diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd
index ed1ade8ce88d86c29ad83a54a51a08b395678af2..2ddd92eed392dc63020cb2392920791edc8c250b 100644 (file)
--- a/media_interfaces/sync/rx_control.vhd
+++ b/media_interfaces/sync/rx_control.vhd
@@ -75,6 +75,8 @@ signal next_sop            : std_logic;
 signal reg_rx_data_in      : std_logic_vector(7 downto 0);
 signal reg_rx_k_in         : std_logic;
 
+signal reset_cnt           : unsigned(7 downto 0);
+
 begin
 
 ----------------------------------------------------------------------
@@ -139,6 +141,7 @@ PROC_RX_FSM : process begin
     when SLEEP =>
       rx_state_bits         <= x"1";
       got_link_ready_i      <= '0';
+      make_reset_i          <= '0';
       if reg_rx_k_in = '1' and reg_rx_data_in = x"BC" then
         rx_state            <= wAIT_1;
       end if;
@@ -154,6 +157,7 @@ PROC_RX_FSM : process begin
             rx_state        <= GET_IDLE;
           when K_RST =>
             rx_state        <= MAKE_RESET;
+            reset_cnt <= x"00";
           when K_DLM =>
             rx_state        <= GET_DLM;
           when K_REQ =>
@@ -210,10 +214,18 @@ PROC_RX_FSM : process begin
         send_link_reset_i   <= '1';
         make_reset_i        <= '0';
         got_link_ready_i    <= '0';
-      else
+        if reset_cnt < x"c0" then
+          reset_cnt           <= reset_cnt + 1;
+        else
+          make_reset_i      <= '1';
+        end if;  
+      elsif reset_cnt >= x"c0" or reset_cnt < x"80" then
         send_link_reset_i   <= '0';
         make_reset_i        <= '1';
         rx_state            <= SLEEP;
+      else
+        reset_cnt <= reset_cnt + 1;
+        send_link_reset_i   <= '1';
       end if;
       
   end case;
@@ -267,10 +279,14 @@ DEBUG_OUT(5)            <= ct_fifo_afull;
 DEBUG_OUT(6)            <= ct_fifo_empty;
 DEBUG_OUT(7)            <= ct_fifo_write;
 DEBUG_OUT(15 downto 8)  <= reg_rx_data_in(7 downto 0);
+DEBUG_OUT(16)           <= reg_rx_k_in;
+DEBUG_OUT(17)           <= make_reset_i;
+DEBUG_OUT(18)           <= send_link_reset_i;
+DEBUG_OUT(19)           <= '1' when rx_state_bits = x"f" else '0';
 --DEBUG_OUT(16)           <= rx_data(16);
--- DEBUG_OUT(31 downto 18) <= (others => '0');
-DEBUG_OUT(23 downto 16) <= rx_data(7 downto 0);
-DEBUG_OUT(31 downto 24) <= ct_fifo_data_out(7 downto 0);
+DEBUG_OUT(31 downto 20) <= (others => '0');
+-- DEBUG_OUT(23 downto 16) <= rx_data(7 downto 0);
+-- DEBUG_OUT(31 downto 24) <= ct_fifo_data_out(7 downto 0);
 
 
 

diff --git a/special/spi_master.vhd b/special/spi_master.vhd
index 69ae43c4749bc6fe0886c1e8a59ec57e01275556..4caf5f141540c7c81875ac47920f1ee28ce58f99 100755 (executable)
--- a/special/spi_master.vhd
+++ b/special/spi_master.vhd
@@ -41,7 +41,7 @@ architecture Behavioral of spi_master is
   attribute HGROUP of Behavioral : architecture  is "SPI_group";
 
 -- Signals
-    type STATES is (SLEEP,RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE);
+    type STATES is (SLEEP,DONE);--RD_BSY,WR_BSY,RD_RDY,WR_RDY,RD_ACK,WR_ACK
     signal CURRENT_STATE, NEXT_STATE: STATES;
 
     signal status_data      : std_logic_vector(31 downto 0);
@@ -148,63 +148,63 @@ begin
   case CURRENT_STATE is
       when SLEEP        =>
           if   ( (spi_busy = '0') and (bus_read_in = '1') ) then
-              NEXT_STATE <= RD_RDY;
+              NEXT_STATE <= DONE;
               store_rd_x <= '1';
           elsif( (spi_busy = '0') and (bus_write_in = '1') ) then
-              NEXT_STATE <= WR_RDY;
+              NEXT_STATE <= DONE;
               store_wr_x <= '1';
           elsif( (bus_addr_in(0) = '0') and (spi_busy = '1') and (bus_read_in = '1') ) then
-              NEXT_STATE <= RD_BSY; -- CMD register is busy protected
+              NEXT_STATE <= SLEEP; -- CMD register is busy protected
               bus_busy_x <= '1';
           elsif( (bus_addr_in(0) = '0') and (spi_busy = '1') and (bus_write_in = '1') ) then
-              NEXT_STATE <= WR_BSY; -- CMD register is busy protected
+              NEXT_STATE <= SLEEP; -- CMD register is busy protected
               bus_busy_x <= '1';
           elsif( (bus_addr_in(0) = '1') and (spi_busy = '1') and (bus_read_in = '1') ) then
-              NEXT_STATE <= RD_RDY; -- STATUS register is not
+              NEXT_STATE <= DONE; -- STATUS register is not
               store_rd_x <= '1';
           elsif( (bus_addr_in(0) = '1') and (spi_busy = '1') and (bus_write_in = '1') ) then
-              NEXT_STATE <= WR_RDY; -- STATUS register is not
+              NEXT_STATE <= DONE; -- STATUS register is not
               store_wr_x <= '1';
           else
               NEXT_STATE <= SLEEP;
           end if;
-      when RD_RDY        =>
-          NEXT_STATE <= RD_ACK;
-          bus_ack_x  <= '1';
-      when WR_RDY        =>
-          NEXT_STATE <= WR_ACK;
-          bus_ack_x  <= '1';
-      when RD_ACK        =>
-          if( bus_read_in = '0' ) then
-              NEXT_STATE <= DONE;
-          else
-              NEXT_STATE <= RD_ACK;
-              bus_ack_x  <= '1';
-          end if;
-      when WR_ACK        =>
-          if( bus_write_in = '0' ) then
-              NEXT_STATE <= DONE;
-          else
-              NEXT_STATE <= WR_ACK;
-              bus_ack_x  <= '1';
-          end if;
-      when RD_BSY        =>
-          if( bus_read_in = '0' ) then
-              NEXT_STATE <= DONE;
-          else
-              NEXT_STATE <= RD_BSY;
-              bus_busy_x <= '1';
-          end if;
-      when WR_BSY        =>
-          if( bus_write_in = '0' ) then
-              NEXT_STATE <= DONE;
-          else
-              NEXT_STATE <= WR_BSY;
-              bus_busy_x <= '1';
-          end if;
+--       when RD_RDY        =>
+--           NEXT_STATE <= RD_ACK;
+--           bus_ack_x  <= '1';
+--       when WR_RDY        =>
+--           NEXT_STATE <= WR_ACK;
+--           bus_ack_x  <= '1';
+--       when RD_ACK        =>
+--           if( bus_read_in = '0' ) then
+--               NEXT_STATE <= DONE;
+--           else
+--               NEXT_STATE <= RD_ACK;
+--               bus_ack_x  <= '1';
+--           end if;
+--       when WR_ACK        =>
+--           if( bus_write_in = '0' ) then
+--               NEXT_STATE <= DONE;
+--           else
+--               NEXT_STATE <= WR_ACK;
+--               bus_ack_x  <= '1';
+--           end if;
+--       when RD_BSY        =>
+--           if( bus_read_in = '0' ) then
+--               NEXT_STATE <= DONE;
+--           else
+--               NEXT_STATE <= RD_BSY;
+--               bus_busy_x <= '1';
+--           end if;
+--       when WR_BSY        =>
+--           if( bus_write_in = '0' ) then
+--               NEXT_STATE <= DONE;
+--           else
+--               NEXT_STATE <= WR_BSY;
+--               bus_busy_x <= '1';
+--           end if;
       when DONE        =>
           NEXT_STATE <= SLEEP;
-
+          bus_ack_x  <= '1';
       when others      =>
           NEXT_STATE <= SLEEP;
   end case;