added reset when no cable connected

diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd
index 00dbfddbba49604c6603dfef25fbab93fb681876..6a0ecc8cfc4a9af1e2d9ea70c46c404857167611 100644 (file)
--- a/mdc_oepb.vhd
+++ b/mdc_oepb.vhd
@@ -55,7 +55,8 @@ architecture mdc_oepb_arch of mdc_oepb is
   signal CLK_100        : std_logic;
   signal pll_locked     : std_logic;
   signal test_counter   : unsigned(25 downto 0);
-  signal reset          : std_logic;
+  signal reset_startup  : std_logic;
+  signal reset_internal : std_logic;
   signal reset_counter  : unsigned(23 downto 0) := x"000000";
 
 
@@ -171,11 +172,17 @@ begin
   THE_RESET_COUNTER_PROC: process(CLK)
     begin
       if rising_edge(CLK) then
-        reset_counter <= reset_counter + "1";
-        reset <= '1';
-        if( reset_counter = x"FFFFEF" ) then
-          reset <= '0';
-          reset_counter <= x"FFFFEF";
+        if SD = '0' or pll_locked = '0' then --MED_STAT_OP(14) = '1'  then
+          reset_counter  <= x"000F00";
+          reset_internal <= '1';
+        elsif( reset_counter = x"000FEF" ) then
+          reset_startup <= '0';
+          reset_internal <= '0';
+          reset_counter  <= x"000FEF";
+        else
+          reset_counter <= reset_counter + "1";
+          reset_startup <= '0';
+          reset_internal <= '1';
         end if;
       end if;
     end process;
@@ -208,7 +215,7 @@ begin
       )
     port map(
       CLK    => CLK_100,
-      RESET  => reset,
+      RESET  => reset_internal,
       CLK_EN => '1',
       MED_DATAREADY_OUT   => MED_DATAREADY_OUT,
       MED_DATA_OUT        => MED_DATA_OUT,
@@ -340,7 +347,7 @@ begin
 -- full range: 8000 - FFFF
 -- 8000 - 80FF  ADC                     (17)
 -- 9000 - 9FFF  SPI
--- A000 - A7FF  Threshold Bytes         (16)
+-- A000 - A0FF  Threshold Bytes         (16)
 -- F000 - F00F  Test readout addresses  (15-0)
 
 
@@ -429,7 +436,7 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 )
   THE_ADC : adc_ltc2308_readout
     port map(
       CLK    => CLK_100,
-      RESET  => RESET,
+      RESET  => reset_internal,
       CLK_EN => '1',
 
       ADC_SCK       => ADC_SCK,
@@ -460,7 +467,7 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 )
       CLK    => CLK_100,
       CLK_25 => CLK,
       CLK_EN => '1',
-      RESET  => RESET,
+      RESET  => reset_internal,
 
       --Internal Connection
       MED_DATA_IN        => MED_DATA_OUT,
@@ -511,7 +518,7 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 )
     THE_TRIG_DISTR : trigger_distributor
     port map (
         CLK                => CLK_100,
-        RESET              => reset,
+        RESET              => reset_internal,
         INTERNAL_RESET_IN  => '0',
         A_RDO_IN           => token_to_mux_out_i,
         TRIGGER_IN         => pseudo_timing_trigger,
@@ -526,7 +533,6 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 )
         LED_ERROR_OUT      => D(2),
         LED_GOOD_OUT       => D(1)
         );
-
 ---------------------------------------------------------------------
 -- FEE Readout
 ---------------------------------------------------------------------
@@ -534,7 +540,7 @@ THE_ADDRESS_DEC_REG_PROC: process( CLK_100 )
     --generic map (bus_number => bus_number)
     port map (
       CLK                          => CLK_100,
-      RESET                        => reset,
+      RESET                        => reset_internal,
       A_ADS_0                      => '0',
       A_ADS_1                      => '0',
       A_ADS_2                      => '0',