--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+
+entity spi_slave is
+ port(
+ CLK : in std_logic;
+
+ SPI_CLK : in std_logic;
+ SPI_CS : in std_logic;
+ SPI_IN : in std_logic;
+ SPI_OUT : out std_logic;
+
+ DATA_OUT : out std_logic_vector(15 downto 0);
+ DATA_IN : in std_logic_vector(15 downto 0);
+ ADDR_OUT : out std_logic_vector(7 downto 0);
+ WRITE_OUT : out std_logic;
+ READ_OUT : out std_logic;
+ READY_IN : in std_logic;
+
+ DEBUG : out std_logic_vector(15 downto 0)
+ );
+end entity;
+
+architecture SPI_Slave_arch of spi_slave is
+signal spi_clk_last : std_logic;
+signal spi_clk_reg : std_logic;
+signal spi_cs_reg : std_logic;
+signal spi_in_reg : std_logic;
+
+signal operation_i : std_logic;
+signal data_write : std_logic_vector(15 downto 0);
+signal data_in_i : std_logic_vector(15 downto 0);
+signal addr_i : std_logic_vector(7 downto 0);
+signal last_input : std_logic;
+signal input : std_logic_vector(31 downto 0);
+
+signal next_output : std_logic;
+signal output_data : std_logic_vector (31 downto 0);
+
+signal bitcnt : integer range 0 to 31 := 31;
+
+type state_t is (IDLE, WAIT_FOR_CMD, GET_DATA, PREPARE_OUTPUT, WRITE_DATA, WAIT_FINISH);
+signal state : state_t;
+
+signal buf_SPI_OUT : std_logic;
+
+begin
+
+spi_clk_last <= spi_clk_reg when rising_edge(CLK);
+spi_clk_reg <= SPI_CLK when rising_edge(CLK);
+spi_cs_reg <= SPI_CS when rising_edge(CLK);
+spi_in_reg <= SPI_IN when rising_edge(CLK);
+
+DATA_OUT <= data_write;
+
+PROC_OUTPUT : process begin
+ wait until rising_edge(CLK);
+ next_output <= output_data(bitcnt);
+ if spi_clk_reg = '0' and spi_clk_last = '1' then
+ SPI_OUT <= last_input;
+ if operation_i = '0' and bitcnt <= 15 then
+ SPI_OUT <= next_output;
+ end if;
+ end if;
+end process;
+
+PROC_INPUT_SHIFT : process begin
+ wait until rising_edge(CLK);
+ if spi_cs_reg = '1' then
+ bitcnt <= 31;
+ else
+ if spi_clk_reg = '1' and spi_clk_last = '0' then
+ if bitcnt /= 0 then
+ bitcnt <= bitcnt - 1;
+ else
+ bitcnt <= 31;
+ end if;
+ last_input <= spi_in_reg;
+ input(bitcnt) <= spi_in_reg;
+ end if;
+ end if;
+end process;
+
+PROC_GEN_SIGNALS : process begin
+ wait until rising_edge(CLK);
+ --write_i <= (others => '0');
+ READ_OUT <= '0';
+ WRITE_OUT <= '0';
+ case state is
+ when IDLE =>
+ --operation_i <= x"0";
+ if spi_cs_reg = '0' then
+ state <= WAIT_FOR_CMD;
+ end if;
+
+ when WAIT_FOR_CMD =>
+ if bitcnt = 22 then
+ operation_i <= input(23);
+ if (input(23) = '0') then
+ READ_OUT <= '1';
+ else
+ WRITE_OUT <= '1';
+ end if;
+ ADDR_OUT <= input(31 downto 24);
+ state <= GET_DATA;
+ end if;
+
+ when GET_DATA =>
+ state <= PREPARE_OUTPUT;
+
+ when PREPARE_OUTPUT =>
+ if READY_IN = '1' then
+ output_data(15 downto 0) <= DATA_IN;
+ end if;
+ state <= WRITE_DATA;
+
+ when WRITE_DATA =>
+ if bitcnt = 31 then
+ if operation_i = '1' then
+ WRITE_OUT <= '1';
+ data_write <= input(15 downto 0);
+ --write_i(to_integer(unsigned(input(31 downto 28)))) <= '1';
+ end if;
+ state <= WAIT_FINISH;
+ end if;
+
+ when WAIT_FINISH =>
+ WRITE_OUT <= '0';
+ --if spi_cs_reg = '1' then
+ state <= IDLE;
+ --end if;
+
+ end case;
+
+ if spi_cs_reg = '1' then
+ state <= IDLE;
+ operation_i <= '0';
+ end if;
+end process;
+
+DEBUG(0) <= spi_clk_reg;
+DEBUG(1) <= spi_cs_reg;
+DEBUG(2) <= spi_in_reg;
+DEBUG(3) <= buf_SPI_OUT;
+DEBUG(7 downto 4) <= std_logic_vector(to_unsigned(bitcnt,4));
+DEBUG(14 downto 8) <= input(30 downto 24);
+--DEBUG_OUT(15) <= write_i(4);
+
+end;
\ No newline at end of file
--- /dev/null
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+#LOCATE COMP "rstn" SITE "B3" ;
+LOCATE COMP "LED[0]" SITE "H11" ;
+LOCATE COMP "LED[1]" SITE "J13" ;
+LOCATE COMP "LED[2]" SITE "J11" ;
+LOCATE COMP "LED[3]" SITE "L12" ;
+LOCATE COMP "LED[4]" SITE "K11" ;
+LOCATE COMP "LED[5]" SITE "L13" ;
+LOCATE COMP "LED[6]" SITE "N15" ;
+LOCATE COMP "LED[7]" SITE "P16" ;
+#LOCATE COMP "DIPSW[0]" SITE "N2" ;
+#LOCATE COMP "DIPSW[1]" SITE "P1" ;
+#LOCATE COMP "DIPSW[2]" SITE "M3" ;
+#LOCATE COMP "DIPSW[3]" SITE "N1" ;
+#LOCATE COMP "clk_x1" SITE "C8" ;
+#FREQUENCY PORT "clk_x1" 12.000000 MHz ;
+#IOBUF PORT "clk_x1" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+#IOBUF PORT "DIPSW[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+#IOBUF PORT "DIPSW[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+#IOBUF PORT "DIPSW[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+#IOBUF PORT "DIPSW[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+#IOBUF PORT "rstn" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "LED[0]" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "LED[1]" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "LED[2]" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "LED[3]" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "LED[4]" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "LED[5]" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "LED[6]" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+IOBUF PORT "LED[7]" PULLMODE=UP IO_TYPE=LVCMOS33 ;
+SYSCONFIG MCCLK_FREQ=133 MASTER_SPI_PORT=DISABLE CONFIGURATION=CFG ;
+
+LOCATE COMP "MISO_OUT" SITE "A4";
+LOCATE COMP "MOSI_IN" SITE "B4";
+LOCATE COMP "SCLK_IN" SITE "B5";
+LOCATE COMP "CS_IN" SITE "B6";
+
+IOBUF PORT "MISO_OUT" PULLMODE=UP IO_TYPE=LVCMOS33;
+IOBUF PORT "MOSI_IN" PULLMODE=DOWN IO_TYPE=LVCMOS33;
+IOBUF PORT "SCLK_IN" PULLMODE=DOWN IO_TYPE=LVCMOS33;
+IOBUF PORT "CS_IN" PULLMODE=DOWN IO_TYPE=LVCMOS33;
\ No newline at end of file
--- /dev/null
+Familyname => 'MachXO3LF',
+Devicename => 'LCMXO3LF-6900C',
+Package => 'CABGA256',
+Speedgrade => '5',
+
+TOPNAME => "thresholds",
+lm_license_file_for_synplify => "27000\@lxcad01.gsi.de",
+lm_license_file_for_par => "1702\@hadeb05.gsi.de",
+lattice_path => '/opt/lattice/diamond/3.6_x64',
+synplify_path => '/opt/synplicity/K-2015.09',
+#synplify_command => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options",
+synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp",
+
+nodelist_file => 'nodelist_frankfurt.txt',
+
+
+#Include only necessary lpf files
+#pinout_file => '', #name of pin-out file, if not equal TOPNAME
+include_TDC => 0,
+include_GBE => 0,
+
+#Report settings
+firefox_open => 0,
+twr_number_of_errors => 20,
+no_ltxt2ptxt => 1, #if there is no serdes being used
+make_jed => 1,
#project files
-add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesis/vhdl/machxo3lf.vhd"
+#add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesis/vhdl/machxo3lf.vhd"
#add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../../logicbox/code/uart_sctrl.vhd"
+add_file -vhdl -lib work "../../dirich/code/spi_slave.vhd"
add_file -vhdl -lib work "../../logicbox/code/sedcheck.vhd"
add_file -vhdl -lib work "../../mdcfee/code/pwm.vhd"
-add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
-add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
-add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd"
-add_file -vhdl -lib work "../../logicbox/cores/efb.vhd"
-add_file -verilog -lib work "../../logicbox/cores/efb_define_def.v"
-add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v"
+#add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd"
+#add_file -vhdl -lib work "../../logicbox/cores/efb.vhd"
+#add_file -verilog -lib work "../../logicbox/cores/efb_define_def.v"
+#add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v"
add_file -vhdl -lib work "thresholds.vhd"
#device options
set_option -technology MACHXO3LF
-set_option -part LCMXO3LF_4300E
-set_option -package UWG81CTR
+set_option -part LCMXO3LF_6900C
+set_option -package BG256C
set_option -speed_grade -5
set_option -part_companion ""
\r
entity thresholds is\r
port(\r
- CLK : in std_logic;\r
+ --CLK : in std_logic;\r
\r
OUTPUT : out std_logic_vector(15 downto 0);\r
- TX_IN : in std_logic;\r
- RX_OUT : out std_logic\r
--- MISO_OUT : out std_logic;\r
--- MOSI_IN : in std_logic;\r
--- SCLK_IN : in std_logic;\r
--- CS_IN : in std_logic\r
+ MISO_OUT : out std_logic;\r
+ MOSI_IN : in std_logic;\r
+ SCLK_IN : in std_logic;\r
+ CS_IN : in std_logic;\r
+ \r
+ LED : out std_logic_vector(7 downto 0)\r
);\r
end entity;\r
\r
architecture arch of thresholds is\r
signal clk_osc, clk_i : std_logic;\r
\r
- signal uart_rx_data : std_logic_vector(31 downto 0);\r
- signal uart_tx_data : std_logic_vector(31 downto 0);\r
- signal uart_addr : std_logic_vector(7 downto 0);\r
+ signal spi_rx_data : std_logic_vector(15 downto 0);\r
+ signal spi_tx_data : std_logic_vector(15 downto 0);\r
+ signal spi_addr : std_logic_vector(7 downto 0);\r
signal bus_read : std_logic := '0';\r
signal bus_write : std_logic := '0';\r
signal bus_ready : std_logic; \r
- signal uart_busy : std_logic; \r
+ signal spi_busy : std_logic; \r
\r
signal sed_error : std_logic;\r
signal sed_debug : std_logic_vector(31 downto 0);\r
signal flash_go : std_logic;\r
signal flash_busy : std_logic;\r
signal flash_err : std_logic;\r
-\r
+ \r
+ signal dummy_register : std_logic_vector(15 downto 0);\r
\r
component OSCH\r
generic (NOM_FREQ: string := "33.25");\r
begin\r
\r
\r
-\r
+LED <= dummy_register(7 downto 0);\r
---------------------------------------------------------------------------\r
-- Clock\r
---------------------------------------------------------------------------\r
---------------------------------------------------------------------------\r
-- UART\r
---------------------------------------------------------------------------\r
-THE_UART : entity work.uart_sctrl\r
- generic map(\r
- CLOCK_SPEED => 133000000\r
- )\r
+THE_SPI : entity work.spi_slave\r
port map(\r
CLK => clk_i,\r
- RESET => '0',\r
- UART_RX => TX_IN,\r
- UART_TX => RX_OUT,\r
- \r
- DATA_OUT => uart_rx_data,\r
- DATA_IN => uart_tx_data,\r
- ADDR_OUT => uart_addr, \r
+ SPI_CLK => SCLK_IN,\r
+ SPI_CS => CS_IN ,\r
+ SPI_IN => MOSI_IN,\r
+ SPI_OUT => MISO_OUT,\r
+ \r
+ DATA_OUT => spi_rx_data,\r
+ DATA_IN => spi_tx_data,\r
+ ADDR_OUT => spi_addr, \r
WRITE_OUT => bus_write,\r
READ_OUT => bus_read,\r
READY_IN => bus_ready,\r
\r
DEBUG => open\r
);\r
-\r
-\r
+ \r
+ \r
PROC_REGS : process begin\r
wait until rising_edge(clk_i);\r
bus_ready <= '0';\r
pwm_write_i<= '0';\r
if bus_read = '1' then\r
bus_ready <= '1';\r
- case uart_addr is\r
- when x"ee" => uart_tx_data <= sed_debug;\r
+ case spi_addr is\r
+ when x"ee" => spi_tx_data <= sed_debug(15 downto 0);\r
+ when x"ef" => spi_tx_data <= sed_debug(31 downto 16);\r
+ \r
+ when x"e4" => spi_tx_data <= dummy_register;\r
+ \r
end case;\r
elsif bus_write = '1' then\r
- if uart_addr < x"10" then\r
- pwm_data_i <= uart_rx_data(15 downto 0);\r
- pwm_addr_i <= uart_addr(4 downto 0);\r
+ if spi_addr < x"10" then\r
+ pwm_data_i <= spi_rx_data(15 downto 0);\r
+ pwm_addr_i <= spi_addr(4 downto 0);\r
pwm_write_i<= '1';\r
else\r
- case uart_addr is\r
--- when x"10" => reg <= uart_rx_data;\r
- when x"ee" => controlsed_i <= uart_rx_data(3 downto 0);\r
+ case spi_addr is\r
+-- when x"10" => reg <= spi_rx_data;\r
+ when x"ee" => controlsed_i <= spi_rx_data(3 downto 0);\r
+ \r
+ when x"e4" => dummy_register <= spi_rx_data ;\r
end case;\r
end if; \r
end if;\r
-- Flash Controller\r
--------------------------------------------------------------------------- \r
\r
-THE_FLASH_RAM : entity work.flashram\r
- port map(\r
- DataInA => ram_data_i,\r
- AddressA => ram_addr_i,\r
- ClockA => clk_i, \r
- ClockEnA => '1',\r
- WrA => ram_write_i, \r
- ResetA => '0',\r
- QA => ram_data_o,\r
-\r
- DataInB => flashram_data_i,\r
- AddressB => flashram_addr_i,\r
- ClockB => clk_i,\r
- ClockEnB => flashram_cen_i,\r
- WrB => flashram_write_i, \r
- ResetB => flashram_reset,\r
- QB => flashram_data_o\r
- );\r
-\r
-\r
-\r
-THE_FLASH : UFM_WB\r
- port map(\r
- clk_i => clk_i,\r
- rst_n => '1',\r
- cmd => flash_command,\r
- ufm_page => flash_page,\r
- GO => flash_go,\r
- BUSY => flash_busy,\r
- ERR => flash_err,\r
- mem_clk => open,\r
- mem_we => flashram_write_i,\r
- mem_ce => flashram_cen_i,\r
- mem_addr => flashram_addr_i,\r
- mem_wr_data => flashram_data_i,\r
- mem_rd_data => flashram_data_o\r
- ); \r
+-- THE_FLASH_RAM : entity work.flashram\r
+-- port map(\r
+-- DataInA => ram_data_i,\r
+-- AddressA => ram_addr_i,\r
+-- ClockA => clk_i, \r
+-- ClockEnA => '1',\r
+-- WrA => ram_write_i, \r
+-- ResetA => '0',\r
+-- QA => ram_data_o,\r
+-- \r
+-- DataInB => flashram_data_i,\r
+-- AddressB => flashram_addr_i,\r
+-- ClockB => clk_i,\r
+-- ClockEnB => flashram_cen_i,\r
+-- WrB => flashram_write_i, \r
+-- ResetB => flashram_reset,\r
+-- QB => flashram_data_o\r
+-- );\r
+-- \r
+-- \r
+-- \r
+-- THE_FLASH : UFM_WB\r
+-- port map(\r
+-- clk_i => clk_i,\r
+-- rst_n => '1',\r
+-- cmd => flash_command,\r
+-- ufm_page => flash_page,\r
+-- GO => flash_go,\r
+-- BUSY => flash_busy,\r
+-- ERR => flash_err,\r
+-- mem_clk => open,\r
+-- mem_we => flashram_write_i,\r
+-- mem_ce => flashram_cen_i,\r
+-- mem_addr => flashram_addr_i,\r
+-- mem_wr_data => flashram_data_i,\r
+-- mem_rd_data => flashram_data_o\r
+-- ); \r
\r
\r
end architecture;\r
jspc29 / dirich.git / commitdiff