pwm with 133MHz

diff --git a/thresholds/thresholds.prj b/thresholds/thresholds.prj
index c68aaaa80c50c31f31942911641495fb028f9bfd..f99281428024b90b66144c81c14fad281a0e5ff4 100644 (file)
--- a/thresholds/thresholds.prj
+++ b/thresholds/thresholds.prj
@@ -17,6 +17,7 @@ add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB_16bit.v"
 
 add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/generic_flash_ctrl.vhd"
 add_file -vhdl -lib work "thresholds.vhd"
+add_file -vhdl -lib work "../cores/pll_in133_out33_133_66.vhd"
 
 
 

diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd
index d06996f9e6a47a320c5695a4087cd94c22813323..f4df69ac8065e37f7c7c0adbf9e4619bc60a2d09 100644 (file)
--- a/thresholds/thresholds.vhd
+++ b/thresholds/thresholds.vhd
@@ -26,7 +26,7 @@ architecture arch of thresholds is
   type ram_t is array (15 downto 0) of std_logic_vector(15 downto 0);\r
   signal ram_data : ram_t := (others =>("0000000000100001"));\r
   \r
-  signal clk_osc, clk_i : std_logic;\r
+  signal clk_i, clk_osc, clk_33,clk_66 : std_logic;\r
 \r
   signal spi_rx_data : std_logic_vector(15 downto 0);\r
   signal spi_tx_data : std_logic_vector(15 downto 0);\r
@@ -72,21 +72,31 @@ begin
 -- Clock\r
 ---------------------------------------------------------------------------\r
 clk_source: OSCH\r
-  generic map ( NOM_FREQ => "33.25" )\r
+  generic map ( NOM_FREQ => "133.0" )\r
   port map (\r
     STDBY    => '0',\r
     OSC      => clk_osc,\r
     SEDSTDBY => open\r
   );\r
 \r
-clk_i <= clk_osc;  \r
-  \r
+--clk_i <= clk_osc;  \r
+\r
+\r
+THE_PLL : entity work.pll_in133_out33_133_66\r
+  port map (\r
+     CLKI => clk_osc,\r
+     CLKOP => clk_i, --133\r
+     CLKOS => clk_33, --33\r
+     CLKOS2=> clk_66  --66\r
+  );  \r
+\r
+\r
 ---------------------------------------------------------------------------\r
 -- SPI\r
 ---------------------------------------------------------------------------\r
 THE_SPI : entity work.spi_slave\r
   port map(\r
-    CLK       => clk_i,\r
+    CLK       => clk_33,\r
 \r
     SPI_CLK   => SCLK_IN,\r
     SPI_CS    => CS_IN ,\r
@@ -113,8 +123,8 @@ THE_SPI : entity work.spi_slave
 THE_FLASH_CONTROLLER : entity generic_flash_ctrl\r
   port map(\r
 \r
-    CLK_f => clk_i,\r
-    CLK_l => clk_i,\r
+    CLK_f => clk_33,\r
+    CLK_l => clk_33,\r
     RESET => '0',\r
     \r
     SPI_DATA_IN   => spi_data_out,\r
@@ -136,7 +146,7 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl
   );  \r
 \r
 PROC_REGS : process begin\r
-  wait until rising_edge(clk_i);\r
+  wait until rising_edge(clk_33);\r
   bus_ready     <= '0';\r
   pwm_write     <= '0';\r
   \r
@@ -180,7 +190,7 @@ THE_SED : entity work.sedcheck
     DEV_DENSITY =>"4300L"\r
     )\r
   port map(\r
-    CLK        => clk_i,\r
+    CLK        => clk_33,\r
     ERROR_OUT  => sed_error,\r
     \r
     CONTROL_IN => controlsed_i,\r