--Run wih 125 MHz instead of 100 MHz
constant USE_125_MHZ : integer := c_NO; --not implemented yet!
+ constant USE_EXTERNALCLOCK : integer := c_NO; --not implemented yet!
--Use sync mode, RX clock for all parts of the FPGA
constant USE_RXCLOCK : integer := c_NO; --not implemented yet!
------------------------------------------------------------------------------
type intlist_t is array(0 to 7) of integer;
type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
- constant HW_INFO_BASE : unsigned(31 downto 0) := x"91009480";
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"91009000";
constant CLOCK_FREQUENCY_ARR : intlist_t := (100,125, others => 0);
constant MEDIA_FREQUENCY_ARR : intlist_t := (200,125, others => 0);
constant HARDWARE_INFO : std_logic_vector(31 downto 0);
constant CLOCK_FREQUENCY : integer;
constant MEDIA_FREQUENCY : integer;
-
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
+
+
end;
package body config is
HW_INFO_BASE );
constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_125_MHZ);
constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_125_MHZ);
+
+
+
+function generateIncludedFeatures return std_logic_vector is
+ variable t : std_logic_vector(63 downto 0);
+begin
+ t := (others => '0');
+ t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 2
+ t(7 downto 0) := x"00"; --std_logic_vector(to_unsigned(USE_HPTDC_FASTMODE_PINOUT*3,8));
+ t(11 downto 8) := x"0"; --std_logic_vector(to_unsigned(USE_DOUBLE_EDGE*2,4));
+ t(15) := '0'; --TDC
+ t(42 downto 42) := "1"; --std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+ t(44 downto 44) := "0"; --std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+ t(51 downto 48) := x"0";--std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+ t(52 downto 52) := std_logic_vector(to_unsigned(USE_125_MHZ,1));
+ t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+ t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNALCLOCK,1));
+ return t;
+end function;
+
+ constant INCLUDED_FEATURES : std_logic_vector := generateIncludedFeatures;
end package body;
\ No newline at end of file
signal spi_cs : std_logic_vector(15 downto 0);
signal spi_sdi, spi_sdo, spi_sck : std_logic;
- signal clk_adcfast_i : std_logic;
signal clk_adcref_i : std_logic;
signal debug_adc : std_logic_vector(31 downto 0);
signal adc_restart_i : std_logic;
REGIO_HARDWARE_VERSION => HARDWARE_INFO,
REGIO_INIT_ADDRESS => INIT_ADDRESS,
REGIO_USE_VAR_ENDPOINT_ID => c_YES,
+ REGIO_INCLUDED_FEATURES => INCLUDED_FEATURES,
CLOCK_FREQUENCY => CLOCK_FREQUENCY,
TIMING_TRIGGER_RAW => c_YES,
--Configure data handler
port map(
CLK => clk_100_i,
CLK_ADCRAW => CLK_PCLK_RIGHT,
- CLK_ADCREF => clk_adcref_i,
- CLK_ADCDAT => clk_adcfast_i,
RESTART_IN => adc_restart_i,
ADCCLK_OUT => P_CLOCK,
ADC_DATA_IN => adc_data,
ADC_FCO_IN => adc_fco,
ADC_DATA_VALID => adc_data_valid,
+ ADC_STATUS_IN => debug_adc,
ADC_RESET_OUT => adc_restart_i,
---------------------------------------------------------------------------
LED_GREEN <= not med_stat_op(9);
LED_ORANGE <= not med_stat_op(10);
-LED_RED <= not or_all(debug_adc) when rising_edge(clk_100_i);
+LED_RED <= '1';
LED_YELLOW <= not med_stat_op(11);
---------------------------------------------------------------------------
port(
CLK : in std_logic;
CLK_ADCRAW : in std_logic;
- CLK_ADCREF : in std_logic;
- CLK_ADCDAT : in std_logic;
RESTART_IN : in std_logic;
ADCCLK_OUT : out std_logic;
--FCO is another channel for each ADC
constant fpgaside : s_t := (0,0,0,0,0,0,1,0,1,1,1,1);
type q_t is array(0 to 11) of std_logic_vector(19 downto 0);
-signal q : q_t;
-signal tmp : q_t;
+signal q,qq,qqq : q_t;
signal clk_adcfast_i : std_logic_vector(1 downto 0); --200MHz
signal clk_data : std_logic_vector(1 downto 0); --100MHz
-signal restart_i : std_logic_vector(1 downto 0);
+signal clk_data_half : std_logic_vector(1 downto 0);
+signal restart_i : std_logic_vector(1 downto 0);
+signal q0_q, q0 : std_logic_vector(19 downto 0);
+
type state_t is (S1,S2,S3,S4,S5);
type states_t is array(0 to 11) of state_t;
-signal state : states_t;
+signal state : states_t;
+signal state_q : state_t;
type value_it is array(0 to 4) of std_logic_vector(9 downto 0);
type value_t is array(0 to 11) of value_it;
signal fifo_empty : std_logic_vector(11 downto 0);
signal fifo_last_empty : std_logic_vector(11 downto 0);
+signal lock : std_logic_vector(2 downto 0);
begin
port map(
CLK => CLK_ADCRAW,
CLKOP => ADCCLK_OUT,
- LOCK => open
+ LOCK => lock(0)
);
THE_ADC_PLL_0 : entity work.pll_adc10bit
port map(
CLK => CLK_ADCRAW,
CLKOP => clk_adcfast_i(0),
- LOCK => open
+ LOCK => lock(1)
);
THE_ADC_PLL_1 : entity work.pll_adc10bit
port map(
CLK => CLK_ADCRAW,
CLKOP => clk_adcfast_i(1),
- LOCK => open
+ LOCK => lock(2)
);
restart_i(0) <= RESTART_IN when rising_edge(clk_data(0));
restart_i(1) <= RESTART_IN when rising_edge(clk_data(1));
+
+ clk_data_half(0) <= not clk_data_half(0) when rising_edge(clk_data(0));
+ clk_data_half(1) <= not clk_data_half(1) when rising_edge(clk_data(1));
THE_LEFT : entity work.dqsinput_7x5
port map(
clk_4 => ADC_DCO(5),
clk_5 => ADC_DCO(6),
clk_6 => ADC_DCO(8),
- clkdiv_reset => restart_i(0),
+ clkdiv_reset => RESTART_IN,
eclk => clk_adcfast_i(0),
reset_0 => restart_i(0),
reset_1 => restart_i(0),
clk_2 => ADC_DCO(10),
clk_3 => ADC_DCO(11),
clk_4 => ADC_DCO(12),
- clkdiv_reset => restart_i(1),
+ clkdiv_reset => RESTART_IN,
eclk => clk_adcfast_i(1),
reset_0 => restart_i(1),
reset_1 => restart_i(1),
gen_chips_left : for i in 0 to DEVICES_LEFT+DEVICES_RIGHT-1 generate
+ gen_data_mapping : for j in 0 to CHANNELS generate
+ gen_data_mapping_bits : for k in 0 to 3 generate
+ qqq(i)(j*4+3-k) <= qq(i)(k*(CHANNELS+1)+j);
+ end generate;
+ end generate;
+
proc_collect_data : process begin
wait until rising_edge(clk_data(fpgaside(i)));
+ qq(i) <= q(i);
fifo_write(i) <= '0';
case state(i) is
when S1 =>
- if q(i)(19 downto 16) = x"0011" then
+-- fifo_input(i)(0)(3 downto 0) <= qqq(i)(3 downto 0 );
+-- fifo_input(i)(1)(3 downto 0) <= qqq(i)(7 downto 4 );
+-- fifo_input(i)(2)(3 downto 0) <= qqq(i)(11 downto 8 );
+-- fifo_input(i)(3)(3 downto 0) <= qqq(i)(15 downto 12);
+-- fifo_input(i)(4)(3 downto 0) <= qqq(i)(19 downto 16);
+-- fifo_write(i) <= '1';
+ if qqq(i)(19 downto 16) = "0011" then
state(i) <= S2;
- value(i)(0)(9 downto 8) <= q(i)(1 downto 0 );
- value(i)(1)(9 downto 8) <= q(i)(5 downto 4 );
- value(i)(2)(9 downto 8) <= q(i)(9 downto 8 );
- value(i)(3)(9 downto 8) <= q(i)(13 downto 12);
- value(i)(4)(9 downto 8) <= q(i)(17 downto 16);
+ value(i)(0)(9 downto 8) <= qqq(i)(1 downto 0 );
+ value(i)(1)(9 downto 8) <= qqq(i)(5 downto 4 );
+ value(i)(2)(9 downto 8) <= qqq(i)(9 downto 8 );
+ value(i)(3)(9 downto 8) <= qqq(i)(13 downto 12);
+ value(i)(4)(9 downto 8) <= qqq(i)(17 downto 16);
fifo_input(i) <= value(i);
- fifo_input(i)(0)(1 downto 0) <= q(i)(3 downto 2 );
- fifo_input(i)(1)(1 downto 0) <= q(i)(7 downto 6 );
- fifo_input(i)(2)(1 downto 0) <= q(i)(11 downto 10);
- fifo_input(i)(3)(1 downto 0) <= q(i)(15 downto 14);
- fifo_input(i)(4)(1 downto 0) <= q(i)(19 downto 18);
+ fifo_input(i)(0)(1 downto 0) <= qqq(i)(3 downto 2 );
+ fifo_input(i)(1)(1 downto 0) <= qqq(i)(7 downto 6 );
+ fifo_input(i)(2)(1 downto 0) <= qqq(i)(11 downto 10);
+ fifo_input(i)(3)(1 downto 0) <= qqq(i)(15 downto 14);
+ fifo_input(i)(4)(1 downto 0) <= qqq(i)(19 downto 18);
fifo_write(i) <= '1';
end if;
when S2 =>
state(i) <= S3;
- value(i)(0)(7 downto 4) <= q(i)(3 downto 0 );
- value(i)(1)(7 downto 4) <= q(i)(7 downto 4 );
- value(i)(2)(7 downto 4) <= q(i)(11 downto 8 );
- value(i)(3)(7 downto 4) <= q(i)(15 downto 12);
- value(i)(4)(7 downto 4) <= q(i)(19 downto 16);
+ value(i)(0)(7 downto 4) <= qqq(i)(3 downto 0 );
+ value(i)(1)(7 downto 4) <= qqq(i)(7 downto 4 );
+ value(i)(2)(7 downto 4) <= qqq(i)(11 downto 8 );
+ value(i)(3)(7 downto 4) <= qqq(i)(15 downto 12);
+ value(i)(4)(7 downto 4) <= qqq(i)(19 downto 16);
when S3 =>
state(i) <= S4;
fifo_input(i) <= value(i);
- fifo_input(i)(0)(3 downto 0) <= q(i)(3 downto 0 );
- fifo_input(i)(1)(3 downto 0) <= q(i)(7 downto 4 );
- fifo_input(i)(2)(3 downto 0) <= q(i)(11 downto 8 );
- fifo_input(i)(3)(3 downto 0) <= q(i)(15 downto 12);
- fifo_input(i)(4)(3 downto 0) <= q(i)(19 downto 16);
+ fifo_input(i)(0)(3 downto 0) <= qqq(i)(3 downto 0 );
+ fifo_input(i)(1)(3 downto 0) <= qqq(i)(7 downto 4 );
+ fifo_input(i)(2)(3 downto 0) <= qqq(i)(11 downto 8 );
+ fifo_input(i)(3)(3 downto 0) <= qqq(i)(15 downto 12);
+ fifo_input(i)(4)(3 downto 0) <= qqq(i)(19 downto 16);
fifo_write(i) <= '1';
when S4 =>
state(i) <= S5;
- value(i)(0)(9 downto 6) <= q(i)(3 downto 0 );
- value(i)(1)(9 downto 6) <= q(i)(7 downto 4 );
- value(i)(2)(9 downto 6) <= q(i)(11 downto 8 );
- value(i)(3)(9 downto 6) <= q(i)(15 downto 12);
- value(i)(4)(9 downto 6) <= q(i)(19 downto 16);
+ value(i)(0)(9 downto 6) <= qqq(i)(3 downto 0 );
+ value(i)(1)(9 downto 6) <= qqq(i)(7 downto 4 );
+ value(i)(2)(9 downto 6) <= qqq(i)(11 downto 8 );
+ value(i)(3)(9 downto 6) <= qqq(i)(15 downto 12);
+ value(i)(4)(9 downto 6) <= qqq(i)(19 downto 16);
when S5 =>
state(i) <= S1;
- value(i)(0)(5 downto 2) <= q(i)(3 downto 0 );
- value(i)(1)(5 downto 2) <= q(i)(7 downto 4 );
- value(i)(2)(5 downto 2) <= q(i)(11 downto 8 );
- value(i)(3)(5 downto 2) <= q(i)(15 downto 12);
- value(i)(4)(5 downto 2) <= q(i)(19 downto 16);
+ value(i)(0)(5 downto 2) <= qqq(i)(3 downto 0 );
+ value(i)(1)(5 downto 2) <= qqq(i)(7 downto 4 );
+ value(i)(2)(5 downto 2) <= qqq(i)(11 downto 8 );
+ value(i)(3)(5 downto 2) <= qqq(i)(15 downto 12);
+ value(i)(4)(5 downto 2) <= qqq(i)(19 downto 16);
end case;
if restart_i(fpgaside(i)) = '1' then
state(i) <= S1;
RdClock => CLK,
WrEn => fifo_write(i),
RdEn => '1',
- Reset => restart_i(fpgaside(i)),
+ Reset => '0',
RPReset => RESTART_IN,
Q(49 downto 0) => fifo_output(i),
Empty => fifo_empty(i),
Full => open
);
- DEBUG(i) <= or_all(tmp(i));
+-- DEBUG(i) <= or_all(tmp(i));
proc_output : process begin
wait until rising_edge(CLK);
+ fifo_last_empty <= fifo_empty;
if fifo_last_empty(i) = '0' then
DATA_OUT(i*40+39 downto i*40+0) <= fifo_output(i)(39 downto 0);
FCO_OUT (i*10+9 downto i*10+0) <= fifo_output(i)(49 downto 40);
end generate;
+q0 <= q(0) when rising_edge(clk_data(0));
+q0_q <= q0 when rising_edge(CLK);
+
+proc_debug : process begin
+ wait until rising_edge(CLK);
+ state_q <= state(0);
+ DEBUG <= (others => '0');
+ DEBUG(3 downto 0) <= q0_q(3 downto 0);
+ DEBUG(7 downto 4) <= q0_q(19 downto 16);
+ case state_q is
+ when S1 => DEBUG(11 downto 8) <= x"1";
+ when S2 => DEBUG(11 downto 8) <= x"2";
+ when S3 => DEBUG(11 downto 8) <= x"3";
+ when S4 => DEBUG(11 downto 8) <= x"4";
+ when S5 => DEBUG(11 downto 8) <= x"5";
+ when others => DEBUG(11 downto 8) <= x"0";
+ end case;
+ DEBUG(14 downto 12) <= lock;
+ DEBUG(17 downto 16) <= clk_data_half;
+end process;
+
end architecture;
ADC_DATA_IN : in std_logic_vector(DEVICES*CHANNELS*RESOLUTION-1 downto 0);
ADC_FCO_IN : in std_logic_vector(DEVICES*RESOLUTION-1 downto 0);
ADC_DATA_VALID : in std_logic_vector(DEVICES-1 downto 0);
+ ADC_STATUS_IN : in std_logic_vector(31 downto 0);
ADC_RESET_OUT : out std_logic;
signal fifo_read : std_logic_vector(DEVICES*CHANNELS-1 downto 0);
signal fifo_empty : std_logic_vector(DEVICES*CHANNELS-1 downto 0);
signal fifo_full : std_logic_vector(DEVICES*CHANNELS-1 downto 0);
+signal fifo_write : std_logic_vector(DEVICES*CHANNELS-1 downto 0);
signal fifo_reset : std_logic;
+signal fifo_stop : std_logic;
type dout_t is array(0 to DEVICES*CHANNELS-1) of std_logic_vector(17 downto 0);
signal fifo_dout : dout_t;
signal ctrl_reg : std_logic_vector(31 downto 0);
signal saved_addr : integer range 0 to DEVICES*CHANNELS-1;
-signal fifo_wait_1, fifo_wait_2 : std_logic;
+signal fifo_wait_0, fifo_wait_1, fifo_wait_2 : std_logic;
begin
THE_FIFO : entity work.fifo_18x1k_oreg
port map (
Data(9 downto 0) => ADC_DATA_IN(10*i+9 downto 10*i),
- Data(17 downto 10) => ADC_FCO_IN (10*(i/CHANNELS)+7 downto 10*(i/CHANNELS)),
+-- Data(17 downto 10) => ADC_FCO_IN (10*(i/CHANNELS)+7 downto 10*(i/CHANNELS)),
+ Data(15 downto 12) => ADC_FCO_IN (10*(i/CHANNELS)+3 downto 10*(i/CHANNELS)),
Clock => CLK,
- WrEn => ADC_DATA_VALID(i / CHANNELS),
+ WrEn => fifo_write(i),
RdEn => fifo_read(i),
Reset => fifo_reset,
AmFullThresh => "1111110000",
Full => open,
AlmostFull => fifo_full(i)
);
+ fifo_write(i) <= ADC_DATA_VALID(i / CHANNELS) and not fifo_stop;
end generate;
-fifo_wait_1 <= or_all(fifo_read) when rising_edge(CLK);
+fifo_wait_1 <= fifo_wait_0 when rising_edge(CLK);
fifo_wait_2 <= fifo_wait_1 when rising_edge(CLK);
BUS_TX.unknown <= '0';
ADC_RESET_OUT <= '0';
fifo_read <= fifo_full;
+ fifo_wait_0 <= '0';
if BUS_RX.read = '1' then
if BUS_RX.addr(7 downto 0) = x"80" then
BUS_TX.data <= ctrl_reg;
BUS_TX.ack <= '1';
+ elsif BUS_RX.addr(7 downto 0) = x"82" then
+ BUS_TX.data <= ADC_STATUS_IN(31 downto 0);
+ BUS_TX.ack <= '1';
+ elsif BUS_RX.addr(7 downto 0) = x"83" then
+ BUS_TX.data <= (others => '0');
+ BUS_TX.data(10 downto 0) <= fifo_count(0);
+ BUS_TX.ack <= '1';
elsif BUS_RX.addr(7 downto 0) < std_logic_vector(to_unsigned(DEVICES*CHANNELS,8)) then
saved_addr <= to_integer(unsigned(BUS_RX.addr(6 downto 0)));
fifo_read(to_integer(unsigned(BUS_RX.addr(6 downto 0)))) <= '1';
+ fifo_wait_0 <= '1';
else
BUS_TX.unknown <= '1';
end if;
ctrl_reg <= BUS_RX.data;
BUS_TX.ack <= '1';
elsif BUS_RX.addr(7 downto 0) = x"81" then
- ADC_RESET_OUT <= '1';
+ ADC_RESET_OUT <= BUS_RX.data(0);
+ fifo_stop <= BUS_RX.data(1);
BUS_TX.ack <= '1';
else
BUS_TX.unknown <= '1';
jspc29 / trb3.git / commitdiff