started to implement trigger input statistics

diff --git a/base/code/input_statistics.vhd b/base/code/input_statistics.vhd
new file mode 100644 (file)
index 0000000..19f9b97
--- /dev/null
+++ b/base/code/input_statistics.vhd
@@ -0,0 +1,78 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+
+entity input_statistics is
+  generic(
+    INPUTS     : integer range 1 to 32 := 16
+    );
+  port(
+    CLK        : in std_logic;
+    
+    INPUT      : in  std_logic_vector(INPUTS-1 downto 0);
+
+    DATA_IN    : in  std_logic_vector(31 downto 0) := (others => '0');
+    DATA_OUT   : out std_logic_vector(31 downto 0);
+    WRITE_IN   : in  std_logic := '0';
+    READ_IN    : in  std_logic := '0';
+    ACK_OUT    : out std_logic;
+    NACK_OUT   : out std_logic;
+    ADDR_IN    : in  std_logic_vector(15 downto 0) := (others => '0')
+    
+    );
+end entity;
+
+
+architecture input_statistics_arch of input_statistics is
+
+signal inp_reg      : std_logic_vector(INPUTS-1 downto 0);
+
+signal trigger_fifo : std_logic;
+signal reset_cnt    : std_logic;
+
+signal enable : std_logic_vector(31 downto 0);
+signal invert : std_logic_vector(31 downto 0);
+signal rate   : unsigned(31 downto 0);
+
+begin
+
+
+THE_CONTROL : process 
+  variable tmp : integer range 0 to 15;
+begin
+  wait until rising_edge(CLK);
+  ACK_OUT  <= '0';
+  NACK_OUT <= '0';
+  trigger_fifo  <= '0';
+  if WRITE_IN = '1' then
+    if ADDR_IN(6 downto 4) = "000" then
+      ACK_OUT <= '1';
+      case ADDR_IN(3 downto 0) is
+        when x"0"   => enable <= DATA_IN;
+        when x"1"   => invert <= DATA_IN;
+        when x"2"   => rate   <= unsigned(DATA_IN);
+        when x"f"   => trigger_fifo <= DATA_IN(0);
+                       reset_cnt    <= DATA_IN(1);
+        when others => NACK_OUT <= '1'; ACK_OUT <= '0';
+      end case;
+    end if;
+  elsif READ_IN = '1' then
+    if ADDR_IN(6 downto 4) = "000" then
+      ACK_OUT <= '1';
+      case ADDR_IN(3 downto 0) is
+        when x"0"   => DATA_OUT <= enable;
+        when x"1"   => DATA_OUT <= invert;
+        when x"2"   => DATA_OUT <= std_logic_vector(rate);
+        when x"e"   => DATA_OUT(INPUTS-1 downto 0)  <= inp_reg; DATA_OUT(31 downto INPUTS) <= (others => '0');
+        when others => DATA_OUT <= (others => '0');
+      end case;
+    end if;
+  end if;
+end process;
+
+
+inp_reg <= INPUT when rising_edge(CLK);
+
+end architecture;
\ No newline at end of file

diff --git a/base/code/input_to_trigger_logic.vhd b/base/code/input_to_trigger_logic.vhd
index 8b595c80d1480e1b15149a7cf43e0e29fbf083cf..aa3e38dac2ad87944dcca7980baa25c61eaa00eb 100644 (file)
--- a/base/code/input_to_trigger_logic.vhd
+++ b/base/code/input_to_trigger_logic.vhd
@@ -27,13 +27,16 @@ entity input_to_trigger_logic is
 end entity;
 
 
-
 architecture input_to_trigger_logic_arch of input_to_trigger_logic is
 
 type reg_t is array(0 to OUTPUTS-1) of std_logic_vector(31 downto 0);
 signal enable : reg_t;
 signal invert : reg_t;
 
+signal inp_reg : std_logic_vector(INPUTS-1 downto 0);
+signal output_i: std_logic_vector(OUTPUTS-1 downto 0);
+signal out_reg : std_logic_vector(OUTPUTS-1 downto 0);
+
 begin
 
 
@@ -56,15 +59,20 @@ begin
     case ADDR_IN(1 downto 0) is
       when "00"   => DATA_OUT <= enable(tmp);
       when "01"   => DATA_OUT <= invert(tmp);
+      when "10"   => DATA_OUT(INPUTS-1 downto 0)  <= inp_reg; DATA_OUT(31 downto INPUTS) <= (others => '0');
+      when "11"   => DATA_OUT(OUTPUTS-1 downto 0) <= out_reg; DATA_OUT(31 downto OUTPUTS) <= (others => '0');
       when others => DATA_OUT <= (others => '0');
     end case;
   end if;
 end process;
 
 gen_outs : for i in 0 to OUTPUTS-1 generate
-  OUTPUT(i) <= or_all((INPUT xor invert(i)(INPUTS-1 downto 0)) and enable(i)(INPUTS-1 downto 0));
+  output_i(i) <= or_all((INPUT xor invert(i)(INPUTS-1 downto 0)) and enable(i)(INPUTS-1 downto 0));
 end generate;
 
+inp_reg <= INPUT when rising_edge(CLK);
+out_reg <= output_i when rising_edge(CLK);
 
+OUTPUT  <= output_i;
 
 end architecture;
\ No newline at end of file

diff --git a/hadesstart/config.vhd b/hadesstart/config.vhd
index 0243ff68699ca3cf6c6179a531767cf41b26537d..826a9b99a40b846c65f44c5f9a651d89ca2fc90e 100644 (file)
--- a/hadesstart/config.vhd
+++ b/hadesstart/config.vhd
@@ -23,8 +23,12 @@ package config is
 
 --Add logic to generate configurable trigger signal from input signals.
     constant INCLUDE_TRIGGER_LOGIC  : integer := c_YES;    
+--Do histos of all inputs
+    constant INCLUDE_STATISTICS     : integer := c_YES;    
 --number of real inputs to the FPGA    
     constant PHYSICAL_INPUTS        : integer := 16;
+
+    
     
 --Run wih 125 MHz instead of 100 MHz     
     constant USE_125_MHZ            : integer := c_NO;  --not implemented yet!  

diff --git a/hadesstart/trb3_periph_hadesstart.prj b/hadesstart/trb3_periph_hadesstart.prj
index dea3fa628f4878b21fec5deae247b5e28d9bbf98..fb204569a567d89c43528ade9e6d99c098c73b5e 100644 (file)
--- a/hadesstart/trb3_periph_hadesstart.prj
+++ b/hadesstart/trb3_periph_hadesstart.prj
@@ -168,7 +168,9 @@ add_file -vhdl -lib "work" "../base/cores/FIFO_DC_36x128_OutReg.vhd"
 add_file -vhdl -lib "work" "currentRelease/Reference_Channel_200.vhd"
 add_file -vhdl -lib "work" "currentRelease/Reference_Channel.vhd"
 
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
 add_file -vhdl -lib "work" "../base/code/input_to_trigger_logic.vhd"
+add_file -vhdl -lib "work" "../base/code/input_statistics.vhd"
 
 add_file -vhdl -lib "work" "trb3_periph_hadesstart.vhd"
 

diff --git a/hadesstart/trb3_periph_hadesstart.vhd b/hadesstart/trb3_periph_hadesstart.vhd
index 34714330861b5b104ee2c4a72d5c6e2bc55f71d8..a2f6bd828193ebdabf766653ef8122d8003035d5 100644 (file)
--- a/hadesstart/trb3_periph_hadesstart.vhd
+++ b/hadesstart/trb3_periph_hadesstart.vhd
@@ -171,19 +171,16 @@ architecture trb3_periph_hadesstart_arch of trb3_periph_hadesstart is
   signal timer_ticks         : std_logic_vector(1 downto 0);
 
   --Flash
-  signal spictrl_read_en  : std_logic;
-  signal spictrl_write_en : std_logic;
-  signal spictrl_data_in  : std_logic_vector(31 downto 0);
-  signal spictrl_addr     : std_logic;
-  signal spictrl_data_out : std_logic_vector(31 downto 0);
-  signal spictrl_ack      : std_logic;
-  signal spictrl_busy     : std_logic;
-  signal spimem_read_en   : std_logic;
-  signal spimem_write_en  : std_logic;
-  signal spimem_data_in   : std_logic_vector(31 downto 0);
-  signal spimem_addr      : std_logic_vector(5 downto 0);
-  signal spimem_data_out  : std_logic_vector(31 downto 0);
-  signal spimem_ack       : std_logic;
+  signal spimem_read_en          : std_logic;
+  signal spimem_write_en         : std_logic;
+  signal spimem_data_in          : std_logic_vector(31 downto 0);
+  signal spimem_addr             : std_logic_vector(8 downto 0);
+  signal spimem_data_out         : std_logic_vector(31 downto 0);
+  signal spimem_dataready_out    : std_logic;
+  signal spimem_no_more_data_out : std_logic;
+  signal spimem_unknown_addr_out : std_logic;
+  signal spimem_write_ack_out    : std_logic;
+  
   signal spidac_read_en   : std_logic;
   signal spidac_write_en  : std_logic;
   signal spidac_data_in   : std_logic_vector(31 downto 0);
@@ -192,14 +189,11 @@ architecture trb3_periph_hadesstart_arch of trb3_periph_hadesstart is
   signal spidac_ack       : std_logic;
   signal spidac_busy      : std_logic;
 
-
   signal spi_cs  : std_logic_vector(1 downto 0);
   signal spi_sdi : std_logic;
   signal spi_sdo : std_logic;
   signal spi_sck : std_logic;
 
-      
-
   signal hitreg_read_en    : std_logic;
   signal hitreg_write_en   : std_logic;
   signal hitreg_addr       : std_logic_vector(6 downto 0);
@@ -256,7 +250,15 @@ architecture trb3_periph_hadesstart_arch of trb3_periph_hadesstart is
   signal trig_ack   : std_logic := '0';
   signal trig_nack  : std_logic := '0';
   signal trig_addr  : std_logic_vector(15 downto 0) := (others => '0');
-  
+
+  signal stat_out   : std_logic_vector(3 downto 0);
+  signal stat_din   : std_logic_vector(31 downto 0);
+  signal stat_dout  : std_logic_vector(31 downto 0);
+  signal stat_write : std_logic := '0';
+  signal stat_read  : std_logic := '0';
+  signal stat_ack   : std_logic := '0';
+  signal stat_nack  : std_logic := '0';
+  signal stat_addr  : std_logic_vector(15 downto 0) := (others => '0');  
   --TDC
   signal hit_in_i         : std_logic_vector(64 downto 1);
   signal inputs_i         : std_logic_vector(63 downto 0);
@@ -472,9 +474,6 @@ begin
   common_stat_reg       <= (others => '0');
   stat_reg              <= (others => '0');
 
----------------------------------------------------------------------------
--- AddOn
----------------------------------------------------------------------------
 
 ---------------------------------------------------------------------------
 -- Bus Handler
@@ -482,8 +481,8 @@ begin
   THE_BUS_HANDLER : trb_net16_regio_bus_handler
     generic map(
       PORT_NUMBER    => 10,
-      PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", 9 => x"cf00", others => x"0000"),
-      PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, 4 => 5, 5 => 7, 6 => 7, 7 => 7, 8 => 3, 9 => 6, others => 0)
+      PORT_ADDRESSES => (0 => x"d000", 1 => x"cf80", 2 => x"d400", 3 => x"c000", 4 => x"c100", 5 => x"c200", 6 => x"c300", 7 => x"c400", 8 => x"c800", 9 => x"cf00", others => x"0000"),
+      PORT_ADDR_MASK => (0 => 9,       1 => 6,       2 => 5,       3 => 7,       4 => 5,       5 => 7,       6 => 7,       7 => 7,       8 => 3,       9 => 6,       others => 0)
       )
     port map(
       CLK   => clk_100_i,
@@ -500,30 +499,29 @@ begin
       DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
       DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
 
-      --Bus Handler (SPI CTRL)
-      BUS_READ_ENABLE_OUT(0)              => spictrl_read_en,
-      BUS_WRITE_ENABLE_OUT(0)             => spictrl_write_en,
-      BUS_DATA_OUT(0*32+31 downto 0*32)   => spictrl_data_in,
-      BUS_ADDR_OUT(0*16)                  => spictrl_addr,
-      BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open,
+    --Bus Handler (SPI Flash control)
+      BUS_READ_ENABLE_OUT(0)              => spimem_read_en,
+      BUS_WRITE_ENABLE_OUT(0)             => spimem_write_en,
+      BUS_DATA_OUT(0*32+31 downto 0*32)   => spimem_data_in,
+      BUS_ADDR_OUT(0*16+8 downto 0*16)    => spimem_addr,
+      BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
       BUS_TIMEOUT_OUT(0)                  => open,
-      BUS_DATA_IN(0*32+31 downto 0*32)    => spictrl_data_out,
-      BUS_DATAREADY_IN(0)                 => spictrl_ack,
-      BUS_WRITE_ACK_IN(0)                 => spictrl_ack,
-      BUS_NO_MORE_DATA_IN(0)              => spictrl_busy,
-      BUS_UNKNOWN_ADDR_IN(0)              => '0',
-      --Bus Handler (SPI Memory)
-      BUS_READ_ENABLE_OUT(1)              => spimem_read_en,
-      BUS_WRITE_ENABLE_OUT(1)             => spimem_write_en,
-      BUS_DATA_OUT(1*32+31 downto 1*32)   => spimem_data_in,
-      BUS_ADDR_OUT(1*16+5 downto 1*16)    => spimem_addr,
-      BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open,
+      BUS_DATA_IN(0*32+31 downto 0*32)    => spimem_data_out,
+      BUS_DATAREADY_IN(0)                 => spimem_dataready_out,
+      BUS_WRITE_ACK_IN(0)                 => spimem_write_ack_out,
+      BUS_NO_MORE_DATA_IN(0)              => spimem_no_more_data_out,
+      BUS_UNKNOWN_ADDR_IN(0)              => spimem_unknown_addr_out,
+      --Input statistics
+      BUS_READ_ENABLE_OUT(1)              => stat_read,
+      BUS_WRITE_ENABLE_OUT(1)             => stat_write,
+      BUS_DATA_OUT(1*32+31 downto 1*32)   => stat_din,
+      BUS_ADDR_OUT(1*16+15 downto 1*16)   => stat_addr,
       BUS_TIMEOUT_OUT(1)                  => open,
-      BUS_DATA_IN(1*32+31 downto 1*32)    => spimem_data_out,
-      BUS_DATAREADY_IN(1)                 => spimem_ack,
-      BUS_WRITE_ACK_IN(1)                 => spimem_ack,
+      BUS_DATA_IN(1*32+31 downto 1*32)    => stat_dout,
+      BUS_DATAREADY_IN(1)                 => stat_ack,
+      BUS_WRITE_ACK_IN(1)                 => stat_ack,
       BUS_NO_MORE_DATA_IN(1)              => '0',
-      BUS_UNKNOWN_ADDR_IN(1)              => '0',
+      BUS_UNKNOWN_ADDR_IN(1)              => stat_nack,      
       --Bus Handler (SPI DAC)
       BUS_READ_ENABLE_OUT(2)              => spidac_read_en,
       BUS_WRITE_ENABLE_OUT(2)             => spidac_write_en,
@@ -619,6 +617,7 @@ begin
       BUS_WRITE_ACK_IN(9)                 => trig_ack,
       BUS_NO_MORE_DATA_IN(9)              => '0',
       BUS_UNKNOWN_ADDR_IN(9)              => trig_nack,
+
       STAT_DEBUG => open
       );
 
@@ -637,61 +636,37 @@ begin
 ---------------------------------------------------------------------------
 -- SPI / Flash
 ---------------------------------------------------------------------------
-
-  THE_SPI_MASTER : spi_master
-    port map(
-      CLK_IN         => clk_100_i,
-      RESET_IN       => reset_i,
-      -- Slave bus
-      BUS_READ_IN    => spictrl_read_en,
-      BUS_WRITE_IN   => spictrl_write_en,
-      BUS_BUSY_OUT   => spictrl_busy,
-      BUS_ACK_OUT    => spictrl_ack,
-      BUS_ADDR_IN(0) => spictrl_addr,
-      BUS_DATA_IN    => spictrl_data_in,
-      BUS_DATA_OUT   => spictrl_data_out,
-      -- SPI connections
-      SPI_CS_OUT     => FLASH_CS,
-      SPI_SDI_IN     => FLASH_DOUT,
-      SPI_SDO_OUT    => FLASH_DIN,
-      SPI_SCK_OUT    => FLASH_CLK,
-      -- BRAM for read/write data
-      BRAM_A_OUT     => spi_bram_addr,
-      BRAM_WR_D_IN   => spi_bram_wr_d,
-      BRAM_RD_D_OUT  => spi_bram_rd_d,
-      BRAM_WE_OUT    => spi_bram_we,
-      -- Status lines
-      STAT           => open
-      );
-
-  -- data memory for SPI accesses
-  THE_SPI_MEMORY : spi_databus_memory
-    port map(
-      CLK_IN        => clk_100_i,
-      RESET_IN      => reset_i,
-      -- Slave bus
-      BUS_ADDR_IN   => spimem_addr,
-      BUS_READ_IN   => spimem_read_en,
-      BUS_WRITE_IN  => spimem_write_en,
-      BUS_ACK_OUT   => spimem_ack,
-      BUS_DATA_IN   => spimem_data_in,
-      BUS_DATA_OUT  => spimem_data_out,
-      -- state machine connections
-      BRAM_ADDR_IN  => spi_bram_addr,
-      BRAM_WR_D_OUT => spi_bram_wr_d,
-      BRAM_RD_D_IN  => spi_bram_rd_d,
-      BRAM_WE_IN    => spi_bram_we,
-      -- Status lines
-      STAT          => open
-      );
-
+THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload
+  port map(
+    CLK_IN               => clk_100_i,
+    RESET_IN             => reset_i,
+    
+    BUS_ADDR_IN          => spimem_addr,
+    BUS_READ_IN          => spimem_read_en,
+    BUS_WRITE_IN         => spimem_write_en,
+    BUS_DATAREADY_OUT    => spimem_dataready_out,
+    BUS_WRITE_ACK_OUT    => spimem_write_ack_out,
+    BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
+    BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
+    BUS_DATA_IN          => spimem_data_in,
+    BUS_DATA_OUT         => spimem_data_out,
+    
+    DO_REBOOT_IN         => common_ctrl_reg(15),     
+    PROGRAMN             => PROGRAMN,
+    
+    SPI_CS_OUT           => FLASH_CS,
+    SPI_SCK_OUT          => FLASH_CLK,
+    SPI_SDO_OUT          => FLASH_DIN,
+    SPI_SDI_IN           => FLASH_DOUT
+    );
+    
 -------------------------------------------------------------------------------
 -- SPI
 -------------------------------------------------------------------------------
 gen_SPI : if INCLUDE_SPI = 1 generate  
   DAC_SPI : spi_ltc2600
     generic map (
-      BITS       => 14,
+      BITS       => 32,
       WAITCYCLES => 15)
     port map (
       CLK_IN         => clk_100_i,
@@ -727,7 +702,7 @@ end generate;
 -- Trigger logic
 ---------------------------------------------------------------------------
 gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
-  THE_TRIG_LOGIC : input_to_trigger_logic
+  THE_TRIG_LOGIC : entity work.input_to_trigger_logic
     generic map(
       INPUTS    => PHYSICAL_INPUTS,
       OUTPUTS   => 4
@@ -749,15 +724,29 @@ gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate
 end generate;
 
 ---------------------------------------------------------------------------
--- Reboot FPGA
+-- Input Statistics
 ---------------------------------------------------------------------------
-  THE_FPGA_REBOOT : fpga_reboot
+gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate
+
+  THE_STAT_LOGIC : entity work.input_statistics
+    generic map(
+      INPUTS    => PHYSICAL_INPUTS
+      )
     port map(
       CLK       => clk_100_i,
-      RESET     => reset_i,
-      DO_REBOOT => common_ctrl_reg(15),
-      PROGRAMN  => PROGRAMN
+      
+      INPUT     => inputs_i(PHYSICAL_INPUTS-1 downto 0),
+
+      DATA_IN   => stat_din,  
+      DATA_OUT  => stat_dout, 
+      WRITE_IN  => stat_write,
+      READ_IN   => stat_read,
+      ACK_OUT   => stat_ack,  
+      NACK_OUT  => stat_nack, 
+      ADDR_IN   => stat_addr
       );
+end generate;
+
 
 ---------------------------------------------------------------------------
 -- LED