operation_i <= input(23);
if (input(23) = '0') then
READ_OUT <= '1';
- else
- WRITE_OUT <= '1';
+ --else
+ -- WRITE_OUT <= '1';
end if;
ADDR_OUT <= input(31 downto 24);
state <= GET_DATA;
COMMERCIAL ;
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
-SYSCONFIG MCCLK_FREQ=33 BACKGROUND_RECONFIG=ON ENABLE_TRANSFR=ENABLE MUX_CONFIGURATION_PORTS=ENABLE ;
+SYSCONFIG MCCLK_FREQ=33.25 BACKGROUND_RECONFIG=ON ENABLE_TRANSFR=ENABLE MUX_CONFIGURATION_PORTS=ENABLE ;
LOCATE COMP "MISO_OUT" SITE "E1"; #DAC1_CTRL0
-../../trb3sc/scripts/compile.pl
\ No newline at end of file
+/home/adrian/git/trb3sc/scripts/compile.pl
\ No newline at end of file
+ #Familyname => 'MachXO3LF',
+ #Devicename => 'LCMXO3LF-6900C',
+ #Package => 'CABGA256',
+ #Speedgrade => '5',
+
Familyname => 'MachXO3LF',
-Devicename => 'LCMXO3LF-6900C',
-Package => 'CABGA256',
+Devicename => 'LCMXO3LF-4300E',
+Package => 'WLCSP81',
Speedgrade => '5',
TOPNAME => "thresholds",
#Include only necessary lpf files
-#pinout_file => '', #name of pin-out file, if not equal TOPNAME
+pinout_file => 'thresholds', #name of pin-out file, if not equal TOPNAME
include_TDC => 0,
include_GBE => 0,
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="efb" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2017 04 07 13:37:10.538" version="1.2" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="efb.lpc" type="lpc" modified="2017 04 07 13:37:08.000"/>
+ <File name="efb.vhd" type="top_level_vhdl" modified="2017 04 07 13:37:08.000"/>
+ <File name="efb_tmpl.vhd" type="template_vhdl" modified="2017 04 07 13:37:08.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=machxo3lf
+PartType=LCMXO3LF-6900C
+PartName=LCMXO3LF-6900C-6BG256C
+SpeedGrade=6
+Package=CABGA256
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=EFB
+CoreRevision=1.2
+ModuleName=efb
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=04/07/2017
+Time=13:37:08
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+freq=
+i2c1=0
+i2c1config=0
+i2c1_addr=7-Bit Addressing
+i2c1_ce=0
+i2c1_freq=100
+i2c1_sa=10000
+i2c1_we=0
+i2c2=0
+i2c2_addr=7-Bit Addressing
+i2c2_ce=0
+i2c2_freq=100
+i2c2_sa=10000
+i2c2_we=0
+ufm_addr=7-Bit Addressing
+ufm_sa=10000
+pll=0
+pll_cnt=1
+spi=0
+spi_clkinv=0
+spi_cs=1
+spi_en=0
+spi_freq=1
+spi_lsb=0
+spi_mode=Slave
+spi_ib=0
+spi_ph=0
+spi_hs=0
+spi_rxo=0
+spi_rxr=0
+spi_txo=0
+spi_txr=0
+spi_we=0
+static_tc=Static
+tc=0
+tc_clkinv=Positive
+tc_ctr=1
+tc_div=1
+tc_ipcap=0
+tc_mode=CTCM
+tc_ocr=32767
+tc_oflow=1
+tc_o=TOGGLE
+tc_opcomp=0
+tc_osc=0
+tc_sa_oflow=0
+tc_top=65535
+ufm=1
+wb_clk_freq=33.25
+ufm_usage=SHARED_EBR_TAG
+ufm_ebr=2014
+ufm_remain=
+mem_size=32
+ufm_start=
+ufm_init=0
+memfile=
+ufm_dt=hex
+wb=1
+
+[Command]
+cmd_line= -w -n efb -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.25 -ufm -ufm_ebr 2014 -mem_size 32 -ufm_0 -wb -dev 6900
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.0.99.2
+-- Module Version: 1.2
+--/d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n efb -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.25 -ufm -ufm_ebr 2014 -mem_size 32 -ufm_0 -wb -dev 6900
+
+-- Fri Apr 7 13:37:08 2017
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library MACHXO3L;
+use MACHXO3L.components.all;
+-- synopsys translate_on
+
+entity efb is
+ port (
+ wb_clk_i: in std_logic;
+ wb_rst_i: in std_logic;
+ wb_cyc_i: in std_logic;
+ wb_stb_i: in std_logic;
+ wb_we_i: in std_logic;
+ wb_adr_i: in std_logic_vector(7 downto 0);
+ wb_dat_i: in std_logic_vector(7 downto 0);
+ wb_dat_o: out std_logic_vector(7 downto 0);
+ wb_ack_o: out std_logic;
+ wbc_ufm_irq: out std_logic);
+end efb;
+
+architecture Structure of efb is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component EFB
+ generic (EFB_I2C1 : in String; EFB_I2C2 : in String;
+ EFB_SPI : in String; EFB_TC : in String;
+ EFB_TC_PORTMODE : in String; EFB_UFM : in String;
+ EFB_WB_CLK_FREQ : in String; DEV_DENSITY : in String;
+ UFM_INIT_PAGES : in Integer;
+ UFM_INIT_START_PAGE : in Integer;
+ UFM_INIT_ALL_ZEROS : in String;
+ UFM_INIT_FILE_NAME : in String;
+ UFM_INIT_FILE_FORMAT : in String;
+ I2C1_ADDRESSING : in String; I2C2_ADDRESSING : in String;
+ I2C1_SLAVE_ADDR : in String; I2C2_SLAVE_ADDR : in String;
+ I2C1_BUS_PERF : in String; I2C2_BUS_PERF : in String;
+ I2C1_CLK_DIVIDER : in Integer;
+ I2C2_CLK_DIVIDER : in Integer; I2C1_GEN_CALL : in String;
+ I2C2_GEN_CALL : in String; I2C1_WAKEUP : in String;
+ I2C2_WAKEUP : in String; SPI_MODE : in String;
+ SPI_CLK_DIVIDER : in Integer; SPI_LSB_FIRST : in String;
+ SPI_CLK_INV : in String; SPI_PHASE_ADJ : in String;
+ SPI_SLAVE_HANDSHAKE : in String;
+ SPI_INTR_TXRDY : in String; SPI_INTR_RXRDY : in String;
+ SPI_INTR_TXOVR : in String; SPI_INTR_RXOVR : in String;
+ SPI_WAKEUP : in String; TC_MODE : in String;
+ TC_SCLK_SEL : in String; TC_CCLK_SEL : in Integer;
+ GSR : in String; TC_TOP_SET : in Integer;
+ TC_OCR_SET : in Integer; TC_OC_MODE : in String;
+ TC_RESETN : in String; TC_TOP_SEL : in String;
+ TC_OV_INT : in String; TC_OCR_INT : in String;
+ TC_ICR_INT : in String; TC_OVERFLOW : in String;
+ TC_ICAPTURE : in String);
+ port (WBCLKI: in std_logic; WBRSTI: in std_logic;
+ WBCYCI: in std_logic; WBSTBI: in std_logic;
+ WBWEI: in std_logic; WBADRI7: in std_logic;
+ WBADRI6: in std_logic; WBADRI5: in std_logic;
+ WBADRI4: in std_logic; WBADRI3: in std_logic;
+ WBADRI2: in std_logic; WBADRI1: in std_logic;
+ WBADRI0: in std_logic; WBDATI7: in std_logic;
+ WBDATI6: in std_logic; WBDATI5: in std_logic;
+ WBDATI4: in std_logic; WBDATI3: in std_logic;
+ WBDATI2: in std_logic; WBDATI1: in std_logic;
+ WBDATI0: in std_logic; PLL0DATI7: in std_logic;
+ PLL0DATI6: in std_logic; PLL0DATI5: in std_logic;
+ PLL0DATI4: in std_logic; PLL0DATI3: in std_logic;
+ PLL0DATI2: in std_logic; PLL0DATI1: in std_logic;
+ PLL0DATI0: in std_logic; PLL0ACKI: in std_logic;
+ PLL1DATI7: in std_logic; PLL1DATI6: in std_logic;
+ PLL1DATI5: in std_logic; PLL1DATI4: in std_logic;
+ PLL1DATI3: in std_logic; PLL1DATI2: in std_logic;
+ PLL1DATI1: in std_logic; PLL1DATI0: in std_logic;
+ PLL1ACKI: in std_logic; I2C1SCLI: in std_logic;
+ I2C1SDAI: in std_logic; I2C2SCLI: in std_logic;
+ I2C2SDAI: in std_logic; SPISCKI: in std_logic;
+ SPIMISOI: in std_logic; SPIMOSII: in std_logic;
+ SPISCSN: in std_logic; TCCLKI: in std_logic;
+ TCRSTN: in std_logic; TCIC: in std_logic;
+ UFMSN: in std_logic; WBDATO7: out std_logic;
+ WBDATO6: out std_logic; WBDATO5: out std_logic;
+ WBDATO4: out std_logic; WBDATO3: out std_logic;
+ WBDATO2: out std_logic; WBDATO1: out std_logic;
+ WBDATO0: out std_logic; WBACKO: out std_logic;
+ PLLCLKO: out std_logic; PLLRSTO: out std_logic;
+ PLL0STBO: out std_logic; PLL1STBO: out std_logic;
+ PLLWEO: out std_logic; PLLADRO4: out std_logic;
+ PLLADRO3: out std_logic; PLLADRO2: out std_logic;
+ PLLADRO1: out std_logic; PLLADRO0: out std_logic;
+ PLLDATO7: out std_logic; PLLDATO6: out std_logic;
+ PLLDATO5: out std_logic; PLLDATO4: out std_logic;
+ PLLDATO3: out std_logic; PLLDATO2: out std_logic;
+ PLLDATO1: out std_logic; PLLDATO0: out std_logic;
+ I2C1SCLO: out std_logic; I2C1SCLOEN: out std_logic;
+ I2C1SDAO: out std_logic; I2C1SDAOEN: out std_logic;
+ I2C2SCLO: out std_logic; I2C2SCLOEN: out std_logic;
+ I2C2SDAO: out std_logic; I2C2SDAOEN: out std_logic;
+ I2C1IRQO: out std_logic; I2C2IRQO: out std_logic;
+ SPISCKO: out std_logic; SPISCKEN: out std_logic;
+ SPIMISOO: out std_logic; SPIMISOEN: out std_logic;
+ SPIMOSIO: out std_logic; SPIMOSIEN: out std_logic;
+ SPIMCSN7: out std_logic; SPIMCSN6: out std_logic;
+ SPIMCSN5: out std_logic; SPIMCSN4: out std_logic;
+ SPIMCSN3: out std_logic; SPIMCSN2: out std_logic;
+ SPIMCSN1: out std_logic; SPIMCSN0: out std_logic;
+ SPICSNEN: out std_logic; SPIIRQO: out std_logic;
+ TCINT: out std_logic; TCOC: out std_logic;
+ WBCUFMIRQ: out std_logic; CFGWAKE: out std_logic;
+ CFGSTDBY: out std_logic);
+ end component;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ EFBInst_0: EFB
+ generic map (UFM_INIT_FILE_FORMAT=> "HEX", UFM_INIT_FILE_NAME=> "NONE",
+ UFM_INIT_ALL_ZEROS=> "ENABLED", UFM_INIT_START_PAGE=> 2014,
+ UFM_INIT_PAGES=> 32, DEV_DENSITY=> "6900L", EFB_UFM=> "ENABLED",
+ TC_ICAPTURE=> "DISABLED", TC_OVERFLOW=> "DISABLED", TC_ICR_INT=> "OFF",
+ TC_OCR_INT=> "OFF", TC_OV_INT=> "OFF", TC_TOP_SEL=> "OFF",
+ TC_RESETN=> "ENABLED", TC_OC_MODE=> "TOGGLE", TC_OCR_SET=> 32767,
+ TC_TOP_SET=> 65535, GSR=> "ENABLED", TC_CCLK_SEL=> 1, TC_MODE=> "CTCM",
+ TC_SCLK_SEL=> "PCLOCK", EFB_TC_PORTMODE=> "WB", EFB_TC=> "DISABLED",
+ SPI_WAKEUP=> "DISABLED", SPI_INTR_RXOVR=> "DISABLED",
+ SPI_INTR_TXOVR=> "DISABLED", SPI_INTR_RXRDY=> "DISABLED",
+ SPI_INTR_TXRDY=> "DISABLED", SPI_SLAVE_HANDSHAKE=> "DISABLED",
+ SPI_PHASE_ADJ=> "DISABLED", SPI_CLK_INV=> "DISABLED",
+ SPI_LSB_FIRST=> "DISABLED", SPI_CLK_DIVIDER=> 1, SPI_MODE=> "MASTER",
+ EFB_SPI=> "DISABLED", I2C2_WAKEUP=> "DISABLED", I2C2_GEN_CALL=> "DISABLED",
+ I2C2_CLK_DIVIDER=> 1, I2C2_BUS_PERF=> "100kHz", I2C2_SLAVE_ADDR=> "0b1000010",
+ I2C2_ADDRESSING=> "7BIT", EFB_I2C2=> "DISABLED", I2C1_WAKEUP=> "DISABLED",
+ I2C1_GEN_CALL=> "DISABLED", I2C1_CLK_DIVIDER=> 1, I2C1_BUS_PERF=> "100kHz",
+ I2C1_SLAVE_ADDR=> "0b1000001", I2C1_ADDRESSING=> "7BIT",
+ EFB_I2C1=> "DISABLED", EFB_WB_CLK_FREQ=> "33.2")
+ port map (WBCLKI=>wb_clk_i, WBRSTI=>wb_rst_i, WBCYCI=>wb_cyc_i,
+ WBSTBI=>wb_stb_i, WBWEI=>wb_we_i, WBADRI7=>wb_adr_i(7),
+ WBADRI6=>wb_adr_i(6), WBADRI5=>wb_adr_i(5),
+ WBADRI4=>wb_adr_i(4), WBADRI3=>wb_adr_i(3),
+ WBADRI2=>wb_adr_i(2), WBADRI1=>wb_adr_i(1),
+ WBADRI0=>wb_adr_i(0), WBDATI7=>wb_dat_i(7),
+ WBDATI6=>wb_dat_i(6), WBDATI5=>wb_dat_i(5),
+ WBDATI4=>wb_dat_i(4), WBDATI3=>wb_dat_i(3),
+ WBDATI2=>wb_dat_i(2), WBDATI1=>wb_dat_i(1),
+ WBDATI0=>wb_dat_i(0), PLL0DATI7=>scuba_vlo,
+ PLL0DATI6=>scuba_vlo, PLL0DATI5=>scuba_vlo,
+ PLL0DATI4=>scuba_vlo, PLL0DATI3=>scuba_vlo,
+ PLL0DATI2=>scuba_vlo, PLL0DATI1=>scuba_vlo,
+ PLL0DATI0=>scuba_vlo, PLL0ACKI=>scuba_vlo,
+ PLL1DATI7=>scuba_vlo, PLL1DATI6=>scuba_vlo,
+ PLL1DATI5=>scuba_vlo, PLL1DATI4=>scuba_vlo,
+ PLL1DATI3=>scuba_vlo, PLL1DATI2=>scuba_vlo,
+ PLL1DATI1=>scuba_vlo, PLL1DATI0=>scuba_vlo,
+ PLL1ACKI=>scuba_vlo, I2C1SCLI=>scuba_vlo,
+ I2C1SDAI=>scuba_vlo, I2C2SCLI=>scuba_vlo,
+ I2C2SDAI=>scuba_vlo, SPISCKI=>scuba_vlo, SPIMISOI=>scuba_vlo,
+ SPIMOSII=>scuba_vlo, SPISCSN=>scuba_vlo, TCCLKI=>scuba_vlo,
+ TCRSTN=>scuba_vlo, TCIC=>scuba_vlo, UFMSN=>scuba_vhi,
+ WBDATO7=>wb_dat_o(7), WBDATO6=>wb_dat_o(6),
+ WBDATO5=>wb_dat_o(5), WBDATO4=>wb_dat_o(4),
+ WBDATO3=>wb_dat_o(3), WBDATO2=>wb_dat_o(2),
+ WBDATO1=>wb_dat_o(1), WBDATO0=>wb_dat_o(0), WBACKO=>wb_ack_o,
+ PLLCLKO=>open, PLLRSTO=>open, PLL0STBO=>open, PLL1STBO=>open,
+ PLLWEO=>open, PLLADRO4=>open, PLLADRO3=>open, PLLADRO2=>open,
+ PLLADRO1=>open, PLLADRO0=>open, PLLDATO7=>open,
+ PLLDATO6=>open, PLLDATO5=>open, PLLDATO4=>open,
+ PLLDATO3=>open, PLLDATO2=>open, PLLDATO1=>open,
+ PLLDATO0=>open, I2C1SCLO=>open, I2C1SCLOEN=>open,
+ I2C1SDAO=>open, I2C1SDAOEN=>open, I2C2SCLO=>open,
+ I2C2SCLOEN=>open, I2C2SDAO=>open, I2C2SDAOEN=>open,
+ I2C1IRQO=>open, I2C2IRQO=>open, SPISCKO=>open,
+ SPISCKEN=>open, SPIMISOO=>open, SPIMISOEN=>open,
+ SPIMOSIO=>open, SPIMOSIEN=>open, SPIMCSN7=>open,
+ SPIMCSN6=>open, SPIMCSN5=>open, SPIMCSN4=>open,
+ SPIMCSN3=>open, SPIMCSN2=>open, SPIMCSN1=>open,
+ SPIMCSN0=>open, SPICSNEN=>open, SPIIRQO=>open, TCINT=>open,
+ TCOC=>open, WBCUFMIRQ=>wbc_ufm_irq, CFGWAKE=>open,
+ CFGSTDBY=>open);
+
+end Structure;
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="flash" module="EFB" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2017 05 22 14:32:10.863" version="1.2" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="flash.lpc" type="lpc" modified="2017 05 22 14:32:07.000"/>
+ <File name="flash.vhd" type="top_level_vhdl" modified="2017 05 22 14:32:07.000"/>
+ <File name="flash_tmpl.vhd" type="template_vhdl" modified="2017 05 22 14:32:07.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=machxo3lf
+PartType=LCMXO3LF-4300E
+PartName=LCMXO3LF-4300E-5MG256C
+SpeedGrade=5
+Package=CSFBGA256
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=EFB
+CoreRevision=1.2
+ModuleName=flash
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=05/22/2017
+Time=14:32:07
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+freq=
+i2c1=0
+i2c1config=0
+i2c1_addr=7-Bit Addressing
+i2c1_ce=0
+i2c1_freq=100
+i2c1_sa=10000
+i2c1_we=0
+i2c2=0
+i2c2_addr=7-Bit Addressing
+i2c2_ce=0
+i2c2_freq=100
+i2c2_sa=10000
+i2c2_we=0
+ufm_addr=7-Bit Addressing
+ufm_sa=10000
+pll=0
+pll_cnt=1
+spi=0
+spi_clkinv=0
+spi_cs=1
+spi_en=0
+spi_freq=1
+spi_lsb=0
+spi_mode=Slave
+spi_ib=0
+spi_ph=0
+spi_hs=0
+spi_rxo=0
+spi_rxr=0
+spi_txo=0
+spi_txr=0
+spi_we=0
+static_tc=Static
+tc=0
+tc_clkinv=Positive
+tc_ctr=1
+tc_div=1
+tc_ipcap=0
+tc_mode=CTCM
+tc_ocr=32767
+tc_oflow=1
+tc_o=TOGGLE
+tc_opcomp=0
+tc_osc=0
+tc_sa_oflow=0
+tc_top=65535
+ufm=1
+wb_clk_freq=33.25
+ufm_usage=SHARED_EBR_TAG
+ufm_ebr=765
+ufm_remain=
+mem_size=2
+ufm_start=
+ufm_init=0
+memfile=
+ufm_dt=hex
+wb=1
+
+[Command]
+cmd_line= -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.25 -ufm -ufm_ebr 765 -mem_size 2 -ufm_0 -wb -dev 4300
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.0.99.2
+-- Module Version: 1.2
+--/home/soft/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n flash -lang vhdl -synth synplify -bus_exp 7 -bb -type efb -arch xo3c00f -freq 33.25 -ufm -ufm_ebr 765 -mem_size 2 -ufm_0 -wb -dev 4300
+
+-- Mon May 22 14:32:07 2017
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library MACHXO3L;
+use MACHXO3L.components.all;
+-- synopsys translate_on
+
+entity flash is
+ port (
+ wb_clk_i: in std_logic;
+ wb_rst_i: in std_logic;
+ wb_cyc_i: in std_logic;
+ wb_stb_i: in std_logic;
+ wb_we_i: in std_logic;
+ wb_adr_i: in std_logic_vector(7 downto 0);
+ wb_dat_i: in std_logic_vector(7 downto 0);
+ wb_dat_o: out std_logic_vector(7 downto 0);
+ wb_ack_o: out std_logic;
+ wbc_ufm_irq: out std_logic);
+end flash;
+
+architecture Structure of flash is
+
+ -- internal signal declarations
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VHI
+ port (Z: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component EFB
+ generic (EFB_I2C1 : in String; EFB_I2C2 : in String;
+ EFB_SPI : in String; EFB_TC : in String;
+ EFB_TC_PORTMODE : in String; EFB_UFM : in String;
+ EFB_WB_CLK_FREQ : in String; DEV_DENSITY : in String;
+ UFM_INIT_PAGES : in Integer;
+ UFM_INIT_START_PAGE : in Integer;
+ UFM_INIT_ALL_ZEROS : in String;
+ UFM_INIT_FILE_NAME : in String;
+ UFM_INIT_FILE_FORMAT : in String;
+ I2C1_ADDRESSING : in String; I2C2_ADDRESSING : in String;
+ I2C1_SLAVE_ADDR : in String; I2C2_SLAVE_ADDR : in String;
+ I2C1_BUS_PERF : in String; I2C2_BUS_PERF : in String;
+ I2C1_CLK_DIVIDER : in Integer;
+ I2C2_CLK_DIVIDER : in Integer; I2C1_GEN_CALL : in String;
+ I2C2_GEN_CALL : in String; I2C1_WAKEUP : in String;
+ I2C2_WAKEUP : in String; SPI_MODE : in String;
+ SPI_CLK_DIVIDER : in Integer; SPI_LSB_FIRST : in String;
+ SPI_CLK_INV : in String; SPI_PHASE_ADJ : in String;
+ SPI_SLAVE_HANDSHAKE : in String;
+ SPI_INTR_TXRDY : in String; SPI_INTR_RXRDY : in String;
+ SPI_INTR_TXOVR : in String; SPI_INTR_RXOVR : in String;
+ SPI_WAKEUP : in String; TC_MODE : in String;
+ TC_SCLK_SEL : in String; TC_CCLK_SEL : in Integer;
+ GSR : in String; TC_TOP_SET : in Integer;
+ TC_OCR_SET : in Integer; TC_OC_MODE : in String;
+ TC_RESETN : in String; TC_TOP_SEL : in String;
+ TC_OV_INT : in String; TC_OCR_INT : in String;
+ TC_ICR_INT : in String; TC_OVERFLOW : in String;
+ TC_ICAPTURE : in String);
+ port (WBCLKI: in std_logic; WBRSTI: in std_logic;
+ WBCYCI: in std_logic; WBSTBI: in std_logic;
+ WBWEI: in std_logic; WBADRI7: in std_logic;
+ WBADRI6: in std_logic; WBADRI5: in std_logic;
+ WBADRI4: in std_logic; WBADRI3: in std_logic;
+ WBADRI2: in std_logic; WBADRI1: in std_logic;
+ WBADRI0: in std_logic; WBDATI7: in std_logic;
+ WBDATI6: in std_logic; WBDATI5: in std_logic;
+ WBDATI4: in std_logic; WBDATI3: in std_logic;
+ WBDATI2: in std_logic; WBDATI1: in std_logic;
+ WBDATI0: in std_logic; PLL0DATI7: in std_logic;
+ PLL0DATI6: in std_logic; PLL0DATI5: in std_logic;
+ PLL0DATI4: in std_logic; PLL0DATI3: in std_logic;
+ PLL0DATI2: in std_logic; PLL0DATI1: in std_logic;
+ PLL0DATI0: in std_logic; PLL0ACKI: in std_logic;
+ PLL1DATI7: in std_logic; PLL1DATI6: in std_logic;
+ PLL1DATI5: in std_logic; PLL1DATI4: in std_logic;
+ PLL1DATI3: in std_logic; PLL1DATI2: in std_logic;
+ PLL1DATI1: in std_logic; PLL1DATI0: in std_logic;
+ PLL1ACKI: in std_logic; I2C1SCLI: in std_logic;
+ I2C1SDAI: in std_logic; I2C2SCLI: in std_logic;
+ I2C2SDAI: in std_logic; SPISCKI: in std_logic;
+ SPIMISOI: in std_logic; SPIMOSII: in std_logic;
+ SPISCSN: in std_logic; TCCLKI: in std_logic;
+ TCRSTN: in std_logic; TCIC: in std_logic;
+ UFMSN: in std_logic; WBDATO7: out std_logic;
+ WBDATO6: out std_logic; WBDATO5: out std_logic;
+ WBDATO4: out std_logic; WBDATO3: out std_logic;
+ WBDATO2: out std_logic; WBDATO1: out std_logic;
+ WBDATO0: out std_logic; WBACKO: out std_logic;
+ PLLCLKO: out std_logic; PLLRSTO: out std_logic;
+ PLL0STBO: out std_logic; PLL1STBO: out std_logic;
+ PLLWEO: out std_logic; PLLADRO4: out std_logic;
+ PLLADRO3: out std_logic; PLLADRO2: out std_logic;
+ PLLADRO1: out std_logic; PLLADRO0: out std_logic;
+ PLLDATO7: out std_logic; PLLDATO6: out std_logic;
+ PLLDATO5: out std_logic; PLLDATO4: out std_logic;
+ PLLDATO3: out std_logic; PLLDATO2: out std_logic;
+ PLLDATO1: out std_logic; PLLDATO0: out std_logic;
+ I2C1SCLO: out std_logic; I2C1SCLOEN: out std_logic;
+ I2C1SDAO: out std_logic; I2C1SDAOEN: out std_logic;
+ I2C2SCLO: out std_logic; I2C2SCLOEN: out std_logic;
+ I2C2SDAO: out std_logic; I2C2SDAOEN: out std_logic;
+ I2C1IRQO: out std_logic; I2C2IRQO: out std_logic;
+ SPISCKO: out std_logic; SPISCKEN: out std_logic;
+ SPIMISOO: out std_logic; SPIMISOEN: out std_logic;
+ SPIMOSIO: out std_logic; SPIMOSIEN: out std_logic;
+ SPIMCSN7: out std_logic; SPIMCSN6: out std_logic;
+ SPIMCSN5: out std_logic; SPIMCSN4: out std_logic;
+ SPIMCSN3: out std_logic; SPIMCSN2: out std_logic;
+ SPIMCSN1: out std_logic; SPIMCSN0: out std_logic;
+ SPICSNEN: out std_logic; SPIIRQO: out std_logic;
+ TCINT: out std_logic; TCOC: out std_logic;
+ WBCUFMIRQ: out std_logic; CFGWAKE: out std_logic;
+ CFGSTDBY: out std_logic);
+ end component;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ EFBInst_0: EFB
+ generic map (UFM_INIT_FILE_FORMAT=> "HEX", UFM_INIT_FILE_NAME=> "NONE",
+ UFM_INIT_ALL_ZEROS=> "ENABLED", UFM_INIT_START_PAGE=> 765,
+ UFM_INIT_PAGES=> 2, DEV_DENSITY=> "4300L", EFB_UFM=> "ENABLED",
+ TC_ICAPTURE=> "DISABLED", TC_OVERFLOW=> "DISABLED", TC_ICR_INT=> "OFF",
+ TC_OCR_INT=> "OFF", TC_OV_INT=> "OFF", TC_TOP_SEL=> "OFF",
+ TC_RESETN=> "ENABLED", TC_OC_MODE=> "TOGGLE", TC_OCR_SET=> 32767,
+ TC_TOP_SET=> 65535, GSR=> "ENABLED", TC_CCLK_SEL=> 1, TC_MODE=> "CTCM",
+ TC_SCLK_SEL=> "PCLOCK", EFB_TC_PORTMODE=> "WB", EFB_TC=> "DISABLED",
+ SPI_WAKEUP=> "DISABLED", SPI_INTR_RXOVR=> "DISABLED",
+ SPI_INTR_TXOVR=> "DISABLED", SPI_INTR_RXRDY=> "DISABLED",
+ SPI_INTR_TXRDY=> "DISABLED", SPI_SLAVE_HANDSHAKE=> "DISABLED",
+ SPI_PHASE_ADJ=> "DISABLED", SPI_CLK_INV=> "DISABLED",
+ SPI_LSB_FIRST=> "DISABLED", SPI_CLK_DIVIDER=> 1, SPI_MODE=> "MASTER",
+ EFB_SPI=> "DISABLED", I2C2_WAKEUP=> "DISABLED", I2C2_GEN_CALL=> "DISABLED",
+ I2C2_CLK_DIVIDER=> 1, I2C2_BUS_PERF=> "100kHz", I2C2_SLAVE_ADDR=> "0b1000010",
+ I2C2_ADDRESSING=> "7BIT", EFB_I2C2=> "DISABLED", I2C1_WAKEUP=> "DISABLED",
+ I2C1_GEN_CALL=> "DISABLED", I2C1_CLK_DIVIDER=> 1, I2C1_BUS_PERF=> "100kHz",
+ I2C1_SLAVE_ADDR=> "0b1000001", I2C1_ADDRESSING=> "7BIT",
+ EFB_I2C1=> "DISABLED", EFB_WB_CLK_FREQ=> "33.2")
+ port map (WBCLKI=>wb_clk_i, WBRSTI=>wb_rst_i, WBCYCI=>wb_cyc_i,
+ WBSTBI=>wb_stb_i, WBWEI=>wb_we_i, WBADRI7=>wb_adr_i(7),
+ WBADRI6=>wb_adr_i(6), WBADRI5=>wb_adr_i(5),
+ WBADRI4=>wb_adr_i(4), WBADRI3=>wb_adr_i(3),
+ WBADRI2=>wb_adr_i(2), WBADRI1=>wb_adr_i(1),
+ WBADRI0=>wb_adr_i(0), WBDATI7=>wb_dat_i(7),
+ WBDATI6=>wb_dat_i(6), WBDATI5=>wb_dat_i(5),
+ WBDATI4=>wb_dat_i(4), WBDATI3=>wb_dat_i(3),
+ WBDATI2=>wb_dat_i(2), WBDATI1=>wb_dat_i(1),
+ WBDATI0=>wb_dat_i(0), PLL0DATI7=>scuba_vlo,
+ PLL0DATI6=>scuba_vlo, PLL0DATI5=>scuba_vlo,
+ PLL0DATI4=>scuba_vlo, PLL0DATI3=>scuba_vlo,
+ PLL0DATI2=>scuba_vlo, PLL0DATI1=>scuba_vlo,
+ PLL0DATI0=>scuba_vlo, PLL0ACKI=>scuba_vlo,
+ PLL1DATI7=>scuba_vlo, PLL1DATI6=>scuba_vlo,
+ PLL1DATI5=>scuba_vlo, PLL1DATI4=>scuba_vlo,
+ PLL1DATI3=>scuba_vlo, PLL1DATI2=>scuba_vlo,
+ PLL1DATI1=>scuba_vlo, PLL1DATI0=>scuba_vlo,
+ PLL1ACKI=>scuba_vlo, I2C1SCLI=>scuba_vlo,
+ I2C1SDAI=>scuba_vlo, I2C2SCLI=>scuba_vlo,
+ I2C2SDAI=>scuba_vlo, SPISCKI=>scuba_vlo, SPIMISOI=>scuba_vlo,
+ SPIMOSII=>scuba_vlo, SPISCSN=>scuba_vlo, TCCLKI=>scuba_vlo,
+ TCRSTN=>scuba_vlo, TCIC=>scuba_vlo, UFMSN=>scuba_vhi,
+ WBDATO7=>wb_dat_o(7), WBDATO6=>wb_dat_o(6),
+ WBDATO5=>wb_dat_o(5), WBDATO4=>wb_dat_o(4),
+ WBDATO3=>wb_dat_o(3), WBDATO2=>wb_dat_o(2),
+ WBDATO1=>wb_dat_o(1), WBDATO0=>wb_dat_o(0), WBACKO=>wb_ack_o,
+ PLLCLKO=>open, PLLRSTO=>open, PLL0STBO=>open, PLL1STBO=>open,
+ PLLWEO=>open, PLLADRO4=>open, PLLADRO3=>open, PLLADRO2=>open,
+ PLLADRO1=>open, PLLADRO0=>open, PLLDATO7=>open,
+ PLLDATO6=>open, PLLDATO5=>open, PLLDATO4=>open,
+ PLLDATO3=>open, PLLDATO2=>open, PLLDATO1=>open,
+ PLLDATO0=>open, I2C1SCLO=>open, I2C1SCLOEN=>open,
+ I2C1SDAO=>open, I2C1SDAOEN=>open, I2C2SCLO=>open,
+ I2C2SCLOEN=>open, I2C2SDAO=>open, I2C2SDAOEN=>open,
+ I2C1IRQO=>open, I2C2IRQO=>open, SPISCKO=>open,
+ SPISCKEN=>open, SPIMISOO=>open, SPIMISOEN=>open,
+ SPIMOSIO=>open, SPIMOSIEN=>open, SPIMCSN7=>open,
+ SPIMCSN6=>open, SPIMCSN5=>open, SPIMCSN4=>open,
+ SPIMCSN3=>open, SPIMCSN2=>open, SPIMCSN1=>open,
+ SPIMCSN0=>open, SPICSNEN=>open, SPIIRQO=>open, TCINT=>open,
+ TCOC=>open, WBCUFMIRQ=>wbc_ufm_irq, CFGWAKE=>open,
+ CFGSTDBY=>open);
+
+end Structure;
--- /dev/null
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 05.01.2017 14:31:03
+-- Design Name:
+-- Module Name: sim_tb - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library work;
+use work.trb_net_std.all;
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity sim_tb is
+end sim_tb;
+
+architecture Behavioral of sim_tb is
+signal CLK ,Flag_Lim, Flag_LUT: std_logic := '0';
+signal DOUT : std_logic_vector(15 downto 0);
+constant CLK_PERIOD : time := 20 ns;
+
+begin
+--Input : entity work.input_env
+-- port map(
+-- CLK => CLK,
+-- DOUT => DIN_i
+-- );
+
+ thresholds : entity work.thresholds
+ port map(
+ -- CLK => CLK,
+ DAC_FLAG => '0',
+ OUTPUT => DOUT,
+ MISO_OUT =>open,
+ MOSI_IN =>'1',--: in std_logic;
+ SCLK_IN =>'1',--: in std_logic;
+ CS_IN =>'0'--: in std_logic--;
+ );
+
+
+
+ CLK_PROC : process is
+ begin
+ CLK <= '1';
+ wait for CLK_PERIOD / 2;
+ CLK <= '0';
+ wait for CLK_PERIOD / 2;
+ end process;
+
+
+
+
+
+end Behavioral;
\ No newline at end of file
#add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesis/vhdl/machxo3lf.vhd"
#add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd"
+#add file -vhdl -lib work "./test/machxo3lf.vhd"
add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
add_file -vhdl -lib work "../../dirich/code/spi_slave.vhd"
add_file -vhdl -lib work "../../logicbox/code/sedcheck.vhd"
#add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd"
#add_file -vhdl -lib work "cores/efb.vhd"
-#add_file -verilog -lib work "cores/efb_define_def.v"
+add_file -verilog -lib work "../../logicbox/cores/efb_define_def.v"
add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v"
add_file -vhdl -lib work "thresholds.vhd"
#device options
set_option -technology MACHXO3LF
-set_option -part LCMXO3LF_6900C
-set_option -package BG256C
+#set_option -part LCMXO3LF_6900C
+#set_option -package BG256C
+set_option -part LCMXO3LF_4300E
+set_option -package UWG81
set_option -speed_grade -5
set_option -part_companion ""
\r
entity thresholds is\r
port(\r
- ID : in std_logic;\r
- OUTPUT : out std_logic_vector(15 downto 0);\r
+ DAC_FLAG : in std_logic; --ID\r
+ OUTPUT : out std_logic_vector(16 downto 1);\r
MISO_OUT : out std_logic;\r
MOSI_IN : in std_logic;\r
SCLK_IN : in std_logic;\r
- CS_IN : in std_logic \r
+ CS_IN : in std_logic--;\r
+ --LED : out std_logic_vector(7 downto 0);\r
+ --DIPSW : in std_logic_vector(3 downto 0)\r
);\r
end entity;\r
\r
signal sed_debug : std_logic_vector(31 downto 0);\r
signal controlsed_i : std_logic_vector(3 downto 0);\r
\r
- signal pwm_data_i : std_logic_vector(15 downto 0);\r
- signal pwm_write_i : std_logic;\r
- signal pwm_addr_i : std_logic_vector(4 downto 0);\r
- signal pwm_data_ii : std_logic_vector(15 downto 0);\r
- signal pwm_write_ii : std_logic;\r
- signal pwm_addr_ii : std_logic_vector(4 downto 0);\r
+ signal pwm_data_i : std_logic_vector(15 downto 0):= x"6000";\r
+ signal pwm_write_i : std_logic;\r
+ signal pwm_addr_i : std_logic_vector(4 downto 0);\r
+ signal pwm_data_ii : std_logic_vector(15 downto 0);\r
+ signal pwm_write_ii : std_logic;\r
+ signal pwm_addr_ii : std_logic_vector(4 downto 0);\r
+ signal pwm_data_iii : std_logic_vector(15 downto 0);\r
+ signal pwm_write_iii : std_logic;\r
+ signal pwm_addr_iii : std_logic_vector(4 downto 0);\r
\r
-- signal flashram_reset : std_logic;\r
--signal flashram_write_i: std_logic;\r
signal flashram_data_i : std_logic_vector(7 downto 0);\r
- signal flashram_data_o : std_logic_vector(7 downto 0);\r
- signal ram_data : ram_t := (others =>("0000000000000000"));--: std_logic_vector(15 downto 0);\r
+ signal flashram_data_o : std_logic_vector(7 downto 0) := "00000010";\r
+ signal ram_data : ram_t := (others =>("0000000000100001"));--: std_logic_vector(15 downto 0);\r
--signal ram_data_o : ram_t := (others =>("0000000000000000"));--std_logic_vector(15 downto 0);\r
\r
- signal flash_command : std_logic;\r
+ signal flash_command : std_logic := '0';\r
--signal flash_page : std_logic_vector(12 downto 0);\r
- signal flash_go : std_logic;\r
+ signal flash_go : std_logic := '1';\r
signal flash_busy : std_logic;\r
signal flash_err : std_logic;\r
\r
- signal compensate_i : signed(15 downto 0);\r
- signal pwm_i : std_logic_vector(15 downto 0);\r
+ signal compensate_i : signed(15 downto 0) := (others =>'0');\r
+ signal pwm_i : std_logic_vector(16 downto 1);\r
signal ufm_bus_ready_in : std_logic;\r
signal ufm_bus_ready_out : std_logic;\r
signal ufm_databyte_counter : unsigned(14 downto 0);\r
\r
- signal ram_data_f_spi_addr : std_logic_vector( 7 downto 0);\r
- signal ram_data_f_spi_data : std_logic_vector(15 downto 0);\r
- signal ram_data_f_spi_write : std_logic;\r
+ signal ram_spi_addr : std_logic_vector( 7 downto 0);\r
+ signal ram_spi_data : std_logic_vector(15 downto 0):= "0000111100001111";\r
+ signal ram_spi_write : std_logic;\r
\r
+ signal show_flash_err : std_logic := '0';\r
+ signal ram_spi_read :std_logic := '0';\r
+ signal flash_temp : std_logic_vector(7 downto 0);\r
+ \r
+ --type state_type is (Start,IDLE,c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14,c15); --type of state machine.\r
+ --signal state: state_type := Start;\r
+ --signal init : std_logic:='1';\r
+ \r
+-- signal temp : std_logic_vector(3 downto 0):= "0000";\r
\r
component OSCH\r
generic (NOM_FREQ: string := "33.25");\r
\r
DEBUG => open\r
);\r
- \r
- \r
-PROC_REGS : process begin\r
- wait until rising_edge(clk_i);\r
- bus_ready <= '0';\r
- pwm_write_i <= '0';\r
- flash_go <= '0';\r
- ram_data_f_spi_write <= '0';\r
+\r
\r
- if pwm_write_ii = '1' then\r
- pwm_data_i <= pwm_data_ii;\r
- pwm_addr_i <= pwm_addr_ii;\r
- pwm_write_i <= pwm_write_ii;\r
- \r
- elsif bus_read = '1' then\r
- bus_ready <= '1';\r
- if spi_addr >= x"10" and spi_addr < x"20" then \r
- spi_tx_data <= ram_data(to_integer(unsigned(spi_addr)));\r
+-- count : process (clk_i)\r
+-- begin\r
+-- if rising_edge(clk_i) then\r
+-- if temp="1001" then\r
+-- temp<="0000";\r
+-- else\r
+-- temp <= std_logic_vector(unsigned(temp) + 1);\r
+-- end if;\r
+-- end if;\r
+-- \r
+-- end process;\r
+ \r
+-- state_machine : process (clk_i)\r
+-- begin\r
+-- if rising_edge(clk_i) then\r
+-- pwm_write_i <= '0';\r
+-- --pwm_data_i <= x"6000";\r
+-- case state is\r
+-- when Start => --when current state is "s0"\r
+-- if init = '1' then\r
+-- pwm_write_i <= '0';\r
+-- state <= c0;\r
+-- end if;\r
+-- \r
+-- when c0 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "00000";\r
+-- state <= c1;\r
+-- \r
+-- when c1 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "00001";\r
+-- state <= c2;\r
+-- \r
+-- when c2 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "00010";\r
+-- state <= c3;\r
+-- \r
+-- when c3 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "00011";\r
+-- state <= c4;\r
+-- \r
+-- when c4 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "00100";\r
+-- state <= c5;\r
+-- \r
+-- when c5 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "00101";\r
+-- state <= c6;\r
+-- \r
+-- when c6 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "00110";\r
+-- state <= c7;\r
+-- \r
+-- when c7 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "00111";\r
+-- state <= c8;\r
+-- \r
+-- when c8 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "01000";\r
+-- state <= c9;\r
+-- \r
+-- when c9 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "01001";\r
+-- state <= c10;\r
+-- \r
+-- when c10 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "01010";\r
+-- state <= c11;\r
+-- \r
+-- when c11 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "01011";\r
+-- state <= c12;\r
+-- \r
+-- when c12 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "01100";\r
+-- state <= c13;\r
+-- \r
+-- when c13 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "01101";\r
+-- state <= c14;\r
+-- \r
+-- when c14 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "01110";\r
+-- state <= c15;\r
+-- \r
+-- when c15 => pwm_write_i <= '1';\r
+-- pwm_addr_i <= "01111";\r
+-- init <= '0';\r
+-- state <= IDLE;\r
+-- init <= '0';\r
+-- \r
+-- when IDLE => pwm_write_i <= pwm_write_ii;\r
+-- pwm_addr_i <= pwm_addr_ii;\r
+-- pwm_data_i <= pwm_data_ii;\r
+-- \r
+-- end case;\r
+-- \r
+-- end if;\r
+-- end process;\r
+\r
+\r
+PWM_select : process begin\r
+ wait until rising_edge(clk_i);\r
+ \r
+ pwm_write_i <= '0';\r
+ if pwm_write_ii = '1' then\r
+ pwm_data_i <= pwm_data_ii;\r
+ pwm_addr_i <= pwm_addr_ii;\r
+ pwm_write_i <= pwm_write_ii;\r
else\r
- case spi_addr is\r
- when x"30" => spi_tx_data <= std_logic_vector(compensate_i);\r
- when x"ee" => spi_tx_data <= sed_debug(15 downto 0);\r
- when x"ef" => spi_tx_data <= sed_debug(31 downto 16);\r
- when others => null;\r
- end case;\r
+ pwm_data_i <= pwm_data_iii;\r
+ pwm_addr_i <= pwm_addr_iii;\r
+ pwm_write_i <= pwm_write_iii;\r
end if;\r
+\r
+end process;\r
+\r
\r
- elsif bus_write = '1' then\r
- if spi_addr < x"10" then -- 0 to 15 0x00 to 0x10 -- write directly to pwm\r
- if flash_busy = '0' or flash_command = '0' then -- avoid conflict with writing from flash\r
- pwm_data_i <= spi_rx_data(15 downto 0);\r
- pwm_addr_i <= spi_addr(4 downto 0);\r
- pwm_write_i <= '1';\r
- end if;\r
- elsif spi_addr >= x"10" and spi_addr < x"20" then -- write to ram\r
- --ram_data(to_integer(unsigned(spi_addr(3 downto 0)))) <= spi_rx_data; \r
- ram_data_f_spi_write <= '1';\r
- ram_data_f_spi_addr <= spi_addr;\r
- ram_data_f_spi_data <= spi_rx_data;\r
- else\r
- case spi_addr is\r
- -- when x"20" => flash_command <= spi_rx_data(0); --read/write to flash;\r
- -- flash_go <= '1';\r
- when x"30" => compensate_i <= spi_rx_data(15 downto 0);--signed(uart_rx_data(15 downto 0);\r
- when x"ee" => controlsed_i <= spi_rx_data(3 downto 0);\r
- end case;\r
+PROC_REGS : process begin\r
+ wait until rising_edge(clk_i);\r
+ bus_ready <= '0';\r
+ pwm_write_iii <= '0';\r
+ flash_go <= '0';\r
+ ram_spi_write <= '0';\r
+ ram_spi_read <= '0';\r
+ \r
+ if bus_read = '1' then\r
+ bus_ready <= '1';\r
+\r
+ if (spi_addr >= x"10") and (spi_addr < X"20") then\r
+ spi_tx_data <= ram_data(to_integer(unsigned(spi_addr(4 downto 0)))); -- Read RAM\r
+ else\r
+ case spi_addr is\r
+ --when x"10" => spi_tx_data <= reg_spi_o(15 downto 0);\r
+ --when x"11" => spi_tx_data <= reg_spi_o(31 downto 16);\r
+ when x"ee" => spi_tx_data <= sed_debug(15 downto 0);\r
+ when x"ef" => spi_tx_data <= sed_debug(31 downto 16);\r
+ -- \r
+ when others => null;\r
+ end case; \r
+ end if;\r
+ elsif bus_write = '1' then\r
+ if (spi_addr >= x"00") and (spi_addr < x"10") then -- write directly to PWM\r
+ pwm_data_iii <= spi_rx_data;\r
+ pwm_addr_iii <= spi_addr(4 downto 0);\r
+ pwm_write_iii <= '1';\r
+ elsif ( spi_addr >= x"10") and (spi_addr < x"20") then -- write to RAM\r
+ ram_spi_data(15 downto 0) <= spi_rx_data;\r
+ ram_spi_write <= '1';\r
+ ram_spi_addr <= "0000" & spi_addr(3 downto 0);\r
+ pwm_data_iii <= spi_rx_data;\r
+ pwm_addr_iii <= spi_addr(4 downto 0);\r
+ pwm_write_iii <= '1';\r
+ else\r
+ case spi_addr is\r
+ when x"20" => flash_command <= '1'; --write to flash;\r
+ flash_go <= '1';\r
+ when x"21" => flash_command <= '0'; --read from flash;\r
+ flash_go <= '1';\r
+ when x"22" => compensate_i <= signed(spi_rx_data(15 downto 0));--signed(uart_rx_data(15 downto 0);\r
+ when x"ee" => controlsed_i <= spi_rx_data(3 downto 0);\r
+ when others => null;\r
+ end case;\r
+ end if;\r
end if; \r
- end if;\r
end process;\r
\r
+-- ManSel : process begin\r
+-- wait until rising_edge(clk_i);\r
+-- flash_go <= '0';\r
+-- ram_spi_write <= '0';\r
+-- --ram_spi_read <= '0';\r
+-- if pwm_write_ii = '1' then\r
+-- pwm_data_i <= pwm_data_ii;\r
+-- pwm_addr_i <= pwm_addr_ii;\r
+-- pwm_write_i <= pwm_write_ii;\r
+-- elsif DIPSW(0) = '0' then\r
+-- case DIPSW(3 downto 1) is\r
+-- when "000" => ram_spi_data(15 downto 0) <= "1100011100111000";\r
+-- ram_spi_write <= '1';\r
+-- ram_spi_addr <= "00000" & DIPSW(3 downto 1);\r
+-- --when "010" => ram_spi_read <= '1';\r
+-- when "011" => flash_command <= '0'; --read from flash;\r
+-- flash_go <= '1';\r
+-- when "100" => flash_command <= '1'; --write to flash;\r
+-- flash_go <= '1';\r
+-- when "101" => ram_spi_data(15 downto 0) <= "0000011000101010";\r
+-- ram_spi_write <= '1';\r
+-- ram_spi_addr <= "00000" & DIPSW(3 downto 1);\r
+-- when others => null;\r
+-- end case;\r
+-- else \r
+-- LED <= not ram_data(to_integer(unsigned(DIPSW(3 downto 1))))(7 downto 0);\r
+-- end if;\r
+-- \r
+-- \r
+-- end process;\r
+\r
\r
THE_SED : entity work.sedcheck\r
port map(\r
); \r
\r
--TODO connect to output according to ID\r
-OUTPUT <= pwm_i;\r
-\r
+process(pwm_i,DAC_FLAG)\r
+ begin\r
+ if DAC_FLAG = '1' then\r
+ OUTPUT <= pwm_i;\r
+ else\r
+ OUTPUT(1) <= pwm_i(15);\r
+ OUTPUT(2) <= pwm_i(13);\r
+ OUTPUT(3) <= pwm_i(8);\r
+ OUTPUT(4) <= pwm_i(5);\r
+ OUTPUT(5) <= pwm_i(16);\r
+ OUTPUT(6) <= pwm_i(4);\r
+ OUTPUT(7) <= pwm_i(3);\r
+ OUTPUT(8) <= pwm_i(6);\r
+ OUTPUT(9) <= pwm_i(2);\r
+ OUTPUT(10) <= pwm_i(1);\r
+ OUTPUT(11) <= pwm_i(7);\r
+ OUTPUT(12) <= pwm_i(9);\r
+ OUTPUT(13) <= pwm_i(14);\r
+ OUTPUT(14) <= pwm_i(12);\r
+ OUTPUT(15) <= pwm_i(10);\r
+ OUTPUT(16) <= pwm_i(11); \r
+ \r
+ end if;\r
+ end process; \r
\r
\r
---------------------------------------------------------------------------\r
-- Flash Controller\r
--------------------------------------------------------------------------- \r
\r
---THE_UFM : entity work.UFM_control\r
--- generic map(\r
--- NO_DATAPAGES => 2,\r
--- UFM_STARTPAGE => "00"&x"00"\r
--- )\r
--- port map(\r
--- CLK => clk_i,\r
--- CMD => flash_command,\r
--- GO => flash_go,\r
--- BUSY => flash_busy,\r
--- RESET => '0',\r
--- DATA_IN => flashram_data_i,\r
--- DATA_OUT => flashram_data_o,\r
--- DATABYTE_COUNTER => ufm_databyte_counter, --specifies current databyte \r
--- BUS_READY_IN => ufm_bus_ready_in,\r
--- BUS_READY_OUT => ufm_bus_ready_out,\r
--- FLASH_ERROR => flash_err\r
--- );\r
-\r
+THE_UFM : entity work.UFM_control\r
+ generic map(\r
+ NO_DATAPAGES => 2,\r
+ UFM_STARTPAGE => "00"&x"00"\r
+ )\r
+ port map(\r
+ CLK => clk_i,\r
+ CMD => flash_command,\r
+ GO => flash_go,\r
+ BUSY => flash_busy,\r
+ RESET => '0',\r
+ DATA_IN => flashram_data_i,\r
+ DATA_OUT => flashram_data_o,\r
+ DATABYTE_COUNTER => ufm_databyte_counter, --specifies current databyte \r
+ BUS_READY_IN => ufm_bus_ready_in,\r
+ BUS_READY_OUT => ufm_bus_ready_out,\r
+ FLASH_ERROR => flash_err\r
+ );\r
\r
---PROC_REGS_FLASH: process begin\r
---wait until rising_edge( clk_i );\r
+ \r
+-- PROC_REGS_FLASH: process begin\r
+-- wait until rising_edge( clk_i );\r
-- ufm_bus_ready_in <= '0';\r
-- pwm_write_ii <= '0';\r
--- if flash_command = '0' and ufm_bus_ready_out = '1' then\r
--- -- copy data from UFM to registers\r
--- ufm_bus_ready_in <= '1';\r
--- case to_integer ( ufm_databyte_counter ) is\r
--- when 0 => ram_data( 0)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 1 => ram_data( 0)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "00000";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 2 => ram_data( 1)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 3 => ram_data( 1)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "00001";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 4 => ram_data( 2)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 5 => ram_data( 2)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "00010";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 6 => ram_data( 3)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 7 => ram_data( 3)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "00011";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 8 => ram_data( 4)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 9 => ram_data( 4)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "00100";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 10 => ram_data( 5)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 11 => ram_data( 5)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "00101";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 12 => ram_data( 6)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 13 => ram_data( 6)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "00110";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 14 => ram_data( 7)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 15 => ram_data( 7)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "00111";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 16 => ram_data( 8)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 17 => ram_data( 8)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "01000";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 18 => ram_data( 9)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 19 => ram_data( 9)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "01001";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 20 => ram_data(10)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 21 => ram_data(10)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "01010";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 22 => ram_data(11)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 23 => ram_data(11)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "01011";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 24 => ram_data(12)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 25 => ram_data(12)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "01100";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 26 => ram_data(13)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 27 => ram_data(13)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "01101";\r
--- pwm_data_ii( 15 downto 8) <= flashram_data_o;\r
--- when 28 => ram_data(14)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 29 => ram_data(14)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "01110";\r
--- pwm_data_ii(15 downto 8) <= flashram_data_o;\r
--- when 30 => ram_data(15)( 7 downto 0) <= flashram_data_o;\r
--- pwm_write_ii <= '0';\r
--- pwm_data_ii( 7 downto 0) <= flashram_data_o;\r
--- when 31 => ram_data(15)(15 downto 8) <= flashram_data_o;\r
--- pwm_write_ii <= '1';\r
--- pwm_addr_ii <= "01111";\r
--- pwm_data_ii(15 downto 8) <= flashram_data_o;\r
+-- \r
+-- if flash_command = '0' and ufm_bus_ready_out = '1' then\r
+-- -- copy data from UFM to registers\r
+-- ufm_bus_ready_in <= '1';\r
+-- case to_integer ( ufm_databyte_counter ) is\r
+-- when 0 => ram_temp <= flashram_data_o;\r
+-- when 1 => ram_data(0)(15 downto 0) <= flashram_data_o & ram_temp;\r
+-- when 2 => ram_temp <= flashram_data_o;\r
+-- when 3 => ram_data(1)(15 downto 0) <= flashram_data_o & ram_temp;\r
-- when others => null;\r
-- end case ;\r
-- \r
-- -- save data from registers to UFM\r
-- ufm_bus_ready_in <= '1';\r
-- case to_integer ( ufm_databyte_counter ) is\r
--- when 0 => flashram_data_i <= ram_data( 0)( 7 downto 0);\r
--- when 1 => flashram_data_i <= ram_data( 0)(15 downto 8);\r
--- when 2 => flashram_data_i <= ram_data( 1)( 7 downto 0);\r
--- when 3 => flashram_data_i <= ram_data( 1)(15 downto 8);\r
--- when 4 => flashram_data_i <= ram_data( 2)( 7 downto 0);\r
--- when 5 => flashram_data_i <= ram_data( 2)(15 downto 8);\r
--- when 6 => flashram_data_i <= ram_data( 3)( 7 downto 0);\r
--- when 7 => flashram_data_i <= ram_data( 3)(15 downto 8);\r
--- when 8 => flashram_data_i <= ram_data( 4)( 7 downto 0);\r
--- when 9 => flashram_data_i <= ram_data( 4)(15 downto 8);\r
--- when 10 => flashram_data_i <= ram_data( 5)( 7 downto 0);\r
--- when 11 => flashram_data_i <= ram_data( 5)(15 downto 8);\r
--- when 12 => flashram_data_i <= ram_data( 6)( 7 downto 0);\r
--- when 13 => flashram_data_i <= ram_data( 6)(15 downto 8);\r
--- when 14 => flashram_data_i <= ram_data( 7)( 7 downto 0);\r
--- when 15 => flashram_data_i <= ram_data( 7)(15 downto 8);\r
--- when 16 => flashram_data_i <= ram_data( 8)( 7 downto 0);\r
--- when 17 => flashram_data_i <= ram_data( 8)(15 downto 8);\r
--- when 18 => flashram_data_i <= ram_data( 9)( 7 downto 0);\r
--- when 19 => flashram_data_i <= ram_data( 9)(15 downto 8);\r
--- when 20 => flashram_data_i <= ram_data(10)( 7 downto 0);\r
--- when 21 => flashram_data_i <= ram_data(10)(15 downto 8);\r
--- when 22 => flashram_data_i <= ram_data(11)( 7 downto 0);\r
--- when 23 => flashram_data_i <= ram_data(11)(15 downto 8);\r
--- when 24 => flashram_data_i <= ram_data(12)( 7 downto 0);\r
--- when 25 => flashram_data_i <= ram_data(12)(15 downto 8);\r
--- when 26 => flashram_data_i <= ram_data(13)( 7 downto 0);\r
--- when 27 => flashram_data_i <= ram_data(13)(15 downto 8);\r
--- when 28 => flashram_data_i <= ram_data(14)( 7 downto 0);\r
--- when 29 => flashram_data_i <= ram_data(14)(15 downto 8);\r
--- when 30 => flashram_data_i <= ram_data(15)( 7 downto 0);\r
--- when 31 => flashram_data_i <= ram_data(15)(15 downto 8);\r
+-- when 0 => flashram_data_i <= ram_data(1)( 7 downto 0);\r
+-- when 1 => flashram_data_i <= ram_data(1)(15 downto 8);\r
+-- --when 2 => flashram_data_i <= ram_data(1)( 7 downto 0);\r
+-- --when 3 => flashram_data_i <= ram_data(1)(15 downto 8);\r
-- when others => null ;\r
-- end case ;\r
-- \r
-- elsif ram_data_f_spi_write = '1' then\r
--- ram_data(to_integer(unsigned(ram_data_f_spi_addr))) <= ram_data_f_spi_data;\r
+-- ram_data(1) <= reg_spi;\r
+-- elsif ram_data_f_spi_read = '1' then\r
+-- reg_spi_o <= ram_data(1);\r
-- end if ;\r
--- end process ;\r
+ \r
+ \r
+\r
+PROC_REGS_FLASH: process begin\r
+wait until rising_edge( clk_i );\r
+ ufm_bus_ready_in <= '0';\r
+ pwm_write_ii <= '0';\r
+ if flash_command = '0' and ufm_bus_ready_out = '1' then\r
+ -- copy data from UFM to registers\r
+ ufm_bus_ready_in <= '1';\r
+ case to_integer ( ufm_databyte_counter ) is\r
+ when 0 => flash_temp <= flashram_data_o;\r
+ when 1 => ram_data( 0) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "00000";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 2 => flash_temp <= flashram_data_o;\r
+ when 3 => ram_data( 1) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "00001";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 4 => flash_temp <= flashram_data_o;\r
+ when 5 => ram_data( 2) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "00010";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 6 => flash_temp <= flashram_data_o;\r
+ when 7 => ram_data( 3) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "00011";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 8 => flash_temp <= flashram_data_o;\r
+ when 9 => ram_data( 4) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "00100";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 10 => flash_temp <= flashram_data_o;\r
+ when 11 => ram_data( 5) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "00101";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 12 => flash_temp <= flashram_data_o;\r
+ when 13 => ram_data( 6) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "00110";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 14 => flash_temp <= flashram_data_o;\r
+ when 15 => ram_data( 7) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "00111";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 16 => flash_temp <= flashram_data_o;\r
+ when 17 => ram_data( 8) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "01000";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 18 => flash_temp <= flashram_data_o;\r
+ when 19 => ram_data( 9) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "01001";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 20 => flash_temp <= flashram_data_o;\r
+ when 21 => ram_data(10) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "01010";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 22 => flash_temp <= flashram_data_o;\r
+ when 23 => ram_data(11) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "01011";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 24 => flash_temp <= flashram_data_o;\r
+ when 25 => ram_data(12) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "01100";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 26 => flash_temp <= flashram_data_o;\r
+ when 27 => ram_data(13) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "01101";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 28 => flash_temp <= flashram_data_o;\r
+ when 29 => ram_data(14) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "01110";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when 30 => flash_temp <= flashram_data_o;\r
+ when 31 => ram_data(15) <= flashram_data_o & flash_temp;\r
+ pwm_write_ii <= '1';\r
+ pwm_addr_ii <= "01111";\r
+ pwm_data_ii <= flashram_data_o & flash_temp;\r
+ when others => null;\r
+ end case ;\r
+ \r
+ elsif flash_command = '1' and ufm_bus_ready_out = '1' then\r
+ -- save data from registers to UFM\r
+ ufm_bus_ready_in <= '1';\r
+ case to_integer ( ufm_databyte_counter ) is\r
+ when 0 => flashram_data_i <= ram_data( 0)( 7 downto 0);\r
+ when 1 => flashram_data_i <= ram_data( 0)(15 downto 8);\r
+ when 2 => flashram_data_i <= ram_data( 1)( 7 downto 0);\r
+ when 3 => flashram_data_i <= ram_data( 1)(15 downto 8);\r
+ when 4 => flashram_data_i <= ram_data( 2)( 7 downto 0);\r
+ when 5 => flashram_data_i <= ram_data( 2)(15 downto 8);\r
+ when 6 => flashram_data_i <= ram_data( 3)( 7 downto 0);\r
+ when 7 => flashram_data_i <= ram_data( 3)(15 downto 8);\r
+ when 8 => flashram_data_i <= ram_data( 4)( 7 downto 0);\r
+ when 9 => flashram_data_i <= ram_data( 4)(15 downto 8);\r
+ when 10 => flashram_data_i <= ram_data( 5)( 7 downto 0);\r
+ when 11 => flashram_data_i <= ram_data( 5)(15 downto 8);\r
+ when 12 => flashram_data_i <= ram_data( 6)( 7 downto 0);\r
+ when 13 => flashram_data_i <= ram_data( 6)(15 downto 8);\r
+ when 14 => flashram_data_i <= ram_data( 7)( 7 downto 0);\r
+ when 15 => flashram_data_i <= ram_data( 7)(15 downto 8);\r
+ when 16 => flashram_data_i <= ram_data( 8)( 7 downto 0);\r
+ when 17 => flashram_data_i <= ram_data( 8)(15 downto 8);\r
+ when 18 => flashram_data_i <= ram_data( 9)( 7 downto 0);\r
+ when 19 => flashram_data_i <= ram_data( 9)(15 downto 8);\r
+ when 20 => flashram_data_i <= ram_data(10)( 7 downto 0);\r
+ when 21 => flashram_data_i <= ram_data(10)(15 downto 8);\r
+ when 22 => flashram_data_i <= ram_data(11)( 7 downto 0);\r
+ when 23 => flashram_data_i <= ram_data(11)(15 downto 8);\r
+ when 24 => flashram_data_i <= ram_data(12)( 7 downto 0);\r
+ when 25 => flashram_data_i <= ram_data(12)(15 downto 8);\r
+ when 26 => flashram_data_i <= ram_data(13)( 7 downto 0);\r
+ when 27 => flashram_data_i <= ram_data(13)(15 downto 8);\r
+ when 28 => flashram_data_i <= ram_data(14)( 7 downto 0);\r
+ when 29 => flashram_data_i <= ram_data(14)(15 downto 8);\r
+ when 30 => flashram_data_i <= ram_data(15)( 7 downto 0);\r
+ when 31 => flashram_data_i <= ram_data(15)(15 downto 8);\r
+ when others => null ;\r
+ end case ;\r
+ \r
+ elsif ram_spi_write = '1' then\r
+ ram_data(to_integer(unsigned(ram_spi_addr))) <= ram_spi_data;\r
+ end if ;\r
+end process ;\r
\r
\r
\r
jspc29 / dirich.git / commitdiff