TAOD : inout std_logic; --address or data
TACK : in std_logic; --MB address
CMS : out std_logic; --common stop
+ COM_STOP : in std_logic; --common stop input from transceiner
TDST : inout std_logic; --data strobe
GDE : out std_logic; --global disable
RDYI : out std_logic; --ready TO first motherboard token out to MB (on AddOn RDM)
RES : out std_logic; -- TDC working mode
TOK : out std_logic; -- TDC working mode
WRM : out std_logic; -- TDC working mode
- TAD : inout std_logic_vector(8 downto 0) --TAD 8 downto 0
+ TAD : inout std_logic_vector(8 downto 0) --TAD 8 downto 0
);
end entity;
-
architecture mdc_oepb_arch of mdc_oepb is
signal CLK_100 : std_logic;
signal reset_mdc_addon_daq_bus_0, pulse_reset_internal_logic : std_logic;
+
+ signal cms_select_in_i: std_logic_vector (3 downto 0);
+ signal a_cms_i : std_logic;
+
+-- signal input_parity_gen : std_logic_vector(9 downto 0);
+
+ type tt is array (3000 downto 0) of std_logic_vector(3 downto 0);
+-- signal data_in, data_out : tt;
+
+-- --signal counter_data : unsigned(35 downto 0);
+-- signal counter_data : std_logic_vector(35 downto 0);
+ signal out_shift_reg : tt;
+ signal out_shift_reg1 : std_logic_vector(3 downto 0);
+ signal temp_led0, temp_led1, temp_led2, temp_led3 : std_logic;
+
+
begin
+
+
---------------------------------------------------------------------
-- PLL: 100 MHz
---------------------------------------------------------------------
---------------------------------------------------------------------
API: trb_net16_endpoint_hades_full
generic map(
- REGIO_NUM_STAT_REGS => 3,
- REGIO_NUM_CTRL_REGS => 3,
+ REGIO_NUM_STAT_REGS => 3,--4, --16 stat reg
+ REGIO_NUM_CTRL_REGS => 3,--3, --8 cotrol reg
--standard values for output registers
REGIO_INIT_CTRL_REGS => (others => '0'),
--set to 0 for unused ctrl registers to save resources
IPU_ERROR_PATTERN_IN => IPU_ERROR_PATTERN_IN,
-- Slow Control Data Port
- REGIO_COMMON_STAT_REG_IN => REGIO_COMMON_STAT_REG_IN,
- REGIO_COMMON_CTRL_REG_OUT => REGIO_COMMON_CTRL_REG_OUT,
- REGIO_REGISTERS_IN => REGIO_REGISTERS_IN,
- REGIO_REGISTERS_OUT => REGIO_REGISTERS_OUT,
+ REGIO_COMMON_STAT_REG_IN => REGIO_COMMON_STAT_REG_IN, --0x00
+ REGIO_COMMON_CTRL_REG_OUT => REGIO_COMMON_CTRL_REG_OUT, --0x20
+ REGIO_REGISTERS_IN => REGIO_REGISTERS_IN, --start 0x80
+ REGIO_REGISTERS_OUT => REGIO_REGISTERS_OUT, --start 0xc0
--following ports only used when using internal data port
REGIO_ADDR_OUT => REGIO_ADDR_OUT,
-- 0xc0 0x0000 -> select verbose mode data
-- 0xc0 0x1000 -> select compact mode data
-- 0xc0 0x2000 -> select test data
+
+-- 0xc0 0xABC2000 -> x"ABC" test data number
+
+-- 0xc0 0x10000000 -> x"1" external cms
+-- 0xc0 0x00000000 -> x"0" internal generated cms
+
+-------------------------------------------------------------------------------
+-- Select Internal or external common stop
+-------------------------------------------------------------------------------
+CMS <= COM_STOP when (cms_select_in_i = x"1") else a_cms_i;
+
+
-- 0xc0 0xABCD2000 -> x"ABCD" test data number
+
PROC_GEN_TIMING : process(CLK_100)
begin
if rising_edge(CLK_100) then
motherboard_type_in_i <= REGIO_REGISTERS_OUT(7 downto 4);
cal_trigger_register_in_i <= x"000" & REGIO_REGISTERS_OUT(11 downto 8);
- data_type_select_in_i <= REGIO_REGISTERS_OUT(31 downto 12);
+ data_type_select_in_i <= REGIO_REGISTERS_OUT(27 downto 12);
+ cms_select_in_i <= REGIO_REGISTERS_OUT(31 downto 28);
end if;
end process;
+
+-- <= REGIO_REGISTERS_OUT(32); --bit 0 of 0xc1
+-- REGIO_REGISTERS_OUT(64); --bit 0 of 0xc2 multiply
+--
+
PULSE_TRIGGER : edge_to_pulse
port map (
CLOCK => CLK_100,
SIGNAL_IN => REGIO_REGISTERS_OUT(0),
PULSE_OUT => pulse_begin_run_trigger_i);
- test_pseudo_signal_i <= (pulse_pseudo_timing_trigger and LVL1_TRG_RELEASE_IN)
+ test_pseudo_signal_i <= (pulse_pseudo_timing_trigger and LVL1_TRG_RELEASE_IN)
when (debug_trigger_distributor_i(3 downto 0) = x"1") else '0';
THE_TRIG_DISTR : trigger_distributor
A_ADS_1 => '0',
A_ADS_2 => '0',
A_ACK => TACK,
- A_CMS => CMS,
+ A_CMS => a_cms_i, --CMS,
A_RDM => RDYI,--out to MB
A_GDE => GDE,
A_RDO => TRDYO,--in
-------------------------------------------------------------------------------
-- DATA MULTIPLEXER for INOUT DST, AOD,TAD
-------------------------------------------------------------------------------
- process(direction_data_line_out_i,
- a_add_configuration_i, a_aod_configuration_i,
- a_dst_configuration_i)
- begin
- --CONFIGURATION or CALIBRATION
- if (direction_data_line_out_i = x"D") then
- TAOD <= a_aod_configuration_i;
- TDST <= a_dst_configuration_i;
- TAD <= a_add_configuration_i;
- --DATA TAKING
- else
- TAOD <= 'Z';
- TDST <= 'Z';
- TAD <= (others => 'Z');
- end if;
- end process;
-
-
- process(CLK_100)
- begin
- if rising_edge(CLK_100) then
- if direction_data_line_out_i = x"D" then
- a_add_data_i <= (others => '0');
- a_aod_data_i <= '0';
- a_dst_data_i <= '0';
+ process(direction_data_line_out_i,
+ a_add_configuration_i, a_aod_configuration_i,
+ a_dst_configuration_i)
+ begin
+ --CONFIGURATION or CALIBRATION
+ if (direction_data_line_out_i = x"D") then
+ TAOD <= a_aod_configuration_i;
+ TDST <= a_dst_configuration_i;
+ TAD <= a_add_configuration_i;
+ --DATA TAKING
else
- a_add_data_i <= TAD;
- a_aod_data_i <= TAOD;
- a_dst_data_i <= TDST;
+ TAOD <= 'Z';
+ TDST <= 'Z';
+ TAD <= (others => 'Z');
end if;
- end if;
- end process;
+ end process;
+
+ process(CLK_100)
+ begin
+ if rising_edge(CLK_100) then
+ if (direction_data_line_out_i = x"D") then
+ a_add_data_i <= (others => '0');
+ a_aod_data_i <= '0';
+ a_dst_data_i <= '0';
+ else
+ a_add_data_i <= TAD;
+ a_aod_data_i <= TAOD;
+ a_dst_data_i <= TDST;
+ end if;
+ end if;
+ end process;
+
+-------------------------------------------------------------------------------
+-- pin not used input for fpga
+-------------------------------------------------------------------------------
+-- TENR <= 'Z';
+-- TDRB <= 'Z';
+-- TENB <= 'Z';
+-- TDRE <= 'Z';
+-- TCDE_0 <= 'Z';
+-- TADS0 <= 'Z';
+-- TADS_1 <= 'Z';
+-- TOR <= 'Z';
+-- TDRA <= 'Z';
+
+-- ADI_0 <= 'Z';
+-- ADI_1 <= 'Z';
---------------------------------------------------------------------
-- LED
---------------------------------------------------------------------
-- STAT_DEBUG(48 downto 41) <= last_rx_fifo_dout;
-- STAT_DEBUG(63 downto 49) <= (others => '0');
+-------------------------------------------------------------------------------
+-- test power consumption
+-------------------------------------------------------------------------------
+-- PARITYGEN : oddParityGen
+-- generic map(width => 10)
+-- port map (
+-- CLK => CLK_100,
+-- ad => input_parity_gen,
+-- oddParity => D(4)
+-- );
+
+-- input_parity_gen(9 downto 8) <= (others => '1');
+-- input_parity_gen(7 downto 4) <= direction_data_line_out_i;
+-- input_parity_gen(3 downto 0) <= x"a";
+
+-- parallel_FIFO : for i in 1 to 2 generate
+
+
+-- DATA : fifo_8192depth_36width_dual_thresh_reg_out
+-- port map (
+-- Data => (others => '1'),--counter_data,
+-- Clock => CLK,
+-- WrEn => counter_data(0),
+-- RdEn => counter_data(5),
+-- Reset => reset_internal,
+-- AmEmptyThresh => "0000000000100",
+-- AmFullThresh => "1110000000000",
+-- Q => data_out(i),
+-- WCNT => open,
+-- Empty => open,
+-- Full => open,
+-- AlmostEmpty => open,
+-- AlmostFull => open);
+
+-- end generate;
+
+--counter_data_conv <= conv_std_logic_vector(counter_data);
+
+-- D(4) <= data_out(1)(5) and data_out(2)(15);-- and data_out(3)(16);
+
+-- process(CLK_100, reset_internal)
+-- begin
+-- if rising_edge(CLK_100) then
+-- if (reset_internal = '1' or counter_data = x"00fff4E20" ) then
+-- counter_data <= (others => '0');
+-- elsif (counter_data < x"0ffff4E20") then
+-- counter_data <= counter_data + 1;
+-- else
+-- counter_data <= counter_data;
+-- end if;
+-- end if;
+-- end process;
+
+-- SHIFT_TEST : for i in 1 to 2999 generate
+
+-- TEST: xor2test
+-- port map (
+-- Clock => CLK_100,
+-- L => motherboard_type_in_i(0),
+-- w => motherboard_type_in_i(0),
+-- Output => out_shift_reg(i),
+-- Input => motherboard_type_in_i(3 downto 0));
+
+-- end generate;
+
+
+-- TEST1: xor2test
+-- port map (
+-- Clock => CLK_100,
+-- L => motherboard_type_in_i(2),
+-- w => motherboard_type_in_i(3),
+-- Output => out_shift_reg1,
+-- Input => cal_trigger_register_in_i(3 downto 0));
+
+
+-- process(CLK_100)
+-- begin
+-- if rising_edge(CLK_100) then
+-- for i in 1 to 2999 loop
+-- temp_led0 <= out_shift_reg(i)(3) or out_shift_reg(i+1)(0) or out_shift_reg1(1);
+-- temp_led1 <= out_shift_reg(i)(2) and out_shift_reg(i+1)(1) and out_shift_reg1(2);
+-- temp_led2 <= out_shift_reg(i)(1) or out_shift_reg(i+1)(2) or out_shift_reg1(3);
+-- temp_led3 <= out_shift_reg(i)(0) and out_shift_reg(i+1)(3) and out_shift_reg1(0);
+-- end loop;
+-- end if;
+-- end process;
+
+-- D(4) <= temp_led0;
+-- D(3) <= temp_led1;
+-- D(2) <= temp_led2;
+-- D(1) <= temp_led3;
+
+
+
end architecture;
jspc29 / mdcoep.git / commitdiff