Change downlink fibers from A(1..9) to D(4..12)

This puts all downlinks and the uplink on the same MTP connectors again,
so that a single MTP pair can be used for all RICH links in mCBM 2021.

diff --git a/hub_test/constrs/hub_test.xdc b/hub_test/constrs/hub_test.xdc
index 371928350fe289d25dd1b5b4afeb62d8846d9d45..190d9a66ba0a61ed6544a36ccd287088f6bf23b9 100644 (file)
--- a/hub_test/constrs/hub_test.xdc
+++ b/hub_test/constrs/hub_test.xdc
@@ -38,8 +38,8 @@ set_property IOSTANDARD LVCMOS18 [get_ports PEX_I2C_SEL1]
 set_property PACKAGE_PIN B34 [get_ports UC_RESET_N]
 set_property IOSTANDARD LVCMOS18 [get_ports UC_RESET_N]
 
-set_property PACKAGE_PIN AK37 [get_ports MGTREFCLK0P_127]
-create_clock -period 10.000 -name MGTREFCLK0P_127 [get_ports MGTREFCLK0P_127]
+set_property PACKAGE_PIN N6 [get_ports MGTREFCLK0P_232]
+create_clock -period 10.000 -name MGTREFCLK0P_232 [get_ports MGTREFCLK0P_232]
 
 set_property PACKAGE_PIN R6 [get_ports MGTREFCLK0P_231]
 create_clock -period 5.000 -name MGTREFCLK0P_231 [get_ports MGTREFCLK0P_231]
@@ -62,14 +62,14 @@ set_property IOSTANDARD LVDS [get_ports TRG_OUT_2_P]
 set_property PACKAGE_PIN AT29 [get_ports TRG_OUT_3_P]
 set_property IOSTANDARD LVDS [get_ports TRG_OUT_3_P]
 
-set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[0].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
-set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[1].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
-set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[2].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
-set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[3].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
-set_property LOC GTHE3_CHANNEL_X0Y15 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[4].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
-set_property LOC GTHE3_CHANNEL_X0Y14 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[5].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
-set_property LOC GTHE3_CHANNEL_X0Y12 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[6].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
-set_property LOC GTHE3_CHANNEL_X0Y13 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[7].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
-set_property LOC GTHE3_CHANNEL_X0Y10 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[8].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
-
-set_property LOC GTHE3_CHANNEL_X1Y29 [get_cells -hierarchical -filter {NAME =~ THE_UPLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
\ No newline at end of file
+set_property LOC GTHE3_CHANNEL_X1Y31 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[0].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
+set_property LOC GTHE3_CHANNEL_X1Y34 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[1].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
+set_property LOC GTHE3_CHANNEL_X1Y32 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[2].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
+set_property LOC GTHE3_CHANNEL_X1Y35 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[3].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
+set_property LOC GTHE3_CHANNEL_X1Y33 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[4].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
+set_property LOC GTHE3_CHANNEL_X1Y37 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[5].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
+set_property LOC GTHE3_CHANNEL_X1Y39 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[6].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
+set_property LOC GTHE3_CHANNEL_X1Y38 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[7].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
+set_property LOC GTHE3_CHANNEL_X1Y36 [get_cells -hierarchical -filter {NAME =~ generate_downlinks[8].THE_DOWNLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]
+
+set_property LOC GTHE3_CHANNEL_X1Y29 [get_cells -hierarchical -filter {NAME =~ THE_UPLINK/*/gthe3_channel_gen.gen_gthe3_channel_inst[0].GTHE3_CHANNEL_PRIM_INST}]

diff --git a/hub_test/src/hub_test.vhd b/hub_test/src/hub_test.vhd
index 1fcc5a79d24fb67c825f6686967561ecf214ba3d..7ace9528da5a54d5e681f42282cb7b0e38dffb8c 100644 (file)
--- a/hub_test/src/hub_test.vhd
+++ b/hub_test/src/hub_test.vhd
@@ -33,8 +33,8 @@ entity hub_test is
         PEX_I2C_SEL1          : out   std_logic;
         UC_RESET_N            : out   std_logic;
 
-        MGTREFCLK0P_127       : in    std_logic; -- 100 MHz, sync. with SI5345_OUT7_P
-        MGTREFCLK0N_127       : in    std_logic;
+        MGTREFCLK0P_232       : in    std_logic; -- 100 MHz, sync. with SI5345_OUT7_P
+        MGTREFCLK0N_232       : in    std_logic;
 
         MGTREFCLK0P_231       : in    std_logic; -- 200 MHz, free-running
         MGTREFCLK0N_231       : in    std_logic;
@@ -239,21 +239,21 @@ begin
         clk_in1_n => SI5345_OUT7_N
     );
 
-    THE_MGTREFCLK0_127 : IBUFDS_GTE3
+    THE_MGTREFCLK0_232 : IBUFDS_GTE3
     generic map (
         REFCLK_EN_TX_PATH  => '0',
         REFCLK_HROW_CK_SEL => "00",
         REFCLK_ICNTL_RX    => "00"
     )
     port map (
-        I     => MGTREFCLK0P_127,
-        IB    => MGTREFCLK0N_127,
+        I     => MGTREFCLK0P_232,
+        IB    => MGTREFCLK0N_232,
         CEB   => mb_sysclk_reset,
         O     => mgtrefclk_downlink,
         ODIV2 => mgtrefclk_downlink_hrow
     );
 
-    BUFG_GT_MGTREFCLK0_127 : BUFG_GT
+    BUFG_GT_MGTREFCLK0_232 : BUFG_GT
     port map (
         O       => mgtrefclk_downlink_bufg,
         CE      => '1',
@@ -421,8 +421,8 @@ begin
             RX_DLM_WORD       => open,
             TX_DLM            => dlm,
             TX_DLM_WORD       => x"00",
-            SD_LOS_IN         => mpod_a_los(linknum),
-            SD_TXDIS_OUT      => mpod_a_txdis(linknum),
+            SD_LOS_IN         => mpod_d_los(linknum + 3),
+            SD_TXDIS_OUT      => mpod_d_txdis(linknum + 3),
             STAT_DEBUG        => open,
             CTRL_DEBUG        => (others => '0')
         );