*** empty log message ***

diff --git a/special/handler_data.vhd b/special/handler_data.vhd
index 3217daac483e2d6ec36f2c55d9b4742708492852..a33781a74e2d3a72d0acb88f8f811dd06eeb7594 100644 (file)
--- a/special/handler_data.vhd
+++ b/special/handler_data.vhd
@@ -52,7 +52,6 @@ entity handler_data is
     --Status
     STAT_DATA_BUFFER_LEVEL       : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
     STAT_HEADER_BUFFER_LEVEL     : out std_logic_vector(31 downto 0);
-
     --Debug
     DEBUG_OUT                    : out std_logic_vector(31 downto 0)
     );
@@ -141,6 +140,7 @@ architecture handler_data_arch of handler_data is
   signal flag_half_full            : std_logic_vector(DATA_INTERFACE_NUMBER-1 downto 0);
   signal flag_almost_full_combined : std_logic;
   signal flag_half_full_combined   : std_logic;
+  
 
 
 begin

diff --git a/special/handler_trigger_and_data.vhd b/special/handler_trigger_and_data.vhd
index 42860f48faea386009fc6e744b1ef90e606fc7dc..5dfa2acae3ba32ee355b666447cc901911a08e01 100644 (file)
--- a/special/handler_trigger_and_data.vhd
+++ b/special/handler_trigger_and_data.vhd
@@ -64,6 +64,13 @@ entity handler_trigger_and_data is
     STAT_DATA_BUFFER_LEVEL       : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0);
     STAT_HEADER_BUFFER_LEVEL     : out std_logic_vector(31 downto 0);
     STATUS_OUT                   : out std_logic_vector(127 downto 0);
+    TIMER_TICKS_IN               : in  std_logic_vector(1 downto 0);
+    STATISTICS_DATA_OUT          : out std_logic_vector(31 downto 0);
+    STATISTICS_ADDR_IN           : in  std_logic_vector(4 downto 0);
+    STATISTICS_READY_OUT         : out std_logic;
+    STATISTICS_READ_IN           : in  std_logic;
+    STATISTICS_ADDR_IN           : in  std_logic;
+    STATISTICS_UNKNOWN_OUT       : out std_logic;
 
     --Debug
     DEBUG_DATA_HANDLER_OUT       : out std_logic_vector(31 downto 0);
@@ -84,6 +91,14 @@ end entity;
 
 architecture handler_trigger_and_data_arch of handler_trigger_and_data is
 
+  type cnt24_DAT_t        is array (DATA_INTERFACE_NUMBER-1 downto 0) of unsigned(23 downto 0);
+  signal timer_fifo_almost_full    : cnt24_DAT_t;
+  signal timer_ipu_idle         : unsigned(23 downto 0);
+  signal timer_ipu_waiting      : unsigned(23 downto 0);
+  signal timer_ipu_working      : unsigned(23 downto 0);  
+  signal timer_lvl1_almost_full : unsigned(23 downto 0);  
+  signal timer_lvl1_idle        : unsigned(23 downto 0);  
+  signal timer_lvl1_working     : unsigned(23 downto 0);  
 
   signal fee_timing_trigger      : std_logic;
   signal fee_trg_received        : std_logic;
@@ -241,6 +256,81 @@ begin
   DEBUG_IPU_HANDLER_OUT          <= status_ipu_handler_i;
   DEBUG_DATA_HANDLER_OUT         <= debug_data_handler_i;
 
+
+-----------------------------------------------------------------------
+-- Statistics
+-----------------------------------------------------------------------
+    the_stat_proc : process(CLK)
+      begin
+        if rising_edge(CLK) then
+          gen_buffer_stat : for i in 0 to DATA_INTERFACE_NUMBER-1 loop
+            if STAT_DATA_BUFFER_LEVEL(i*32+17) = '1' and TIMER_TICKS_IN(0) = '1' then
+              timer_fifo_almost_full(i) <= timer_fifo_almost_full(i) + to_unsigned(1,1);
+            end if;
+          end loop;
+          if STAT_HEADER_BUFFER_LEVEL(17) = '1' and TIMER_TICKS_IN(0) = '1' then
+            timer_lvl1_almost_full <= timer_lvl1_almost_full(0) + to_unsigned(1,1);
+          end if;
+          if STAT_HEADER_BUFFER_LEVEL(20) = '1' and TIMER_TICKS_IN(0) = '1' then
+            timer_lvl1_idle <= timer_lvl1_idle + to_unsigned(1,1);
+          end if;
+          if (STAT_HEADER_BUFFER_LEVEL(21) = '1' or STAT_HEADER_BUFFER_LEVEL(22) = '1') and TIMER_TICKS_IN(0) = '1' then
+            timer_lvl1_working <= timer_lvl1_working + to_unsigned(1,1);
+          end if;
+        end if;
+      end process;
+
+    the_ipu_stat_proc : process(CLK)
+      begin
+        if rising_edge(CLK) then
+          if (status_ipu_handler_i(3 downto 0) = x"0")
+              and TIMER_TICKS_IN(0) = '1' then
+            timer_ipu_idle <= timer_ipu_idle + to_unsigned(1,1);
+          end if;
+          if (status_ipu_handler_i(3 downto 0) = x"2" or status_ipu_handler_i(3 downto 0) = x"3" or status_ipu_handler_i(3 downto 0) = x"4")
+              and (status_ipu_handler_i(7) = '1' or status_ipu_handler_i(6) = '0')
+              and TIMER_TICKS_IN(0) = '1' then
+            timer_ipu_working <= timer_ipu_working + to_unsigned(1,1);
+          end if;
+          if status_ipu_handler_i(6) = '1' and status_ipu_handler_i(7) = '0' and TIMER_TICKS_IN(0) = '1' then
+            timer_ipu_waiting <= timer_ipu_waiting + to_unsigned(1,1);
+          end if;
+        end if;
+      end process;        
+
+  proc_read_stat : process(CLK)
+    variable addr : integer range 0 to 31;
+    begin
+      if rising_edge(CLK) then
+        addr := integer(to_unsigned(STATISTICS_ADDR_IN));
+        if STATISTICS_READ_IN = '1' then
+          if addr < DATA_INTERFACE_NUMBER then
+            STATISTICS_DATA_OUT    <= x"00" & timer_fifo_almost_full(addr);
+            STATISTICS_READY_OUT   <= '1';
+            STATISTICS_UNKNOWN_OUT <= '0';
+          elsif addr >= 16 and addr <= 21 then
+            case addr is
+              when 16 => STATISTICS_DATA_OUT    <= x"00" &  timer_lvl1_almost_full;
+              when 17 => STATISTICS_DATA_OUT    <= x"00" &  timer_lvl1_idle;
+              when 18 => STATISTICS_DATA_OUT    <= x"00" &  timer_lvl1_working;
+              when 19 => STATISTICS_DATA_OUT    <= x"00" &  timer_ipu_idle;
+              when 20 => STATISTICS_DATA_OUT    <= x"00" &  timer_ipu_working;
+              when 21 => STATISTICS_DATA_OUT    <= x"00" &  timer_ipu_waiting;
+            end case;
+            STATISTICS_READY_OUT   <= '1';
+            STATISTICS_UNKNOWN_OUT <= '0';
+          else
+            STATISTICS_READY_OUT   <= '0';
+            STATISTICS_UNKNOWN_OUT <= '1';
+          end if;
+        else
+          STATISTICS_READY_OUT <= '0';
+          STATISTICS_UNKNOWN_OUT <= '0';
+        end if;
+      end if;
+    end process;    
+   
+      
 -----------------------------------------------------------------------
 -- Debug
 -----------------------------------------------------------------------