+++ /dev/null
--- VHDL netlist generated by SCUBA Diamond_2.1_Production (100)
--- Module Version: 5.4
---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 32 -depth 4 -rdata_width 32 -regout -no_enable -pe -1 -pf -1 -e
-
--- Sun Dec 1 06:07:38 2013
-
-library IEEE;
-use IEEE.std_logic_1164.all;
--- synopsys translate_off
-library ecp3;
-use ecp3.components.all;
--- synopsys translate_on
-
-entity fifo_ts_32to32_dc is
- port (
- Data: in std_logic_vector(31 downto 0);
- WrClock: in std_logic;
- RdClock: in std_logic;
- WrEn: in std_logic;
- RdEn: in std_logic;
- Reset: in std_logic;
- RPReset: in std_logic;
- Q: out std_logic_vector(31 downto 0);
- Empty: out std_logic;
- Full: out std_logic);
-end fifo_ts_32to32_dc;
-
-architecture Structure of fifo_ts_32to32_dc is
-
- -- internal signal declarations
- signal invout_1: std_logic;
- signal invout_0: std_logic;
- signal w_gdata_0: std_logic;
- signal w_gdata_1: std_logic;
- signal wptr_0: std_logic;
- signal wptr_1: std_logic;
- signal wptr_2: std_logic;
- signal r_gdata_0: std_logic;
- signal r_gdata_1: std_logic;
- signal rptr_0: std_logic;
- signal rptr_1: std_logic;
- signal rptr_2: std_logic;
- signal w_gcount_0: std_logic;
- signal w_gcount_1: std_logic;
- signal w_gcount_2: std_logic;
- signal r_gcount_0: std_logic;
- signal r_gcount_1: std_logic;
- signal r_gcount_2: std_logic;
- signal w_gcount_r20: std_logic;
- signal w_gcount_r0: std_logic;
- signal w_gcount_r21: std_logic;
- signal w_gcount_r1: std_logic;
- signal w_gcount_r22: std_logic;
- signal w_gcount_r2: std_logic;
- signal r_gcount_w20: std_logic;
- signal r_gcount_w0: std_logic;
- signal r_gcount_w21: std_logic;
- signal r_gcount_w1: std_logic;
- signal r_gcount_w22: std_logic;
- signal r_gcount_w2: std_logic;
- signal empty_i: std_logic;
- signal rRst: std_logic;
- signal full_i: std_logic;
- signal iwcount_0: std_logic;
- signal iwcount_1: std_logic;
- signal w_gctr_ci: std_logic;
- signal iwcount_2: std_logic;
- signal co1: std_logic;
- signal wcount_2: std_logic;
- signal co0: std_logic;
- signal scuba_vhi: std_logic;
- signal ircount_0: std_logic;
- signal ircount_1: std_logic;
- signal r_gctr_ci: std_logic;
- signal ircount_2: std_logic;
- signal co1_1: std_logic;
- signal rcount_2: std_logic;
- signal co0_1: std_logic;
- signal rden_i: std_logic;
- signal cmp_ci: std_logic;
- signal wcount_r0: std_logic;
- signal wcount_r1: std_logic;
- signal rcount_0: std_logic;
- signal rcount_1: std_logic;
- signal co0_2: std_logic;
- signal empty_cmp_clr: std_logic;
- signal empty_cmp_set: std_logic;
- signal empty_d: std_logic;
- signal empty_d_c: std_logic;
- signal wren_i: std_logic;
- signal cmp_ci_1: std_logic;
- signal rcount_w0: std_logic;
- signal rcount_w1: std_logic;
- signal wcount_0: std_logic;
- signal wcount_1: std_logic;
- signal co0_3: std_logic;
- signal full_cmp_clr: std_logic;
- signal full_cmp_set: std_logic;
- signal full_d: std_logic;
- signal full_d_c: std_logic;
- signal scuba_vlo: std_logic;
-
- -- local component declarations
- component AGEB2
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; GE: out std_logic);
- end component;
- component AND2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component CU2
- port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
- CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
- end component;
- component FADD2B
- port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
- B1: in std_logic; CI: in std_logic; COUT: out std_logic;
- S0: out std_logic; S1: out std_logic);
- end component;
- component FD1P3BX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- PD: in std_logic; Q: out std_logic);
- end component;
- component FD1P3DX
- port (D: in std_logic; SP: in std_logic; CK: in std_logic;
- CD: in std_logic; Q: out std_logic);
- end component;
- component FD1S3BX
- port (D: in std_logic; CK: in std_logic; PD: in std_logic;
- Q: out std_logic);
- end component;
- component FD1S3DX
- port (D: in std_logic; CK: in std_logic; CD: in std_logic;
- Q: out std_logic);
- end component;
- component INV
- port (A: in std_logic; Z: out std_logic);
- end component;
- component OR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component ROM16X1A
- generic (INITVAL : in std_logic_vector(15 downto 0));
- port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
- AD0: in std_logic; DO0: out std_logic);
- end component;
- component VHI
- port (Z: out std_logic);
- end component;
- component VLO
- port (Z: out std_logic);
- end component;
- component XOR2
- port (A: in std_logic; B: in std_logic; Z: out std_logic);
- end component;
- component PDPW16KC
- generic (GSR : in String; CSDECODE_R : in String;
- CSDECODE_W : in String; REGMODE : in String;
- DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer);
- port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic;
- DI3: in std_logic; DI4: in std_logic; DI5: in std_logic;
- DI6: in std_logic; DI7: in std_logic; DI8: in std_logic;
- DI9: in std_logic; DI10: in std_logic; DI11: in std_logic;
- DI12: in std_logic; DI13: in std_logic;
- DI14: in std_logic; DI15: in std_logic;
- DI16: in std_logic; DI17: in std_logic;
- DI18: in std_logic; DI19: in std_logic;
- DI20: in std_logic; DI21: in std_logic;
- DI22: in std_logic; DI23: in std_logic;
- DI24: in std_logic; DI25: in std_logic;
- DI26: in std_logic; DI27: in std_logic;
- DI28: in std_logic; DI29: in std_logic;
- DI30: in std_logic; DI31: in std_logic;
- DI32: in std_logic; DI33: in std_logic;
- DI34: in std_logic; DI35: in std_logic;
- ADW0: in std_logic; ADW1: in std_logic;
- ADW2: in std_logic; ADW3: in std_logic;
- ADW4: in std_logic; ADW5: in std_logic;
- ADW6: in std_logic; ADW7: in std_logic;
- ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic;
- BE2: in std_logic; BE3: in std_logic; CEW: in std_logic;
- CLKW: in std_logic; CSW0: in std_logic;
- CSW1: in std_logic; CSW2: in std_logic;
- ADR0: in std_logic; ADR1: in std_logic;
- ADR2: in std_logic; ADR3: in std_logic;
- ADR4: in std_logic; ADR5: in std_logic;
- ADR6: in std_logic; ADR7: in std_logic;
- ADR8: in std_logic; ADR9: in std_logic;
- ADR10: in std_logic; ADR11: in std_logic;
- ADR12: in std_logic; ADR13: in std_logic;
- CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic;
- CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic;
- DO0: out std_logic; DO1: out std_logic;
- DO2: out std_logic; DO3: out std_logic;
- DO4: out std_logic; DO5: out std_logic;
- DO6: out std_logic; DO7: out std_logic;
- DO8: out std_logic; DO9: out std_logic;
- DO10: out std_logic; DO11: out std_logic;
- DO12: out std_logic; DO13: out std_logic;
- DO14: out std_logic; DO15: out std_logic;
- DO16: out std_logic; DO17: out std_logic;
- DO18: out std_logic; DO19: out std_logic;
- DO20: out std_logic; DO21: out std_logic;
- DO22: out std_logic; DO23: out std_logic;
- DO24: out std_logic; DO25: out std_logic;
- DO26: out std_logic; DO27: out std_logic;
- DO28: out std_logic; DO29: out std_logic;
- DO30: out std_logic; DO31: out std_logic;
- DO32: out std_logic; DO33: out std_logic;
- DO34: out std_logic; DO35: out std_logic);
- end component;
- attribute MEM_LPC_FILE : string;
- attribute MEM_INIT_FILE : string;
- attribute RESETMODE : string;
- attribute GSR : string;
- attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_ts_32to32_dc.lpc";
- attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is "";
- attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC";
- attribute GSR of FF_31 : label is "ENABLED";
- attribute GSR of FF_30 : label is "ENABLED";
- attribute GSR of FF_29 : label is "ENABLED";
- attribute GSR of FF_28 : label is "ENABLED";
- attribute GSR of FF_27 : label is "ENABLED";
- attribute GSR of FF_26 : label is "ENABLED";
- attribute GSR of FF_25 : label is "ENABLED";
- attribute GSR of FF_24 : label is "ENABLED";
- attribute GSR of FF_23 : label is "ENABLED";
- attribute GSR of FF_22 : label is "ENABLED";
- attribute GSR of FF_21 : label is "ENABLED";
- attribute GSR of FF_20 : label is "ENABLED";
- attribute GSR of FF_19 : label is "ENABLED";
- attribute GSR of FF_18 : label is "ENABLED";
- attribute GSR of FF_17 : label is "ENABLED";
- attribute GSR of FF_16 : label is "ENABLED";
- attribute GSR of FF_15 : label is "ENABLED";
- attribute GSR of FF_14 : label is "ENABLED";
- attribute GSR of FF_13 : label is "ENABLED";
- attribute GSR of FF_12 : label is "ENABLED";
- attribute GSR of FF_11 : label is "ENABLED";
- attribute GSR of FF_10 : label is "ENABLED";
- attribute GSR of FF_9 : label is "ENABLED";
- attribute GSR of FF_8 : label is "ENABLED";
- attribute GSR of FF_7 : label is "ENABLED";
- attribute GSR of FF_6 : label is "ENABLED";
- attribute GSR of FF_5 : label is "ENABLED";
- attribute GSR of FF_4 : label is "ENABLED";
- attribute GSR of FF_3 : label is "ENABLED";
- attribute GSR of FF_2 : label is "ENABLED";
- attribute GSR of FF_1 : label is "ENABLED";
- attribute GSR of FF_0 : label is "ENABLED";
- attribute syn_keep : boolean;
- attribute NGD_DRC_MASK : integer;
- attribute NGD_DRC_MASK of Structure : architecture is 1;
-
-begin
- -- component instantiation statements
- AND2_t6: AND2
- port map (A=>WrEn, B=>invout_1, Z=>wren_i);
-
- INV_1: INV
- port map (A=>full_i, Z=>invout_1);
-
- AND2_t5: AND2
- port map (A=>RdEn, B=>invout_0, Z=>rden_i);
-
- INV_0: INV
- port map (A=>empty_i, Z=>invout_0);
-
- OR2_t4: OR2
- port map (A=>Reset, B=>RPReset, Z=>rRst);
-
- XOR2_t3: XOR2
- port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0);
-
- XOR2_t2: XOR2
- port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1);
-
- XOR2_t1: XOR2
- port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0);
-
- XOR2_t0: XOR2
- port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1);
-
- LUT4_7: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>wcount_r1);
-
- LUT4_6: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21,
- AD1=>w_gcount_r22, AD0=>scuba_vlo, DO0=>wcount_r0);
-
- LUT4_5: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, AD1=>scuba_vlo,
- AD0=>scuba_vlo, DO0=>rcount_w1);
-
- LUT4_4: ROM16X1A
- generic map (initval=> X"6996")
- port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21,
- AD1=>r_gcount_w22, AD0=>scuba_vlo, DO0=>rcount_w0);
-
- LUT4_3: ROM16X1A
- generic map (initval=> X"0410")
- port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22,
- AD0=>scuba_vlo, DO0=>empty_cmp_set);
-
- LUT4_2: ROM16X1A
- generic map (initval=> X"1004")
- port map (AD3=>rptr_2, AD2=>rcount_2, AD1=>w_gcount_r22,
- AD0=>scuba_vlo, DO0=>empty_cmp_clr);
-
- LUT4_1: ROM16X1A
- generic map (initval=> X"0140")
- port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22,
- AD0=>scuba_vlo, DO0=>full_cmp_set);
-
- LUT4_0: ROM16X1A
- generic map (initval=> X"4001")
- port map (AD3=>wptr_2, AD2=>wcount_2, AD1=>r_gcount_w22,
- AD0=>scuba_vlo, DO0=>full_cmp_clr);
-
- pdp_ram_0_0_0: PDPW16KC
- generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED",
- REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36)
- port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3),
- DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7),
- DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11),
- DI12=>Data(12), DI13=>Data(13), DI14=>Data(14),
- DI15=>Data(15), DI16=>Data(16), DI17=>Data(17),
- DI18=>Data(18), DI19=>Data(19), DI20=>Data(20),
- DI21=>Data(21), DI22=>Data(22), DI23=>Data(23),
- DI24=>Data(24), DI25=>Data(25), DI26=>Data(26),
- DI27=>Data(27), DI28=>Data(28), DI29=>Data(29),
- DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo,
- DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo,
- ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>scuba_vlo, ADW3=>scuba_vlo,
- ADW4=>scuba_vlo, ADW5=>scuba_vlo, ADW6=>scuba_vlo,
- ADW7=>scuba_vlo, ADW8=>scuba_vlo, BE0=>scuba_vhi,
- BE1=>scuba_vhi, BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i,
- CLKW=>WrClock, CSW0=>scuba_vhi, CSW1=>scuba_vlo,
- CSW2=>scuba_vlo, ADR0=>scuba_vlo, ADR1=>scuba_vlo,
- ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo,
- ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>scuba_vlo, ADR8=>scuba_vlo,
- ADR9=>scuba_vlo, ADR10=>scuba_vlo, ADR11=>scuba_vlo,
- ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>scuba_vhi,
- CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo,
- CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19),
- DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24),
- DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29),
- DO12=>Q(30), DO13=>Q(31), DO14=>open, DO15=>open, DO16=>open,
- DO17=>open, DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), DO21=>Q(3),
- DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), DO26=>Q(8),
- DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), DO30=>Q(12),
- DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), DO34=>Q(16),
- DO35=>Q(17));
-
- FF_31: FD1P3BX
- port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset,
- Q=>wcount_0);
-
- FF_30: FD1P3DX
- port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_1);
-
- FF_29: FD1P3DX
- port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wcount_2);
-
- FF_28: FD1P3DX
- port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_0);
-
- FF_27: FD1P3DX
- port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_1);
-
- FF_26: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>w_gcount_2);
-
- FF_25: FD1P3DX
- port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_0);
-
- FF_24: FD1P3DX
- port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_1);
-
- FF_23: FD1P3DX
- port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset,
- Q=>wptr_2);
-
- FF_22: FD1P3BX
- port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst,
- Q=>rcount_0);
-
- FF_21: FD1P3DX
- port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_1);
-
- FF_20: FD1P3DX
- port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rcount_2);
-
- FF_19: FD1P3DX
- port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_0);
-
- FF_18: FD1P3DX
- port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_1);
-
- FF_17: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>r_gcount_2);
-
- FF_16: FD1P3DX
- port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_0);
-
- FF_15: FD1P3DX
- port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_1);
-
- FF_14: FD1P3DX
- port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst,
- Q=>rptr_2);
-
- FF_13: FD1S3DX
- port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0);
-
- FF_12: FD1S3DX
- port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1);
-
- FF_11: FD1S3DX
- port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2);
-
- FF_10: FD1S3DX
- port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0);
-
- FF_9: FD1S3DX
- port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1);
-
- FF_8: FD1S3DX
- port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2);
-
- FF_7: FD1S3DX
- port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r20);
-
- FF_6: FD1S3DX
- port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r21);
-
- FF_5: FD1S3DX
- port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset,
- Q=>w_gcount_r22);
-
- FF_4: FD1S3DX
- port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20);
-
- FF_3: FD1S3DX
- port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21);
-
- FF_2: FD1S3DX
- port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22);
-
- FF_1: FD1S3BX
- port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i);
-
- FF_0: FD1S3DX
- port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i);
-
- w_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open,
- S1=>open);
-
- w_gctr_0: CU2
- port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0,
- NC0=>iwcount_0, NC1=>iwcount_1);
-
- w_gctr_1: CU2
- port map (CI=>co0, PC0=>wcount_2, PC1=>scuba_vlo, CO=>co1,
- NC0=>iwcount_2, NC1=>open);
-
- scuba_vhi_inst: VHI
- port map (Z=>scuba_vhi);
-
- r_gctr_cia: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
- B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open,
- S1=>open);
-
- r_gctr_0: CU2
- port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1,
- NC0=>ircount_0, NC1=>ircount_1);
-
- r_gctr_1: CU2
- port map (CI=>co0_1, PC0=>rcount_2, PC1=>scuba_vlo, CO=>co1_1,
- NC0=>ircount_2, NC1=>open);
-
- empty_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i,
- CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open);
-
- empty_cmp_0: AGEB2
- port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0,
- B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2);
-
- empty_cmp_1: AGEB2
- port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr,
- B1=>scuba_vlo, CI=>co0_2, GE=>empty_d_c);
-
- a0: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d,
- S1=>open);
-
- full_cmp_ci_a: FADD2B
- port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i,
- CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open);
-
- full_cmp_0: AGEB2
- port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0,
- B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3);
-
- full_cmp_1: AGEB2
- port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr,
- B1=>scuba_vlo, CI=>co0_3, GE=>full_d_c);
-
- scuba_vlo_inst: VLO
- port map (Z=>scuba_vlo);
-
- a1: FADD2B
- port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo,
- B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d,
- S1=>open);
-
- Empty <= empty_i;
- Full <= full_i;
-end Structure;
-
--- synopsys translate_off
-library ecp3;
-configuration Structure_CON of fifo_ts_32to32_dc is
- for Structure
- for all:AGEB2 use entity ecp3.AGEB2(V); end for;
- for all:AND2 use entity ecp3.AND2(V); end for;
- for all:CU2 use entity ecp3.CU2(V); end for;
- for all:FADD2B use entity ecp3.FADD2B(V); end for;
- for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for;
- for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for;
- for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for;
- for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for;
- for all:INV use entity ecp3.INV(V); end for;
- for all:OR2 use entity ecp3.OR2(V); end for;
- for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for;
- for all:VHI use entity ecp3.VHI(V); end for;
- for all:VLO use entity ecp3.VLO(V); end for;
- for all:XOR2 use entity ecp3.XOR2(V); end for;
- for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for;
- end for;
-end Structure_CON;
-
--- synopsys translate_on
port(
CLK_IN : in std_logic;
RESET_IN : in std_logic;
- NX_DATA_CLK_TEST_IN : in std_logic;
TRIGGER_IN : in std_logic;
-- nXyter Ports
-- Outputs
NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0);
ADC_DATA_OUT : out std_logic_vector(11 downto 0);
- NEW_DATA_OUT : out std_logic;
+ DATA_CLK_OUT : out std_logic;
-- Slave bus
SLV_READ_IN : in std_logic;
architecture Behavioral of nx_data_receiver is
- -- Clock Check
- signal counter_nx_domain : unsigned(7 downto 0);
- signal counter_nx_ref_domain : unsigned(7 downto 0);
- signal counter_nx_diff : unsigned(7 downto 0);
-
-----------------------------------------------------------------------------
-- NX_TIMESTAMP_CLK Domain
-----------------------------------------------------------------------------
- -- FIFO DC Input Handler
- signal nx_fifo_write_enable : std_logic;
- signal nx_timestamp_fff : std_logic_vector(7 downto 0);
- signal nx_timestamp_ff : std_logic_vector(7 downto 0);
- signal nx_fifo_full : std_logic;
- signal nx_fifo_delay : unsigned(3 downto 0);
- signal nx_fifo_reset : std_logic;
-
-- NX_TIMESTAMP_IN Process
- signal frame_byte_ctr : unsigned(1 downto 0);
- signal nx_frame_word : std_logic_vector(31 downto 0);
- signal nx_new_frame : std_logic;
+ signal nx_frame_word_ff : std_logic_vector(7 downto 0);
+ signal nx_frame_word_f : std_logic_vector(7 downto 0);
+ signal nx_frame_word_t : std_logic_vector(31 downto 0);
+ signal nx_frame_clk_t : std_logic;
+ signal nx_frame_word_coded : std_logic_vector(31 downto 0);
+ signal nx_frame_clk_coded : std_logic;
-- Frame Sync Process
signal frame_byte_pos : unsigned(1 downto 0);
-
+
-- RS Sync FlipFlop
signal nx_frame_synced : std_logic;
signal rs_sync_set : std_logic;
signal rs_sync_reset : std_logic;
-
+
+ -- Gray Decoder
+ signal nx_frame_word : std_logic_vector(31 downto 0);
+ signal nx_frame_clk : std_logic;
+ signal nx_frame_clk_c100 : std_logic;
+
+ -- NX Timestamp Delay
+ constant S1_PIPE_LEN : integer := 5;
+ type delay_array_s1 is array(0 to S1_PIPE_LEN)
+ of std_logic_vector(31 downto 0);
+ signal nx_timestamp_delayed_s1 : delay_array_s1;
+ signal nx_timestamp_delayed_s1_clk : std_logic;
+
+ constant S2_PIPE_LEN : integer := 4;
+ type delay_array_s2 is array(0 to S2_PIPE_LEN)
+ of std_logic_vector(31 downto 0);
+ signal nx_timestamp_delayed_s2 : delay_array_s2;
+ signal nx_timestamp_delay : unsigned(2 downto 0);
+
+ type delay_array_b is array(0 to 3) of std_logic_vector(31 downto 0);
+ signal nx_frame_word_delayed_t : delay_array_b;
+
+ signal nx_frame_clk_delayed_t : std_logic_vector(3 downto 0);
+ signal nx_timestamp_delayed : std_logic_vector(31 downto 0);
+ signal nx_timestamp_delayed_clk : std_logic;
+
+ signal nx_frame_word_delay : unsigned(1 downto 0);
+ signal adc_data_clk_last : std_logic_vector(3 downto 0);
+ signal frame_word_delay_change : std_logic;
+ signal frame_word_delay_set : std_logic;
+
-- NX Clock Active
signal nx_clk_active_ff_0 : std_logic;
signal nx_clk_active_ff_1 : std_logic;
signal johnson_ff_1 : std_logic;
signal johnson_counter_sync : std_logic_vector(1 downto 0);
signal adc_clk_ok : std_logic;
+ signal adc_clk_ok_c100 : std_logic;
signal pll_adc_sampling_clk_o : std_logic;
signal pll_adc_sampling_clk_lock : std_logic;
signal adc_reset_sync : std_logic;
signal adc_reset_ctr : unsigned(11 downto 0);
- -- Reset Handler
- signal startup_reset : std_logic;
- signal rs_wait_timer_start : std_logic;
- signal rs_wait_timer_done : std_logic;
-
- signal rs_timeout_timer_start : std_logic;
- signal rs_timeout_timer_done : std_logic;
- signal rs_timeout_timer_reset : std_logic;
- signal nx_timestamp_reset_o : std_logic;
-
- type R_STATES is (R_IDLE,
- R_SET_ALL_RESETS,
- R_WAIT_1,
- R_WAIT_NX_FRAME_RATE_OK,
- R_PLL_WAIT_LOCK,
- R_WAIT_ADC_OK,
- R_WAIT_DATA_HANDLER_OK
- );
- signal R_STATE : R_STATES;
-
- signal frame_rates_reset : std_logic;
- signal sampling_clk_reset : std_logic;
- signal adc_reset : std_logic;
- signal adc_reset_p : std_logic;
- signal output_handler_reset : std_logic;
-
- signal reset_handler_counter : unsigned(15 downto 0);
- signal reset_handler_busy : std_logic;
- signal reset_timeout_flag : std_logic;
-
- -----------------------------------------------------------------------------
- -- CLK_IN Domain
- -----------------------------------------------------------------------------
-
- -- NX FIFO READ ENABLE
- signal nx_fifo_read_enable : std_logic;
- signal nx_fifo_empty : std_logic;
- signal nx_read_enable : std_logic;
- signal nx_fifo_data_valid_tt : std_logic;
- signal nx_fifo_data_valid_t : std_logic;
- signal nx_fifo_data_valid : std_logic;
-
- signal nx_fifo_data : std_logic_vector(31 downto 0);
-
- -- NX FIFO READ
- type delay_array_t is array(0 to 15) of std_logic_vector(31 downto 0);
- signal nx_timestamp_d : delay_array_t;
- signal nx_timestamp_t : std_logic_vector(31 downto 0);
- signal nx_new_timestamp : std_logic;
- signal nx_new_timestamp_ctr : unsigned(3 downto 0);
- signal nx_fifo_data_f : std_logic_vector(31 downto 0);
-
- -- Resync Counter Process
- signal resync_counter : unsigned(11 downto 0);
- signal resync_ctr_inc : std_logic;
- signal nx_clk_active : std_logic;
-
- -- Parity Error Counter Process
- signal parity_error : std_logic;
- signal parity_error_counter : unsigned(11 downto 0);
-
- signal reg_nx_frame_synced : std_logic;
-
-----------------------------------------------------------------------------
-- ADC Data Handler
-----------------------------------------------------------------------------
-- ADC Handler
signal ADC_RESET_AD9228 : std_logic;
signal adc_data : std_logic_vector(11 downto 0);
- signal test_adc_data : std_logic_vector(11 downto 0);
- signal adc_data_valid : std_logic;
-
- signal adc_data_t : std_logic_vector(11 downto 0);
- signal adc_new_data : std_logic;
- signal adc_new_data_ctr : unsigned(3 downto 0);
+ signal adc_data_clk : std_logic;
+ signal adc_data_clk_c100 : std_logic;
+
+ signal adc_data_s : std_logic_vector(11 downto 0);
+ signal adc_data_s_clk : std_logic;
signal adc_notlock_ctr : unsigned(7 downto 0);
signal ADC_DEBUG : std_logic_vector(15 downto 0);
signal adc_debug_type : std_logic_vector(3 downto 0);
- -- Data Output Handler
- type STATES is (WAIT_ADC,
- WAIT_TIMESTAMP
- );
- signal STATE : STATES;
- signal STATE_d : std_logic;
-
- signal nx_timestamp_o : std_logic_vector(31 downto 0);
- signal adc_data_o : std_logic_vector(11 downto 0);
- signal new_data_o : std_logic;
+ -- Merge Data Streams
+ signal data_frame : std_logic_vector(43 downto 0);
+ signal data_frame_clk : std_logic;
signal merge_timeout_ctr : unsigned(3 downto 0);
signal merge_timeout_error : std_logic;
signal merge_error_ctr : unsigned(11 downto 0);
+
+ -- Data Output Handler
+ signal nx_timestamp_o : std_logic_vector(31 downto 0);
+ signal adc_data_o : std_logic_vector(11 downto 0);
+ signal data_clk_o : std_logic;
-- Check Nxyter Data Clock via Johnson Counter
signal nx_data_clock_test_0 : std_logic;
signal new_adc_dt_error_ctr : unsigned(11 downto 0);
signal new_timestamp_dt_error_ctr : unsigned(11 downto 0);
+ -----------------------------------------------------------------------------
+ -- CLK Domain Transfer
+ -----------------------------------------------------------------------------
+
+ -- NX FIFO READ ENABLE
+ signal fifo_reset_i : std_logic;
+ signal fifo_write_enable : std_logic;
+ signal fifo_read_enable : std_logic;
+ signal fifo_empty : std_logic;
+ signal fifo_full : std_logic;
+ signal fifo_data_clk_tt : std_logic;
+ signal fifo_data_clk_t : std_logic;
+ signal fifo_data_clk : std_logic;
+
+ signal fifo_data : std_logic_vector(43 downto 0);
+
-- Slave Bus
signal slv_data_out_o : std_logic_vector(31 downto 0);
signal slv_no_more_data_o : std_logic;
signal slv_unknown_addr_o : std_logic;
signal slv_ack_o : std_logic;
-
+
signal reset_resync_ctr : std_logic;
signal reset_parity_error_ctr : std_logic;
- signal debug_adc : std_logic_vector(1 downto 0);
+ signal debug_mode : std_logic_vector(2 downto 0);
signal reset_handler_start_r : std_logic;
signal reset_handler_counter_clear : std_logic;
signal adc_bit_shift : unsigned(3 downto 0);
signal johnson_counter_sync_r : unsigned(1 downto 0);
signal pll_adc_sample_clk_dphase_r : unsigned(3 downto 0);
+ signal pll_adc_sample_clk_finedelb_r : std_logic_vector(3 downto 0);
+ signal nx_timestamp_delay_r : unsigned(2 downto 0);
+ signal nx_frame_word_delay_r : unsigned(1 downto 0);
+ signal fifo_full_r : std_logic;
+ signal fifo_empty_r : std_logic;
+
+ -----------------------------------------------------------------------------
+ -- Reset Handler
+ -----------------------------------------------------------------------------
+ signal startup_reset : std_logic;
+ signal rs_wait_timer_start : std_logic;
+ signal rs_wait_timer_done : std_logic;
+
+ signal rs_timeout_timer_start : std_logic;
+ signal rs_timeout_timer_done : std_logic;
+ signal rs_timeout_timer_reset : std_logic;
+ signal nx_timestamp_reset_o : std_logic;
+ signal fifo_reset : std_logic;
+
+ type R_STATES is (R_IDLE,
+ R_SET_ALL_RESETS,
+ R_WAIT_1,
+ R_WAIT_NX_FRAME_RATE_OK,
+ R_PLL_WAIT_LOCK,
+ R_WAIT_ADC_OK,
+ R_WAIT_DATA_HANDLER_OK
+ );
+ signal R_STATE : R_STATES;
+
+ signal frame_rates_reset : std_logic;
+ signal sampling_clk_reset : std_logic;
+ signal adc_reset : std_logic;
+ signal adc_reset_p : std_logic;
+ signal output_handler_reset : std_logic;
+ signal reset_handler_counter : unsigned(15 downto 0);
+ signal reset_handler_busy : std_logic;
+ signal reset_timeout_flag : std_logic;
+
+ -- Resync Counter Process
+ signal resync_counter : unsigned(11 downto 0);
+ signal resync_ctr_inc : std_logic;
+ signal nx_clk_active : std_logic;
+
+ -- Parity Error Counter Process
+ signal parity_error : std_logic;
+ signal parity_error_c100 : std_logic;
+ signal parity_error_counter : unsigned(11 downto 0);
+
+ signal reg_nx_frame_synced : std_logic;
+
-- Reset Domain Transfers
signal RESET_NX_TIMESTAMP_CLK_IN : std_logic;
- signal RESET_NX_DATA_CLK_TEST_IN : std_logic;
signal debug_state : std_logic_vector(3 downto 0);
begin
- PROC_DEBUG_MULT: process(debug_adc,
+ PROC_DEBUG_MULT: process(debug_mode,
adc_data,
- adc_data_valid,
- test_adc_data,
+ adc_data_clk,
adc_clk_ok,
adc_clk_ok_last,
adc_clk_skip,
adc_reset_sync,
adc_reset_sync_s,
ADC_RESET_AD9228,
- nx_new_frame,
+ nx_frame_clk,
adc_reset_ctr,
- nx_fifo_full,
- nx_fifo_write_enable,
- nx_fifo_empty,
- nx_fifo_read_enable,
- nx_fifo_data_valid,
- nx_new_timestamp,
- adc_new_data,
- STATE_d,
- new_data_o,
+ fifo_write_enable,
+ fifo_empty,
+ fifo_read_enable,
+ nx_timestamp_delayed_clk,
+ adc_data_s_clk,
+ data_clk_o,
nx_frame_synced,
rs_sync_reset
)
begin
- case debug_adc is
- when "00" =>
+ case debug_mode is
+ when "000" =>
-- Default
DEBUG_OUT(0) <= CLK_IN;
DEBUG_OUT(1) <= TRIGGER_IN;
- DEBUG_OUT(2) <= nx_fifo_full;
- DEBUG_OUT(3) <= nx_fifo_write_enable;
- DEBUG_OUT(4) <= nx_fifo_empty;
- DEBUG_OUT(5) <= merge_timeout_error; --STATE_d;
- DEBUG_OUT(6) <= nx_fifo_read_enable;
- DEBUG_OUT(7) <= nx_fifo_data_valid;
- DEBUG_OUT(8) <= adc_data_valid;
- DEBUG_OUT(9) <= nx_new_timestamp;
- DEBUG_OUT(10) <= adc_new_data;
- DEBUG_OUT(11) <= nx_fifo_reset;
- DEBUG_OUT(12) <= parity_error;
- DEBUG_OUT(13) <= nx_new_frame;
- DEBUG_OUT(14) <= new_data_o;
+ DEBUG_OUT(2) <= data_frame_clk;
+ DEBUG_OUT(3) <= fifo_reset;
+ DEBUG_OUT(4) <= fifo_full;
+ DEBUG_OUT(5) <= fifo_write_enable;
+ DEBUG_OUT(6) <= fifo_empty;
+ DEBUG_OUT(7) <= fifo_read_enable;
+ DEBUG_OUT(8) <= fifo_data_clk;
+ DEBUG_OUT(9) <= nx_frame_clk;
+ DEBUG_OUT(10) <= nx_timestamp_delayed_clk;
+ DEBUG_OUT(11) <= adc_data_s_clk;
+ DEBUG_OUT(12) <= data_clk_o;
+ DEBUG_OUT(13) <= parity_error_c100;
+ DEBUG_OUT(14) <= merge_timeout_error;
DEBUG_OUT(15) <= nx_frame_synced;
- when "01" =>
+ when "001" =>
-- Reset Handler
DEBUG_OUT(0) <= CLK_IN;
- DEBUG_OUT(1) <= nx_new_frame;
+ DEBUG_OUT(1) <= nx_frame_clk;
DEBUG_OUT(2) <= adc_clk_skip;
DEBUG_OUT(3) <= adc_clk_ok;
DEBUG_OUT(4) <= adc_reset_sync;
DEBUG_OUT(6) <= ADC_RESET_AD9228;
DEBUG_OUT(7) <= pll_adc_not_lock;
DEBUG_OUT(8) <= reset_for_offline;
- DEBUG_OUT(9) <= nx_fifo_reset;
+ DEBUG_OUT(9) <= fifo_reset;
DEBUG_OUT(10) <= reset_handler_busy;
DEBUG_OUT(11) <= sampling_clk_reset;
DEBUG_OUT(15 downto 12) <= debug_state;
- when "10" =>
+ when "010" =>
-- AD9228 Handler Debug output
DEBUG_OUT <= ADC_DEBUG;
- when "11" =>
+ when "011" =>
-- Test Channel
DEBUG_OUT(0) <= CLK_IN;
DEBUG_OUT(3 downto 1) <= debug_state(2 downto 0);
DEBUG_OUT(7) <= pll_adc_not_lock;
DEBUG_OUT(8) <= error_adc0;
DEBUG_OUT(9) <= adc_frame_rate_error;
- DEBUG_OUT(10) <= nx_fifo_reset;
+ DEBUG_OUT(10) <= fifo_reset;
DEBUG_OUT(11) <= sampling_clk_reset;
DEBUG_OUT(12) <= adc_reset;
DEBUG_OUT(13) <= output_handler_reset;
DEBUG_OUT(14) <= frame_rate_error;
DEBUG_OUT(15) <= reset_timeout_flag;
+
+ when "100" =>
+ -- AD9228 Handler Debug output
+ DEBUG_OUT(0) <= CLK_IN;
+ DEBUG_OUT(1) <= '0';
+ DEBUG_OUT(2) <= nx_frame_clk;
+ DEBUG_OUT(3) <= '0';
+ DEBUG_OUT(4) <= nx_timestamp_delayed_clk;
+ DEBUG_OUT(5) <= '0';
+ DEBUG_OUT(6) <= adc_data_clk;
+ DEBUG_OUT(7) <= '0';
+ DEBUG_OUT(8) <= fifo_write_enable;
+ DEBUG_OUT(9) <= '0';
+ DEBUG_OUT(10) <= data_frame_clk;
+ DEBUG_OUT(15 downto 11) <= (others => '0');
+
+ when "101" =>
+ -- AD9228 Handler Debug output
+ DEBUG_OUT(0) <= NX_TIMESTAMP_CLK_IN;
+ DEBUG_OUT(1) <= '0';
+ DEBUG_OUT(2) <= nx_frame_clk;
+ DEBUG_OUT(3) <= '0';
+ DEBUG_OUT(4) <= nx_timestamp_delayed_clk;
+ DEBUG_OUT(5) <= merge_timeout_error;
+ DEBUG_OUT(6) <= adc_data_s_clk;
+ DEBUG_OUT(7) <= data_frame_clk;
+ DEBUG_OUT(9 downto 8) <= nx_frame_word_delay;
+ DEBUG_OUT(10) <= frame_word_delay_change;
+ DEBUG_OUT(11) <= frame_word_delay_set;
+ DEBUG_OUT(15 downto 12) <= adc_data_clk_last;
+
+ when others =>
+ DEBUG_OUT <= (others => '0');
end case;
end process PROC_DEBUG_MULT;
SIGNAL_OUT => RESET_NX_TIMESTAMP_CLK_IN
);
- signal_async_trans_RESET_IN_2: signal_async_trans
- port map (
- CLK_IN => NX_DATA_CLK_TEST_IN,
- SIGNAL_A_IN => RESET_IN,
- SIGNAL_OUT => RESET_NX_DATA_CLK_TEST_IN
- );
-
-----------------------------------------------------------------------------
- -- Check NX Data Clk
+ -- PLL Handler
-----------------------------------------------------------------------------
- PROC_COUNTER_NX_CLOCK: process(NX_TIMESTAMP_CLK_IN)
- begin
- if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
- if( RESET_NX_TIMESTAMP_CLK_IN = '1' ) then
- counter_nx_domain <= (others => '0');
- else
- counter_nx_domain <= counter_nx_domain + 1;
- end if;
- end if;
- end process PROC_COUNTER_NX_CLOCK;
- PROC_COUNTER_NX_REF_CLOCK: process(NX_DATA_CLK_TEST_IN)
- begin
- if (rising_edge(NX_DATA_CLK_TEST_IN) ) then
- if (NX_DATA_CLK_TEST_IN = '1') then
- counter_nx_ref_domain <= (others => '0');
- else
- counter_nx_ref_domain <= counter_nx_ref_domain + 1;
- end if;
- end if;
- end process PROC_COUNTER_NX_REF_CLOCK;
+ pll_adc_sampling_clk_reset <= sampling_clk_reset when rising_edge(CLK_IN);
- counter_nx_diff <= counter_nx_ref_domain - counter_nx_domain;
-
- -----------------------------------------------------------------------------
- -- ADC CLK DOMAIN
- -----------------------------------------------------------------------------
+ pll_adc_sample_clk_finedelb <=
+ pll_adc_sample_clk_finedelb_r when rising_edge(CLK_IN);
- pll_adc_sampling_clk_reset <= sampling_clk_reset;
+ -- Shift dphase to show 0 as optimal value in standard setup
+ pll_adc_sample_clk_dphase <=
+ std_logic_vector(pll_adc_sample_clk_dphase_r - 2) when rising_edge(CLK_IN);
- -- Shift dphase show 0 as optimal value
- pll_adc_sample_clk_dphase <=
- std_logic_vector(pll_adc_sample_clk_dphase_r - 1);
-
pll_adc_sampling_clk_2: pll_adc_sampling_clk
port map (
CLK => adc_sampling_clk,
end if;
end process PROC_PLL_LOCK_COUNTER;
- ADC_RESET_AD9228 <= RESET_IN or adc_reset;
- adc_ad9228_1: adc_ad9228
+ pulse_dtrans_adc_data_clk: pulse_dtrans
+ generic map (
+ CLK_RATIO => 2
+ )
port map (
- CLK_IN => CLK_IN,
- RESET_IN => ADC_RESET_AD9228,
- CLK_ADCDAT_IN => ADC_CLK_DAT_IN,
-
- ADC0_SCLK_IN => pll_adc_sampling_clk_o,
- ADC0_SCLK_OUT => ADC_SAMPLE_CLK_OUT,
- ADC0_DATA_A_IN => ADC_NX_IN(0),
- ADC0_DATA_B_IN => ADC_B_IN(0),
- ADC0_DATA_C_IN => ADC_A_IN(0),
- ADC0_DATA_D_IN => ADC_D_IN(0),
- ADC0_DCLK_IN => ADC_DCLK_IN(0),
- ADC0_FCLK_IN => ADC_FCLK_IN(0),
-
- ADC1_SCLK_IN => pll_adc_sampling_clk_o,
- ADC1_SCLK_OUT => open,
- ADC1_DATA_A_IN => ADC_NX_IN(1),
- ADC1_DATA_B_IN => ADC_A_IN(1),
- ADC1_DATA_C_IN => ADC_B_IN(1),
- ADC1_DATA_D_IN => ADC_D_IN(1),
- ADC1_DCLK_IN => ADC_DCLK_IN(1),
- ADC1_FCLK_IN => ADC_FCLK_IN(1),
-
- ADC0_DATA_A_OUT => adc_data,
- ADC0_DATA_B_OUT => test_adc_data,
- ADC0_DATA_C_OUT => open,
- ADC0_DATA_D_OUT => open,
- ADC0_DATA_VALID_OUT => adc_data_valid,
-
- ADC1_DATA_A_OUT => open,
- ADC1_DATA_B_OUT => open,
- ADC1_DATA_C_OUT => open,
- ADC1_DATA_D_OUT => open,
- ADC1_DATA_VALID_OUT => open,
-
- ADC0_NOTLOCK_COUNTER => adc_notlock_ctr,
- ADC1_NOTLOCK_COUNTER => open,
+ CLK_A_IN => NX_TIMESTAMP_CLK_IN,
+ RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN,
+ PULSE_A_IN => adc_data_clk,
+ CLK_B_IN => CLK_IN,
+ RESET_B_IN => RESET_IN,
+ PULSE_B_OUT => adc_data_clk_c100
+ );
- ERROR_ADC0_OUT => error_adc0,
- ERROR_ADC1_OUT => error_adc1,
- DEBUG_IN => adc_debug_type,
- DEBUG_OUT => ADC_DEBUG
+ pulse_dtrans_nx_frame_clk: pulse_dtrans
+ generic map (
+ CLK_RATIO => 2
+ )
+ port map (
+ CLK_A_IN => NX_TIMESTAMP_CLK_IN,
+ RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN,
+ PULSE_A_IN => nx_frame_clk,
+ CLK_B_IN => CLK_IN,
+ RESET_B_IN => RESET_IN,
+ PULSE_B_OUT => nx_frame_clk_c100
);
+ pulse_dtrans_parity_error: pulse_dtrans
+ generic map (
+ CLK_RATIO => 2
+ )
+ port map (
+ CLK_A_IN => NX_TIMESTAMP_CLK_IN,
+ RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN,
+ PULSE_A_IN => parity_error,
+ CLK_B_IN => CLK_IN,
+ RESET_B_IN => RESET_IN,
+ PULSE_B_OUT => parity_error_c100
+ );
+
timer_static_RESET_TIMER: timer_static
generic map (
CTR_WIDTH => 20,
RESET_B_IN => RESET_IN,
PULSE_B_OUT => adc_reset_sync
);
+
+ signal_async_trans_ADC_CLK_OK: signal_async_trans
+ port map (
+ CLK_IN => CLK_IN,
+ SIGNAL_A_IN => adc_clk_ok,
+ SIGNAL_OUT => adc_clk_ok_c100
+ );
- PROC_RESET_HANDLER: process(CLK_IN)
+ PROC_NX_CLK_ACT: process(NX_TIMESTAMP_CLK_IN)
begin
- if (rising_edge(CLK_IN) ) then
- if( RESET_IN = '1' ) then
- frame_rates_reset <= '0';
- nx_fifo_reset <= '0';
- sampling_clk_reset <= '0';
- adc_reset_p <= '0';
- adc_reset <= '0';
- output_handler_reset <= '0';
+ if (rising_edge(NX_TIMESTAMP_CLK_IN)) then
+ if(RESET_NX_TIMESTAMP_CLK_IN = '1' ) then
+ nx_clk_active_ff_0 <= '0';
+ nx_clk_active_ff_1 <= '0';
+ nx_clk_active_ff_2 <= '0';
+ else
+ nx_clk_active_ff_0 <= not nx_clk_active_ff_2;
+ nx_clk_active_ff_1 <= nx_clk_active_ff_0;
+ nx_clk_active_ff_2 <= nx_clk_active_ff_1;
+ end if;
+ end if;
+ end process PROC_NX_CLK_ACT;
- rs_wait_timer_start <= '0';
- rs_timeout_timer_start <= '0';
- rs_timeout_timer_reset <= '1';
- reset_handler_counter <= (others => '0');
- reset_handler_busy <= '0';
- reset_timeout_flag <= '0';
- startup_reset <= '1';
- nx_timestamp_reset_o <= '0';
- R_STATE <= R_IDLE;
+ -- ADC Sampling Clock Generator using a Johnson Counter
+ PROC_ADC_SAMPLING_CLK_GENERATOR: process(NX_TIMESTAMP_CLK_IN)
+ begin
+ if (rising_edge(NX_TIMESTAMP_CLK_IN)) then
+ if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
+ johnson_ff_0 <= '0';
+ johnson_ff_1 <= '0';
else
- frame_rates_reset <= '0';
- nx_fifo_reset <= '0';
- sampling_clk_reset <= '0';
- adc_reset_p <= '0';
- adc_reset <= '0';
- output_handler_reset <= '0';
+ if (adc_clk_skip = '0') then
+ johnson_ff_0 <= not johnson_ff_1;
+ johnson_ff_1 <= johnson_ff_0;
+ adc_sampling_clk <= not johnson_ff_1;
+ end if;
+ end if;
+ end if;
+ adc_sampling_clk <= johnson_ff_0;
+ end process PROC_ADC_SAMPLING_CLK_GENERATOR;
- rs_wait_timer_start <= '0';
- rs_timeout_timer_start <= '0';
- rs_timeout_timer_reset <= '0';
- reset_handler_busy <= '1';
- nx_timestamp_reset_o <= '0';
-
- debug_state <= x"0";
-
- if (reset_handler_counter_clear = '1') then
- reset_handler_counter <= (others => '0');
+ -- Adjust johnson_counter_sync to show optimal value at 0
+ johnson_counter_sync <= std_logic_vector(johnson_counter_sync_r + 3);
+ PROC_ADC_SAMPLING_CLK_SYNC: process(NX_TIMESTAMP_CLK_IN)
+ variable adc_clk_state : std_logic_vector(1 downto 0);
+ begin
+ if (rising_edge(NX_TIMESTAMP_CLK_IN)) then
+ if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
+ adc_clk_skip <= '0';
+ adc_clk_ok <= '0';
+ else
+ adc_clk_state := johnson_ff_1 & johnson_ff_0;
+ adc_clk_skip <= '0';
+ if (nx_frame_clk_coded = '1') then
+ if (adc_clk_state /= johnson_counter_sync) then
+ adc_clk_skip <= '1';
+ adc_clk_ok <= '0';
+ else
+ adc_clk_ok <= '1';
+ end if;
end if;
-
- if (rs_timeout_timer_done = '1') then
- -- Reset Timeout
- reset_timeout_flag <= '1';
- R_STATE <= R_IDLE;
- else
-
- case R_STATE is
- when R_IDLE =>
- if (reset_for_offline = '1' or
- pll_adc_not_lock = '1' or
- adc_reset_sync = '1' or
- reset_handler_start_r = '1' or
- startup_reset = '1'
- ) then
- if (reset_handler_counter_clear = '0') then
- reset_handler_counter <= reset_handler_counter + 1;
- end if;
- R_STATE <= R_SET_ALL_RESETS;
- else
- reset_handler_busy <= '0';
- R_STATE <= R_IDLE;
- end if;
-
- when R_SET_ALL_RESETS =>
- frame_rates_reset <= '1';
- nx_fifo_reset <= '1';
- sampling_clk_reset <= '1';
- adc_reset_p <= '1';
- adc_reset <= '1';
- output_handler_reset <= '1';
-
- nx_timestamp_reset_o <= '1';
-
- rs_wait_timer_start <= '1'; -- wait 1mue to settle
- R_STATE <= R_WAIT_1;
- debug_state <= x"1";
-
- when R_WAIT_1 =>
- if (rs_wait_timer_done = '0') then
- nx_fifo_reset <= '1';
- sampling_clk_reset <= '1';
- adc_reset <= '1';
- output_handler_reset <= '1';
- R_STATE <= R_WAIT_1;
- else
- -- Release NX Fifo Reset + Start Timeout Handler
- sampling_clk_reset <= '1';
- adc_reset <= '1';
- output_handler_reset <= '1';
- rs_timeout_timer_start <= '1';
- R_STATE <= R_WAIT_NX_FRAME_RATE_OK;
- end if;
- debug_state <= x"2";
-
- when R_WAIT_NX_FRAME_RATE_OK =>
- if (nx_frame_rate_offline = '0' and
- nx_frame_rate_error = '0') then
- -- Release PLL Reset
- adc_reset <= '1';
- output_handler_reset <= '1';
- R_STATE <= R_PLL_WAIT_LOCK;
- else
- sampling_clk_reset <= '1';
- adc_reset <= '1';
- output_handler_reset <= '1';
- R_STATE <= R_WAIT_NX_FRAME_RATE_OK;
- end if;
- debug_state <= x"3";
-
- when R_PLL_WAIT_LOCK =>
- if (pll_adc_not_lock = '1') then
- adc_reset <= '1';
- output_handler_reset <= '1';
- R_STATE <= R_PLL_WAIT_LOCK;
- else
- -- Release ADC Reset
- output_handler_reset <= '1';
- R_STATE <= R_WAIT_ADC_OK;
- end if;
- debug_state <= x"4";
-
- when R_WAIT_ADC_OK =>
- if (error_adc0 = '0' and
- adc_frame_rate_error = '0') then
- -- Release Output Handler Reset
- R_STATE <= R_WAIT_DATA_HANDLER_OK;
- else
- output_handler_reset <= '1';
- R_STATE <= R_WAIT_ADC_OK;
- end if;
- debug_state <= x"5";
-
- when R_WAIT_DATA_HANDLER_OK =>
- if (frame_rate_error = '0') then
- startup_reset <= '0';
- reset_timeout_flag <= '0';
- rs_timeout_timer_reset <= '1';
- R_STATE <= R_IDLE;
- else
- R_STATE <= R_WAIT_DATA_HANDLER_OK;
- end if;
- debug_state <= x"6";
-
- end case;
+ end if;
+ end if;
+ end process PROC_ADC_SAMPLING_CLK_SYNC;
+
+ PROC_ADC_RESET: process(NX_TIMESTAMP_CLK_IN)
+ begin
+ if (rising_edge(NX_TIMESTAMP_CLK_IN)) then
+ if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
+ adc_clk_ok_last <= '0';
+ adc_reset_sync_s <= '0';
+ else
+ adc_reset_sync_s <= '0';
+ adc_clk_ok_last <= adc_clk_ok;
+ if (adc_clk_ok_last = '0' and adc_clk_ok = '1') then
+ adc_reset_sync_s <= '1';
end if;
end if;
end if;
- end process PROC_RESET_HANDLER;
+ end process PROC_ADC_RESET;
+
+ PROC_RESET_CTR: process(CLK_IN)
+ begin
+ if (rising_edge(CLK_IN)) then
+ if (RESET_IN = '1') then
+ adc_reset_ctr <= (others => '0');
+ else
+ if (adc_reset_p = '1') then
+ adc_reset_ctr <= adc_reset_ctr + 1;
+ end if;
+ end if;
+ end if;
+ end process PROC_RESET_CTR;
-----------------------------------------------------------------------------
- -- NX_TIMESTAMP_CLK_IN Domain
+ -- NX Timestamp Handler
-----------------------------------------------------------------------------
-
+
-- Merge TS Data 8bit to 32Bit Timestamp Frame
PROC_8_TO_32_BIT: process(NX_TIMESTAMP_CLK_IN)
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
if( RESET_NX_TIMESTAMP_CLK_IN = '1' ) then
- frame_byte_ctr <= (others => '0');
- nx_frame_word <= (others => '0');
- nx_timestamp_ff <= (others => '0');
- nx_new_frame <= '0';
+ nx_frame_word_f <= (others => '0');
+ nx_frame_clk_t <= '0';
+ nx_frame_word_coded <= (others => '0');
+ nx_frame_clk_coded <= '0';
else
- nx_timestamp_fff <= NX_TIMESTAMP_IN;
- nx_timestamp_ff <= nx_timestamp_fff;
- nx_new_frame <= '0';
+ nx_frame_word_ff <= NX_TIMESTAMP_IN;
+ nx_frame_word_f <= nx_frame_word_ff;
case frame_byte_pos is
- when "11" => nx_frame_word(31 downto 24) <= nx_timestamp_ff;
- frame_byte_ctr <= frame_byte_ctr + 1;
-
- when "10" => nx_frame_word(23 downto 16) <= nx_timestamp_ff;
- frame_byte_ctr <= frame_byte_ctr + 1;
-
- when "01" => nx_frame_word(15 downto 8) <= nx_timestamp_ff;
- frame_byte_ctr <= frame_byte_ctr + 1;
-
- when "00" => nx_frame_word( 7 downto 0) <= nx_timestamp_ff;
- if (frame_byte_ctr = "11") then
- nx_new_frame <= '1';
- end if;
- frame_byte_ctr <= (others => '0');
+ when "11" => nx_frame_word_t(31 downto 24) <= nx_frame_word_f;
+ nx_frame_clk_t <= '0';
+
+ when "10" => nx_frame_word_t(23 downto 16) <= nx_frame_word_f;
+ nx_frame_clk_t <= '0';
+
+ when "01" => nx_frame_word_t(15 downto 8) <= nx_frame_word_f;
+ nx_frame_clk_t <= '0';
+
+ when "00" => nx_frame_word_t( 7 downto 0) <= nx_frame_word_f;
+ nx_frame_clk_t <= '1';
end case;
+
+ -- Output Frame
+ if (nx_frame_clk_t = '1') then
+ nx_frame_word_coded <= nx_frame_word_t;
+ nx_frame_clk_coded <= '1';
+ else
+ nx_frame_word_coded <= x"0000_0001";
+ nx_frame_clk_coded <= '0';
+ end if;
end if;
end if;
end process PROC_8_TO_32_BIT;
- -- Frame Sync process
+ -- TS Frame Sync process
PROC_SYNC_TO_NX_FRAME: process(NX_TIMESTAMP_CLK_IN)
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
else
rs_sync_set <= '0';
rs_sync_reset <= '0';
- if (nx_new_frame = '1') then
- case nx_frame_word is
+ if (nx_frame_clk_t = '1') then
+ case nx_frame_word_t is
when x"7f7f7f06" =>
rs_sync_set <= '1';
frame_byte_pos <= frame_byte_pos - 1;
PROC_RS_FRAME_SYNCED: process(NX_TIMESTAMP_CLK_IN)
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
- if (RESET_NX_TIMESTAMP_CLK_IN = '1' or rs_sync_reset = '1') then
- nx_frame_synced <= '0';
- elsif (rs_sync_set = '1') then
- nx_frame_synced <= '1';
+ if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
+ nx_frame_synced <= '0';
+ else
+ if (rs_sync_reset = '1') then
+ nx_frame_synced <= '0';
+ elsif (rs_sync_set = '1') then
+ nx_frame_synced <= '1';
+ end if;
end if;
end if;
end process PROC_RS_FRAME_SYNCED;
+
+ -----------------------------------------------------------------------------
+ -- Gray Decode Timestamp Frame (Timestamp and Channel Id)
+ -----------------------------------------------------------------------------
+
+ gray_decoder_TIMESTAMP: gray_decoder -- Decode nx_timestamp
+ generic map (
+ WIDTH => 14
+ )
+ port map (
+ CLK_IN => NX_TIMESTAMP_CLK_IN,
+ RESET_IN => RESET_NX_TIMESTAMP_CLK_IN,
+ GRAY_IN(13 downto 7) => not nx_frame_word_coded(30 downto 24),
+ GRAY_IN( 6 downto 0) => not nx_frame_word_coded(22 downto 16),
+ BINARY_OUT(13 downto 7) => nx_frame_word(30 downto 24),
+ BINARY_OUT(6 downto 0) => nx_frame_word(22 downto 16)
+ );
- fifo_ts_32to32_dc_1: fifo_ts_32to32_dc
+ gray_decoder_CHANNEL_ID: gray_decoder -- Decode Channel_ID
+ generic map (
+ WIDTH => 7
+ )
port map (
- Data => nx_frame_word,
- WrClock => NX_TIMESTAMP_CLK_IN,
- RdClock => CLK_IN,
- WrEn => nx_fifo_write_enable,
- RdEn => nx_fifo_read_enable,
- Reset => nx_fifo_reset,
- RPReset => nx_fifo_reset,
- Q => nx_fifo_data_f,
- Empty => nx_fifo_empty,
- Full => nx_fifo_full
+ CLK_IN => NX_TIMESTAMP_CLK_IN,
+ RESET_IN => RESET_NX_TIMESTAMP_CLK_IN,
+ GRAY_IN => nx_frame_word_coded(14 downto 8),
+ BINARY_OUT => nx_frame_word(14 downto 8)
);
- nx_fifo_write_enable <= nx_new_frame and not nx_fifo_full;
-
- PROC_NX_CLK_ACT: process(NX_TIMESTAMP_CLK_IN)
+ -- Leave other bits and frame clk untouched, i.e. delay by one clk
+ PROC_GRAY_DECODE: process(NX_TIMESTAMP_CLK_IN)
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN)) then
- if(RESET_NX_TIMESTAMP_CLK_IN = '1' ) then
- nx_clk_active_ff_0 <= '0';
- nx_clk_active_ff_1 <= '0';
- nx_clk_active_ff_2 <= '0';
- else
- nx_clk_active_ff_0 <= not nx_clk_active_ff_2;
- nx_clk_active_ff_1 <= nx_clk_active_ff_0;
- nx_clk_active_ff_2 <= nx_clk_active_ff_1;
- end if;
+ nx_frame_word(31) <= nx_frame_word_coded(31);
+ nx_frame_word(23) <= nx_frame_word_coded(23);
+ nx_frame_word(15) <= nx_frame_word_coded(15);
+ nx_frame_word(7 downto 1) <= nx_frame_word_coded(7 downto 1);
+ nx_frame_clk <= nx_frame_clk_coded;
end if;
- end process PROC_NX_CLK_ACT;
-
- -- ADC Sampling Clock Generator using a Johnson Counter
- PROC_ADC_SAMPLING_CLK_GENERATOR: process(NX_TIMESTAMP_CLK_IN)
- begin
- if (rising_edge(NX_TIMESTAMP_CLK_IN)) then
- if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
- johnson_ff_0 <= '0';
- johnson_ff_1 <= '0';
- else
- if (adc_clk_skip = '0') then
- johnson_ff_0 <= not johnson_ff_1;
- johnson_ff_1 <= johnson_ff_0;
- adc_sampling_clk <= not johnson_ff_1;
- end if;
- end if;
- end if;
- adc_sampling_clk <= johnson_ff_0;
- end process PROC_ADC_SAMPLING_CLK_GENERATOR;
+ end process PROC_GRAY_DECODE;
- -- Adjust johnson_counter_sync to show optimal value at 0
- johnson_counter_sync <= std_logic_vector(johnson_counter_sync_r + 3);
- PROC_ADC_SAMPLING_CLK_SYNC: process(NX_TIMESTAMP_CLK_IN)
- variable adc_clk_state : std_logic_vector(1 downto 0);
+ -- Replace Parity Bit by Parity Error Bit
+ PROC_PARITY_CHECKER: process(NX_TIMESTAMP_CLK_IN)
+ variable parity_bits : std_logic_vector(22 downto 0);
+ variable parity : std_logic;
begin
if (rising_edge(NX_TIMESTAMP_CLK_IN)) then
if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
- adc_clk_skip <= '0';
- adc_clk_ok <= '0';
+ parity_error <= '0';
+ nx_frame_word(0) <= '0';
else
- adc_clk_state := johnson_ff_1 & johnson_ff_0;
- adc_clk_skip <= '0';
- if (nx_new_frame = '1') then
- if (adc_clk_state /= johnson_counter_sync) then
- adc_clk_skip <= '1';
- adc_clk_ok <= '0';
+ parity_error <= '0';
+ nx_frame_word(0) <= '1';
+
+ if (nx_frame_clk_coded = '1') then
+ -- Timestamp Bit #6 is excluded (funny nxyter-bug)
+ parity_bits := nx_frame_word_coded(31) &
+ nx_frame_word_coded(30 downto 24) &
+ nx_frame_word_coded(21 downto 16) &
+ nx_frame_word_coded(14 downto 8) &
+ nx_frame_word_coded( 2 downto 1);
+ parity := xor_all(parity_bits);
+
+ if (parity /= nx_frame_word_coded(0)) then
+ parity_error <= '1';
+ nx_frame_word(0) <= '1';
else
- adc_clk_ok <= '1';
+ parity_error <= '0';
+ nx_frame_word(0) <= '0';
end if;
end if;
end if;
end if;
- end process PROC_ADC_SAMPLING_CLK_SYNC;
+ end process PROC_PARITY_CHECKER;
- PROC_ADC_RESET: process(NX_TIMESTAMP_CLK_IN)
+ -----------------------------------------------------------------------------
+ -- Delay NX Timestamp relative to ADC Frames
+ -----------------------------------------------------------------------------
+ PROC_NX_TIMESTAMP_FRAME_DELAY: process(NX_TIMESTAMP_CLK_IN)
begin
- if (rising_edge(NX_TIMESTAMP_CLK_IN)) then
- if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
- adc_clk_ok_last <= '0';
- adc_reset_sync_s <= '0';
+ if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
+ nx_frame_word_delayed_t(0) <= nx_frame_word;
+ nx_frame_clk_delayed_t(0) <= nx_frame_clk;
+
+ -- Delay Pipeline NX Clock
+ for X in 1 to 3 loop
+ nx_frame_word_delayed_t(X) <= nx_frame_word_delayed_t(X - 1);
+ nx_frame_clk_delayed_t(X) <= nx_frame_clk_delayed_t(X - 1);
+ end loop;
+ end if;
+ end process PROC_NX_TIMESTAMP_FRAME_DELAY;
+
+ PROC_NX_TIMESTAMP_DELAY: process(NX_TIMESTAMP_CLK_IN)
+ begin
+ if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
+ nx_timestamp_delay <= nx_timestamp_delay_r;
+
+ if (nx_frame_clk_delayed_t(to_integer(nx_frame_word_delay)) = '1') then
+
+ nx_timestamp_delayed_s1(0) <= nx_frame_word_delayed_t(3);
+ -- First Stage Delay S1_PIPE_LEN steps
+ for I in 1 to S1_PIPE_LEN loop
+ nx_timestamp_delayed_s1(I) <= nx_timestamp_delayed_s1(I - 1);
+ end loop;
+
+ -- Second Stage Delay 0...S2_PIPE_LEN steps
+ nx_timestamp_delayed_s2(0) <= nx_timestamp_delayed_s1(S1_PIPE_LEN);
+ for X in 1 to S2_PIPE_LEN loop
+ nx_timestamp_delayed_s2(X) <= nx_timestamp_delayed_s2(X - 1);
+ end loop;
+
+ nx_timestamp_delayed <=
+ nx_timestamp_delayed_s2(to_integer(nx_timestamp_delay));
+ nx_timestamp_delayed_clk <= '1';
else
- adc_reset_sync_s <= '0';
- adc_clk_ok_last <= adc_clk_ok;
- if (adc_clk_ok_last = '0' and adc_clk_ok = '1') then
- adc_reset_sync_s <= '1';
- end if;
+ nx_timestamp_delayed <= x"deadaffe";
+ nx_timestamp_delayed_clk <= '0';
end if;
end if;
- end process PROC_ADC_RESET;
-
- PROC_RESET_CTR: process(CLK_IN)
+ end process PROC_NX_TIMESTAMP_DELAY;
+
+ PROC_NX_FRAME_WORD_DELAY_AUTO_SETUP: process(NX_TIMESTAMP_CLK_IN)
begin
- if (rising_edge(CLK_IN)) then
- if (RESET_IN = '1') then
- adc_reset_ctr <= (others => '0');
+ if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
+ adc_data_clk_last(0) <= adc_data_s_clk;
+ -- Register Info
+ nx_frame_word_delay_r <= nx_frame_word_delay;
+
+ if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
+ nx_frame_word_delay <= "10";
+ adc_data_clk_last(3 downto 1) <= (others => '0');
+ frame_word_delay_change <= '0';
+ frame_word_delay_set <= '0';
else
- if (adc_reset_p = '1') then
- adc_reset_ctr <= adc_reset_ctr + 1;
+ for I in 1 to 3 loop
+ adc_data_clk_last(I) <= adc_data_clk_last(I - 1);
+ end loop;
+ frame_word_delay_change <= '0';
+ frame_word_delay_set <= '0';
+ if (nx_timestamp_delayed_clk = '1') then
+ case adc_data_clk_last is
+ when "0100" =>
+ nx_frame_word_delay <= nx_frame_word_delay + 1;
+ frame_word_delay_change <= '1';
+
+ when "0010" =>
+ nx_frame_word_delay <= nx_frame_word_delay + 2;
+ frame_word_delay_change <= '1';
+
+ when "0001" =>
+ nx_frame_word_delay <= nx_frame_word_delay + 3;
+ frame_word_delay_change <= '1';
+
+ when others =>
+ null;
+
+ end case;
+
+ if (adc_data_s_clk = '1') then
+ frame_word_delay_set <= '1';
+ end if;
end if;
end if;
end if;
- end process PROC_RESET_CTR;
+ end process PROC_NX_FRAME_WORD_DELAY_AUTO_SETUP;
-----------------------------------------------------------------------------
- -- NX CLK_IN Domain
+ -- ADC Input Handler
-----------------------------------------------------------------------------
- -----------------------------------------------------------------------------
- -- Gray Decode Timestamp Frame (Timestamp and Channel Id)
- -----------------------------------------------------------------------------
-
- gray_decoder_TIMESTAMP: gray_decoder -- Decode nx_timestamp
- generic map (
- WIDTH => 14
- )
+ ADC_RESET_AD9228 <= RESET_NX_TIMESTAMP_CLK_IN or reset_handler_start_r; --adc_reset;
+ adc_ad9228_1: adc_ad9228
port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- GRAY_IN(13 downto 7) => not nx_fifo_data_f(30 downto 24),
- GRAY_IN( 6 downto 0) => not nx_fifo_data_f(22 downto 16),
- BINARY_OUT(13 downto 7) => nx_fifo_data(30 downto 24),
- BINARY_OUT(6 downto 0) => nx_fifo_data(22 downto 16)
- );
+ CLK_IN => NX_TIMESTAMP_CLK_IN,
+ RESET_IN => ADC_RESET_AD9228,
+ CLK_ADCDAT_IN => ADC_CLK_DAT_IN,
- gray_decoder_CHANNEL_ID: gray_decoder -- Decode Channel_ID
- generic map (
- WIDTH => 7
- )
- port map (
- CLK_IN => CLK_IN,
- RESET_IN => RESET_IN,
- GRAY_IN => nx_fifo_data_f(14 downto 8),
- BINARY_OUT => nx_fifo_data(14 downto 8)
+ ADC0_SCLK_IN => pll_adc_sampling_clk_o,
+ ADC0_SCLK_OUT => ADC_SAMPLE_CLK_OUT,
+ ADC0_DATA_A_IN => ADC_NX_IN(0),
+ ADC0_DATA_B_IN => ADC_B_IN(0),
+ ADC0_DATA_C_IN => ADC_A_IN(0),
+ ADC0_DATA_D_IN => ADC_D_IN(0),
+ ADC0_DCLK_IN => ADC_DCLK_IN(0),
+ ADC0_FCLK_IN => ADC_FCLK_IN(0),
+
+ ADC1_SCLK_IN => pll_adc_sampling_clk_o,
+ ADC1_SCLK_OUT => open,
+ ADC1_DATA_A_IN => ADC_NX_IN(1),
+ ADC1_DATA_B_IN => ADC_A_IN(1),
+ ADC1_DATA_C_IN => ADC_B_IN(1),
+ ADC1_DATA_D_IN => ADC_D_IN(1),
+ ADC1_DCLK_IN => ADC_DCLK_IN(1),
+ ADC1_FCLK_IN => ADC_FCLK_IN(1),
+
+ ADC0_DATA_A_OUT => adc_data,
+ ADC0_DATA_B_OUT => open,
+ ADC0_DATA_C_OUT => open,
+ ADC0_DATA_D_OUT => open,
+ ADC0_DATA_VALID_OUT => adc_data_clk,
+
+ ADC1_DATA_A_OUT => open,
+ ADC1_DATA_B_OUT => open,
+ ADC1_DATA_C_OUT => open,
+ ADC1_DATA_D_OUT => open,
+ ADC1_DATA_VALID_OUT => open,
+
+ ADC0_NOTLOCK_COUNTER => adc_notlock_ctr,
+ ADC1_NOTLOCK_COUNTER => open,
+
+ ERROR_ADC0_OUT => error_adc0,
+ ERROR_ADC1_OUT => error_adc1,
+ DEBUG_IN => adc_debug_type,
+ DEBUG_OUT => ADC_DEBUG
);
-
- -- Leave other bits untouched
- PROC_GRAY_DECODE: process(CLK_IN)
- begin
- if (rising_edge(CLK_IN) ) then
- nx_fifo_data(31) <= nx_fifo_data_f(31);
- nx_fifo_data(23) <= nx_fifo_data_f(23);
- nx_fifo_data(15) <= nx_fifo_data_f(15);
- nx_fifo_data(7 downto 1) <= nx_fifo_data_f(7 downto 1);
- end if;
- end process PROC_GRAY_DECODE;
- -- Replace Parity Bit by Parity Error Bit
- PROC_PARITY_CHECKER: process(CLK_IN)
- variable parity_bits : std_logic_vector(22 downto 0);
- variable parity : std_logic;
+ PROC_ADC_DATA_BIT_SHIFT: process(NX_TIMESTAMP_CLK_IN)
+ variable adcval : unsigned(11 downto 0) := (others => '0');
begin
- if (rising_edge(CLK_IN) ) then
- if (RESET_IN = '1') then
- nx_fifo_data(0) <= '0';
+ if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
+ if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
+ adc_data_s <= (others => '0');
+ adc_data_s_clk <= '0';
else
- -- Timestamp Bit #6 is excluded (funny nxyter-bug)
- parity_bits := nx_fifo_data_f(31) &
- nx_fifo_data_f(30 downto 24) &
- nx_fifo_data_f(21 downto 16) &
- nx_fifo_data_f(14 downto 8) &
- nx_fifo_data_f( 2 downto 1);
- parity := xor_all(parity_bits);
- if (parity /= nx_fifo_data_f(0)) then
- nx_fifo_data(0) <= '1';
- else
- nx_fifo_data(0) <= '0';
+ if (adc_bit_shift(3) = '1') then
+ adcval := unsigned(adc_data) rol
+ to_integer(adc_bit_shift(2 downto 0));
+ else
+ adcval := unsigned(adc_data) ror
+ to_integer(adc_bit_shift(2 downto 0));
+ end if;
+
+ if (adc_data_clk = '1') then
+ adc_data_s <= std_logic_vector(adcval);
+ adc_data_s_clk <= '1';
+ else
+ adc_data_s <= x"aff";
+ adc_data_s_clk <= '0';
end if;
end if;
end if;
- end process PROC_PARITY_CHECKER;
-
+ end process PROC_ADC_DATA_BIT_SHIFT;
+
-----------------------------------------------------------------------------
- -- FIFO Read Handler
+ -- Merge Data Streams Timestamps and ADC Value
-----------------------------------------------------------------------------
+
+ PROC_DATA_MERGE_HANDLER: process(NX_TIMESTAMP_CLK_IN)
+ begin
+ if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
+ if (RESET_NX_TIMESTAMP_CLK_IN = '1' ) then --r output_handler_reset = '1') then
+ data_frame <= (others => '0');
+ data_frame_clk <= '0';
+ merge_timeout_ctr <= (others => '0');
+ merge_timeout_error <= '0';
+ merge_error_ctr <= (others => '0');
+ else
+ if (nx_timestamp_delayed_clk = '1' and adc_data_s_clk = '1') then
+ data_frame(31 downto 0) <= nx_timestamp_delayed;
+ data_frame(43 downto 32) <= adc_data_s;
+ data_frame_clk <= '1';
+ merge_timeout_ctr <= (others => '0');
+ else
+ data_frame <= (others => '0');
+ data_frame_clk <= '0';
+ merge_timeout_ctr <= merge_timeout_ctr + 1;
+ end if;
- nx_fifo_read_enable <= not nx_fifo_empty;
+ -- Timeout?
+ if (merge_timeout_ctr > x"3") then
+ merge_timeout_error <= '1';
+ merge_error_ctr <= merge_error_ctr + 1;
+ else
+ merge_timeout_error <= '0';
+ end if;
+ end if;
+ end if;
+ end process PROC_DATA_MERGE_HANDLER;
+ -----------------------------------------------------------------------------
+ -- Clock Domain Transfer Data Stream
+ -----------------------------------------------------------------------------
+
+ fifo_data_stream_44to44_dc_1: fifo_data_stream_44to44_dc
+ port map (
+ Data => data_frame,
+ WrClock => NX_TIMESTAMP_CLK_IN,
+ RdClock => CLK_IN,
+ WrEn => fifo_write_enable,
+ RdEn => fifo_read_enable,
+ Reset => fifo_reset_i,
+ RPReset => fifo_reset_i,
+ Q => fifo_data,
+ Empty => fifo_empty,
+ Full => fifo_full
+ );
+ fifo_reset_i <= RESET_IN or fifo_reset;
+ fifo_write_enable <= not fifo_full and data_frame_clk;
+ fifo_read_enable <= not fifo_empty;
+
PROC_NX_FIFO_READ_ENABLE: process(CLK_IN)
begin
if (rising_edge(CLK_IN) ) then
- nx_fifo_data_valid_tt <= nx_fifo_read_enable;
+ fifo_data_clk_tt <= fifo_read_enable;
if(RESET_IN = '1') then
- nx_fifo_data_valid_t <= '0';
- nx_fifo_data_valid <= '0';
+ fifo_data_clk_t <= '0';
+ fifo_data_clk <= '0';
else
-- Delay read signal by two Clock Cycles
- nx_fifo_data_valid_t <= nx_fifo_data_valid_tt;
- nx_fifo_data_valid <= nx_fifo_data_valid_t;
+ fifo_data_clk_t <= fifo_data_clk_tt;
+ fifo_data_clk <= fifo_data_clk_t;
end if;
end if;
end process PROC_NX_FIFO_READ_ENABLE;
-
- PROC_NX_FIFO_READ: process(CLK_IN)
+
+ PROC_DATA_OUTPUT_HANDLER: process(CLK_IN)
begin
if (rising_edge(CLK_IN) ) then
- if (RESET_IN = '1') then
- nx_timestamp_t <= (others => '0');
- nx_new_timestamp <= '0';
- nx_new_timestamp_ctr <= (others => '0');
- for I in 1 to 15 loop
- nx_timestamp_d(I) <= (others => '0');
- end loop;
- parity_error <= '0';
+ if(RESET_IN = '1') then
+ nx_timestamp_o <= (others => '0');
+ adc_data_o <= (others => '0');
+ data_clk_o <= '0';
else
- if (nx_fifo_data_valid = '1') then
- -- Delay Data relative to ADC by 8 steps
- for I in 1 to 15 loop
- nx_timestamp_d(I) <= nx_timestamp_d(I - 1);
- end loop;
- nx_timestamp_d(0) <= nx_fifo_data;
- nx_timestamp_t <= nx_timestamp_d(to_integer(nx_fifo_delay));
- nx_new_timestamp <= '1';
- nx_new_timestamp_ctr <= nx_new_timestamp_ctr + 1;
- parity_error <= nx_timestamp_d(to_integer(nx_fifo_delay))(0);
+ if (fifo_data_clk = '1') then
+ nx_timestamp_o <= fifo_data(31 downto 0);
+ adc_data_o <= fifo_data(43 downto 32);
+ data_clk_o <= '1';
else
- nx_timestamp_t <= x"deadbeef";
- nx_new_timestamp <= '0';
- parity_error <= '0';
+ nx_timestamp_o <= (others => '0');
+ adc_data_o <= (others => '0');
+ data_clk_o <= '0';
end if;
end if;
end if;
- end process PROC_NX_FIFO_READ;
-
+ end process PROC_DATA_OUTPUT_HANDLER;
+
-----------------------------------------------------------------------------
-- Status Counters
-----------------------------------------------------------------------------
if (RESET_IN = '1' or reset_parity_error_ctr = '1') then
parity_error_counter <= (others => '0');
else
- if (parity_error = '1') then
- parity_error_counter <= parity_error_counter + 1;
- end if;
- end if;
- end if;
- end process PROC_PARITY_ERROR_COUNTER;
-
- -----------------------------------------------------------------------------
- -- ADC Fifo Handler
- -----------------------------------------------------------------------------
- PROC_ADC_DATA_READ: process(CLK_IN)
- variable adcval : unsigned(11 downto 0) := (others => '0');
- begin
- if (rising_edge(CLK_IN) ) then
- if (RESET_IN = '1') then
- adc_data_t <= (others => '0');
- adc_new_data <= '0';
- adc_new_data_ctr <= (others => '0');
- else
- if (adc_bit_shift(3) = '1') then
- adcval := unsigned(adc_data) rol
- to_integer(adc_bit_shift(2 downto 0));
- else
- adcval := unsigned(adc_data) ror
- to_integer(adc_bit_shift(2 downto 0));
- end if;
- if (adc_data_valid = '1') then
- adc_data_t <= std_logic_vector(adcval);
- adc_new_data <= '1';
- adc_new_data_ctr <= adc_new_data_ctr + 1;
- else
- adc_data_t <= x"aff";
- adc_new_data <= '0';
- end if;
- end if;
- end if;
- end process PROC_ADC_DATA_READ;
-
- -----------------------------------------------------------------------------
- -- Output handler
- -----------------------------------------------------------------------------
-
- PROC_DATA_STREAM_DELTA_T: process(CLK_IN)
- begin
- if (rising_edge(CLK_IN) ) then
- if (RESET_IN = '1') then
- new_adc_delta_t_ctr <= (others => '0');
- new_timestamp_delta_t_ctr <= (others => '0');
- new_adc_dt_error_ctr <= (others => '0');
- new_timestamp_dt_error_ctr <= (others => '0');
- else
- -- ADC
- if (adc_new_data = '1') then
- if (new_adc_delta_t_ctr < x"2" or
- new_adc_delta_t_ctr > x"3") then
- new_adc_dt_error_ctr <= new_adc_dt_error_ctr + 1;
- end if;
- new_adc_delta_t_ctr <= (others => '0');
- else
- new_adc_delta_t_ctr <= new_adc_delta_t_ctr + 1;
- end if;
-
- -- TimeStamp
- if (nx_new_timestamp = '1') then
- if (new_timestamp_delta_t_ctr < x"2" or
- new_timestamp_delta_t_ctr > x"3") then
- new_timestamp_dt_error_ctr <= new_timestamp_dt_error_ctr + 1;
- end if;
- new_timestamp_delta_t_ctr <= (others => '0');
- else
- new_timestamp_delta_t_ctr <= new_timestamp_delta_t_ctr + 1;
- end if;
-
- end if;
- end if;
- end process PROC_DATA_STREAM_DELTA_T;
-
- PROC_OUTPUT_MERGE_HANDLER: process(CLK_IN)
- begin
- if (rising_edge(CLK_IN) ) then
- if (RESET_IN = '1' or output_handler_reset = '1') then
- nx_timestamp_o <= (others => '0');
- adc_data_o <= (others => '0');
- new_data_o <= '0';
- merge_timeout_ctr <= (others => '0');
- merge_timeout_error <= '0';
- merge_error_ctr <= (others => '0');
- STATE <= WAIT_ADC;
- else
- case STATE is
-
- when WAIT_ADC =>
- STATE_d <= '0';
- if (adc_new_data = '1' and nx_new_timestamp = '1') then
- nx_timestamp_o <= nx_timestamp_t;
- adc_data_o <= adc_data_t;
- new_data_o <= '1';
- merge_timeout_ctr <= (others => '0');
- STATE <= WAIT_ADC;
- elsif (adc_new_data = '1') then
- nx_timestamp_o <= (others => '0');
- adc_data_o <= adc_data_t;
- new_data_o <= '0';
- STATE <= WAIT_TIMESTAMP;
- else
- nx_timestamp_o <= (others => '0');
- adc_data_o <= (others => '0');
- new_data_o <= '0';
- merge_timeout_ctr <= merge_timeout_ctr + 1;
- STATE <= WAIT_ADC;
- end if;
-
- when WAIT_TIMESTAMP =>
- STATE_d <= '1';
- if (merge_timeout_error = '1') then
- nx_timestamp_o <= (others => '0');
- adc_data_o <= (others => '0');
- new_data_o <= '0';
- merge_timeout_ctr <= (others => '0');
- STATE <= WAIT_ADC;
- else
- if (nx_new_timestamp = '1') then
- nx_timestamp_o <= nx_timestamp_t;
- new_data_o <= '1';
- merge_timeout_ctr <= (others => '0');
- STATE <= WAIT_ADC;
- else
- nx_timestamp_o <= (others => '0');
- new_data_o <= '0';
- merge_timeout_ctr <= merge_timeout_ctr + 1;
- STATE <= WAIT_TIMESTAMP;
- end if;
- end if;
-
- end case;
-
- -- Timeout?
- if (merge_timeout_ctr > x"3") then
- merge_timeout_error <= '1';
- merge_error_ctr <= merge_error_ctr + 1;
- else
- merge_timeout_error <= '0';
+ if (parity_error_c100 = '1') then
+ parity_error_counter <= parity_error_counter + 1;
end if;
end if;
end if;
- end process PROC_OUTPUT_MERGE_HANDLER;
+ end process PROC_PARITY_ERROR_COUNTER;
+
-----------------------------------------------------------------------------
-- Rate Counters + Rate Error Check
-----------------------------------------------------------------------------
+
PROC_RATE_COUNTER: process(CLK_IN)
begin
if (rising_edge(CLK_IN) ) then
if (rate_timer_ctr < x"5f5e100") then
rate_timer_ctr <= rate_timer_ctr + 1;
- if (nx_fifo_data_valid = '1') then
+ if (nx_frame_clk_c100 = '1') then
nx_frame_rate_ctr <= nx_frame_rate_ctr + 1;
end if;
- if (adc_data_valid = '1') then
+ if (adc_data_clk_c100 = '1') then
adc_frame_rate_ctr <= adc_frame_rate_ctr + 1;
end if;
- if (new_data_o = '1') then
+ if (data_clk_o = '1') then
frame_rate_ctr <= frame_rate_ctr + 1;
end if;
- if (parity_error = '1') then
+ if (parity_error_c100 = '1') then
parity_err_rate_ctr <= parity_err_rate_ctr + 1;
end if;
else
parity_err_rate <= parity_err_rate_ctr;
nx_frame_rate_ctr(27 downto 1) <= (others => '0');
- nx_frame_rate_ctr(0) <= nx_fifo_data_valid;
+ nx_frame_rate_ctr(0) <= nx_frame_clk_c100;
adc_frame_rate_ctr(27 downto 1) <= (others => '0');
- adc_frame_rate_ctr(0) <= adc_data_valid;
+ adc_frame_rate_ctr(0) <= adc_data_clk_c100;
frame_rate_ctr(27 downto 1) <= (others => '0');
- frame_rate_ctr(0) <= new_data_o;
+ frame_rate_ctr(0) <= data_clk_o;
parity_err_rate_ctr(27 downto 1) <= (others => '0');
- parity_err_rate_ctr(0) <= parity_error;
+ parity_err_rate_ctr(0) <= parity_error_c100;
end if;
end if;
end if;
end if;
end if;
end process PROC_RATE_ERRORS;
+
+ PROC_DATA_STREAM_DELTA_T: process(NX_TIMESTAMP_CLK_IN)
+ begin
+ if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then
+ if (RESET_NX_TIMESTAMP_CLK_IN = '1') then
+ new_adc_delta_t_ctr <= (others => '0');
+ new_timestamp_delta_t_ctr <= (others => '0');
+ new_adc_dt_error_ctr <= (others => '0');
+ new_timestamp_dt_error_ctr <= (others => '0');
+ else
+ -- ADC
+ if (adc_data_clk = '1') then
+ if (new_adc_delta_t_ctr /= x"3" ) then
+ new_adc_dt_error_ctr <= new_adc_dt_error_ctr + 1;
+ end if;
+ new_adc_delta_t_ctr <= (others => '0');
+ else
+ new_adc_delta_t_ctr <= new_adc_delta_t_ctr + 1;
+ end if;
+
+ -- TimeStamp
+ if (nx_frame_clk = '1') then
+ if (new_timestamp_delta_t_ctr /= x"3") then
+ new_timestamp_dt_error_ctr <= new_timestamp_dt_error_ctr + 1;
+ end if;
+ new_timestamp_delta_t_ctr <= (others => '0');
+ else
+ new_timestamp_delta_t_ctr <= new_timestamp_delta_t_ctr + 1;
+ end if;
+
+ end if;
+ end if;
+ end process PROC_DATA_STREAM_DELTA_T;
+
+ -----------------------------------------------------------------------------
+ -- Reset Handler
+ -----------------------------------------------------------------------------
+
+ PROC_RESET_HANDLER: process(CLK_IN)
+ begin
+ if (rising_edge(CLK_IN) ) then
+ if( RESET_IN = '1' ) then
+ frame_rates_reset <= '0';
+ fifo_reset <= '0';
+ sampling_clk_reset <= '0';
+ adc_reset_p <= '0';
+ adc_reset <= '0';
+ output_handler_reset <= '0';
+
+ rs_wait_timer_start <= '0';
+ rs_timeout_timer_start <= '0';
+ rs_timeout_timer_reset <= '1';
+ reset_handler_counter <= (others => '0');
+ reset_handler_busy <= '0';
+ reset_timeout_flag <= '0';
+ startup_reset <= '1';
+ nx_timestamp_reset_o <= '0';
+ R_STATE <= R_IDLE;
+ else
+ frame_rates_reset <= '0';
+ fifo_reset <= '0';
+ sampling_clk_reset <= '0';
+ adc_reset_p <= '0';
+ adc_reset <= '0';
+ output_handler_reset <= '0';
+
+ rs_wait_timer_start <= '0';
+ rs_timeout_timer_start <= '0';
+ rs_timeout_timer_reset <= '0';
+ reset_handler_busy <= '1';
+ nx_timestamp_reset_o <= '0';
+
+ debug_state <= x"0";
+
+ if (reset_handler_counter_clear = '1') then
+ reset_handler_counter <= (others => '0');
+ end if;
+
+ if (rs_timeout_timer_done = '1') then
+ -- Reset Timeout
+ reset_timeout_flag <= '1';
+ R_STATE <= R_IDLE;
+ else
+
+ case R_STATE is
+ when R_IDLE =>
+ if (reset_for_offline = '1' or
+ pll_adc_not_lock = '1' or
+ adc_reset_sync = '1' or
+ reset_handler_start_r = '1' or
+ startup_reset = '1'
+ ) then
+ if (reset_handler_counter_clear = '0') then
+ reset_handler_counter <= reset_handler_counter + 1;
+ end if;
+ R_STATE <= R_SET_ALL_RESETS;
+ else
+ reset_handler_busy <= '0';
+ R_STATE <= R_IDLE;
+ end if;
+
+ when R_SET_ALL_RESETS =>
+ frame_rates_reset <= '1';
+ fifo_reset <= '1';
+ sampling_clk_reset <= '1';
+ adc_reset_p <= '1';
+ adc_reset <= '1';
+ output_handler_reset <= '1';
+
+ nx_timestamp_reset_o <= '1';
+
+ rs_wait_timer_start <= '1'; -- wait 1mue to settle
+ R_STATE <= R_WAIT_1;
+ debug_state <= x"1";
+
+ when R_WAIT_1 =>
+ if (rs_wait_timer_done = '0') then
+ fifo_reset <= '1';
+ sampling_clk_reset <= '1';
+ adc_reset <= '1';
+ output_handler_reset <= '1';
+ R_STATE <= R_WAIT_1;
+ else
+ -- Release NX Fifo Reset + Start Timeout Handler
+ sampling_clk_reset <= '1';
+ adc_reset <= '1';
+ output_handler_reset <= '1';
+ rs_timeout_timer_start <= '1';
+ R_STATE <= R_WAIT_NX_FRAME_RATE_OK;
+ end if;
+ debug_state <= x"2";
+
+ when R_WAIT_NX_FRAME_RATE_OK =>
+ if (nx_frame_rate_offline = '0' and
+ nx_frame_rate_error = '0') then
+ -- Release PLL Reset
+ adc_reset <= '1';
+ output_handler_reset <= '1';
+ R_STATE <= R_PLL_WAIT_LOCK;
+ else
+ sampling_clk_reset <= '1';
+ adc_reset <= '1';
+ output_handler_reset <= '1';
+ R_STATE <= R_WAIT_NX_FRAME_RATE_OK;
+ end if;
+ debug_state <= x"3";
+
+ when R_PLL_WAIT_LOCK =>
+ if (pll_adc_not_lock = '1') then
+ adc_reset <= '1';
+ output_handler_reset <= '1';
+ R_STATE <= R_PLL_WAIT_LOCK;
+ else
+ -- Release ADC Reset
+ output_handler_reset <= '1';
+ R_STATE <= R_WAIT_ADC_OK;
+ end if;
+ debug_state <= x"4";
+
+ when R_WAIT_ADC_OK =>
+ if (error_adc0 = '0' and
+ adc_frame_rate_error = '0') then
+ -- Release Output Handler Reset
+ R_STATE <= R_WAIT_DATA_HANDLER_OK;
+ else
+ output_handler_reset <= '1';
+ R_STATE <= R_WAIT_ADC_OK;
+ end if;
+ debug_state <= x"5";
+
+ when R_WAIT_DATA_HANDLER_OK =>
+ if (frame_rate_error = '0') then
+ startup_reset <= '0';
+ reset_timeout_flag <= '0';
+ rs_timeout_timer_reset <= '1';
+ R_STATE <= R_IDLE;
+ else
+ R_STATE <= R_WAIT_DATA_HANDLER_OK;
+ end if;
+ debug_state <= x"6";
+
+ end case;
+ end if;
+ end if;
+ end if;
+ end process PROC_RESET_HANDLER;
+
+ -----------------------------------------------------------------------------
+ -- Error Status
+ -----------------------------------------------------------------------------
+ PROC_ERROR_STATUS: process(CLK_IN)
+ begin
+ if (rising_edge(CLK_IN)) then
+ if (RESET_IN = '1') then
+ error_status_bits <= (others => '0');
+ error_o <= '0';
+ else
+ if (error_adc0 = '1' or
+ pll_adc_not_lock = '1' or
+ nx_frame_rate_offline = '1' or
+ nx_frame_rate_error = '1' or
+ adc_clk_ok_c100 = '0' or
+ parity_error_c100 = '1' or
+ reg_nx_frame_synced = '0' or
+ adc_frame_rate_error = '1' or
+ parity_rate_error = '1'
+ ) then
+ error_o <= '1';
+ else
+ error_o <= '0';
+ end if;
+
+ error_status_bits(0) <= nx_frame_rate_offline;
+ error_status_bits(1) <= frame_rate_error;
+ error_status_bits(2) <= nx_frame_rate_error;
+ error_status_bits(3) <= adc_frame_rate_error;
+ error_status_bits(4) <= parity_rate_error;
+ error_status_bits(5) <= not reg_nx_frame_synced;
+ error_status_bits(6) <= error_adc0;
+ error_status_bits(7) <= pll_adc_not_lock;
+ error_status_bits(8) <= not adc_clk_ok_c100;
+ error_status_bits(9) <= '0';
+ error_status_bits(10) <= '0';
+ error_status_bits(11) <= '0';
+ end if;
+ end if;
+ end process PROC_ERROR_STATUS;
-----------------------------------------------------------------------------
-- TRBNet Slave Bus
-----------------------------------------------------------------------------
-- Give status info to the TRB Slow Control Channel
- PROC_FIFO_REGISTERS: process(CLK_IN)
+ PROC_SLAVE_BUS: process(CLK_IN)
begin
if (rising_edge(CLK_IN) ) then
if( RESET_IN = '1' ) then
slv_no_more_data_o <= '0';
reset_resync_ctr <= '0';
reset_parity_error_ctr <= '0';
- debug_adc <= (others => '0');
+ debug_mode <= (others => '0');
johnson_counter_sync_r <= "00";
pll_adc_sample_clk_dphase_r <= x"0";
- pll_adc_sample_clk_finedelb <= (others => '0');
+ pll_adc_sample_clk_finedelb_r <= (others => '0');
pll_adc_not_lock_ctr_clear <= '0';
- nx_fifo_delay <= x"8";
+ nx_timestamp_delay_r <= "010";
reset_handler_start_r <= '0';
reset_handler_counter_clear <= '0';
adc_bit_shift <= x"0";
adc_debug_type <= (others => '0');
+ fifo_full_r <= '0';
+ fifo_empty_r <= '0';
else
slv_data_out_o <= (others => '0');
slv_ack_o <= '0';
pll_adc_not_lock_ctr_clear <= '0';
reset_handler_start_r <= '0';
reset_handler_counter_clear <= '0';
+ fifo_full_r <= fifo_full;
+ fifo_empty_r <= fifo_empty;
if (SLV_READ_IN = '1') then
case SLV_ADDR_IN is
slv_ack_o <= '1';
when x"000e" =>
- slv_data_out_o(3 downto 0) <= pll_adc_sample_clk_finedelb;
+ slv_data_out_o(3 downto 0) <= pll_adc_sample_clk_finedelb_r;
slv_data_out_o(31 downto 4) <= (others => '0');
slv_ack_o <= '1';
slv_ack_o <= '1';
when x"0010" =>
- slv_data_out_o(3 downto 0) <= std_logic_vector(nx_fifo_delay);
- slv_data_out_o(31 downto 4) <= (others => '0');
+ slv_data_out_o(2 downto 0) <=
+ std_logic_vector(nx_timestamp_delay_r);
+ slv_data_out_o(3) <= '0';
+ slv_data_out_o(5 downto 4) <=
+ std_logic_vector(nx_frame_word_delay_r);
+ slv_data_out_o(31 downto 6) <= (others => '0');
slv_ack_o <= '1';
when x"0011" =>
- slv_data_out_o(0) <= nx_fifo_full;
- slv_data_out_o(1) <= nx_fifo_empty;
+ slv_data_out_o(0) <= fifo_full_r;
+ slv_data_out_o(1) <= fifo_empty_r;
slv_data_out_o(2) <= '0';
slv_data_out_o(3) <= '0';
- slv_data_out_o(4) <= nx_fifo_data_valid;
- slv_data_out_o(5) <= adc_new_data;
- slv_data_out_o(29 downto 5) <= (others => '0');
+ slv_data_out_o(4) <= '0';
+ slv_data_out_o(5) <= '0';
+ slv_data_out_o(29 downto 6) <= (others => '0');
slv_data_out_o(30) <= '0';
slv_data_out_o(31) <= reg_nx_frame_synced;
slv_ack_o <= '1';
slv_ack_o <= '1';
when x"0013" =>
- slv_data_out_o <= nx_timestamp_t;
+ slv_data_out_o <= (others => '0');--nx_timestamp_t;
slv_ack_o <= '1';
when x"0014" =>
slv_ack_o <= '1';
when x"001c" =>
- slv_data_out_o(11 downto 0) <= adc_data_t;
+ slv_data_out_o(11 downto 0) <= adc_data_o;
slv_data_out_o(31 downto 12) <= (others => '0');
slv_ack_o <= '1';
- when x"001d" =>
- slv_data_out_o(11 downto 0) <= test_adc_data;
- slv_data_out_o(31 downto 12) <= (others => '0');
- slv_ack_o <= '1';
-
when x"001e" =>
- slv_data_out_o(1 downto 0) <= debug_adc;
- slv_data_out_o(31 downto 2) <= (others => '0');
+ slv_data_out_o(2 downto 0) <= debug_mode;
+ slv_data_out_o(31 downto 3) <= (others => '0');
slv_ack_o <= '1';
when x"001f" =>
slv_ack_o <= '1';
when x"000e" =>
- pll_adc_sample_clk_finedelb <= SLV_DATA_IN(3 downto 0);
+ pll_adc_sample_clk_finedelb_r <= SLV_DATA_IN(3 downto 0);
reset_handler_start_r <= '1';
slv_ack_o <= '1';
slv_ack_o <= '1';
when x"0010" =>
- nx_fifo_delay <=
- unsigned(SLV_DATA_IN(3 downto 0));
+ nx_timestamp_delay_r <=
+ unsigned(SLV_DATA_IN(2 downto 0));
slv_ack_o <= '1';
when x"0012" =>
slv_ack_o <= '1';
when x"001e" =>
- debug_adc <= SLV_DATA_IN(1 downto 0);
+ debug_mode <= SLV_DATA_IN(2 downto 0);
slv_ack_o <= '1';
when x"001f" =>
end if;
end if;
end if;
- end process PROC_FIFO_REGISTERS;
-
- -- ErrorPROC_ERROR: process(CLK_IN)
- PROC_ERROR: process(CLK_IN)
- begin
- if (rising_edge(CLK_IN)) then
- if (RESET_IN = '1') then
- error_status_bits <= (others => '0');
- error_o <= '0';
- else
- if (error_adc0 = '1' or
- pll_adc_not_lock = '1' or
- nx_frame_rate_offline = '1' or
- nx_frame_rate_error = '1' or
- adc_clk_ok = '0' or
- parity_error = '1' or
- reg_nx_frame_synced = '0' or
- adc_frame_rate_error = '1' or
- parity_rate_error = '1'
- ) then
- error_o <= '1';
- else
- error_o <= '0';
- end if;
-
- error_status_bits(0) <= nx_frame_rate_offline;
- error_status_bits(1) <= frame_rate_error;
- error_status_bits(2) <= nx_frame_rate_error;
- error_status_bits(3) <= adc_frame_rate_error;
- error_status_bits(4) <= parity_rate_error;
- error_status_bits(5) <= not reg_nx_frame_synced;
- error_status_bits(6) <= error_adc0;
- error_status_bits(7) <= pll_adc_not_lock;
- error_status_bits(8) <= not adc_clk_ok;
- error_status_bits(9) <= '0';
- error_status_bits(10) <= '0';
- error_status_bits(11) <= '0';
- end if;
- end if;
- end process PROC_ERROR;
+ end process PROC_SLAVE_BUS;
-- Output Signals
NX_TIMESTAMP_RESET_OUT <= nx_timestamp_reset_o;
NX_TIMESTAMP_OUT <= nx_timestamp_o;
ADC_DATA_OUT <= adc_data_o;
- NEW_DATA_OUT <= new_data_o;
+ DATA_CLK_OUT <= data_clk_o;
ADC_SCLK_LOCK_OUT <= pll_adc_sampling_clk_lock;
ERROR_OUT <= error_o;
jspc29 / trb3.git / commitdiff