update sync media interface and longer network reset

diff --git a/media_interfaces/med_ecp3_sfp_sync_4.vhd b/media_interfaces/med_ecp3_sfp_sync_4.vhd
index 9501288f90db08ef9151bd84fc20018f6e0f0bd5..17745db90db93a448fe54be6f0fce2b15f474af2 100644 (file)
--- a/media_interfaces/med_ecp3_sfp_sync_4.vhd
+++ b/media_interfaces/med_ecp3_sfp_sync_4.vhd
@@ -66,6 +66,7 @@ signal clk_tx_full, clk_tx_half : std_logic_vector(3 downto 0);
 
 signal tx_data           : std_logic_vector(4*8-1 downto 0);
 signal tx_k              : std_logic_vector(3 downto 0);
+signal tx_cd             : std_logic_vector(3 downto 0);
 signal rx_data           : std_logic_vector(4*8-1 downto 0);
 signal rx_k              : std_logic_vector(3 downto 0);
 signal rx_error          : std_logic_vector(3 downto 0);
@@ -125,7 +126,7 @@ SD_TXDIS_OUT <= (others => RESET);
       fpga_rxrefclk_ch0    => CLK_INTERNAL_FULL,
       txdata_ch0           => tx_data(0*8+7 downto 0*8),
       tx_k_ch0             => tx_k(0),
-      tx_force_disp_ch0    => '0',
+      tx_force_disp_ch0    => tx_cd(0),
       tx_disp_sel_ch0      => '0',
       rxdata_ch0           => rx_data(0*8+7 downto 0*8),
       rx_k_ch0             => rx_k(0),
@@ -157,7 +158,7 @@ SD_TXDIS_OUT <= (others => RESET);
       fpga_rxrefclk_ch1    => CLK_INTERNAL_FULL,
       txdata_ch1           => tx_data(1*8+7 downto 1*8),
       tx_k_ch1             => tx_k(1),
-      tx_force_disp_ch1    => '0',
+      tx_force_disp_ch1    => tx_cd(1),
       tx_disp_sel_ch1      => '0',
       rxdata_ch1           => rx_data(1*8+7 downto 1*8),
       rx_k_ch1             => rx_k(1),
@@ -189,7 +190,7 @@ SD_TXDIS_OUT <= (others => RESET);
       fpga_rxrefclk_ch2    => CLK_INTERNAL_FULL,
       txdata_ch2           => tx_data(2*8+7 downto 2*8),
       tx_k_ch2             => tx_k(2),
-      tx_force_disp_ch2    => '0',
+      tx_force_disp_ch2    => tx_cd(2),
       tx_disp_sel_ch2      => '0',
       rxdata_ch2           => rx_data(2*8+7 downto 2*8),
       rx_k_ch2             => rx_k(2),
@@ -221,7 +222,7 @@ SD_TXDIS_OUT <= (others => RESET);
       fpga_rxrefclk_ch3    => CLK_INTERNAL_FULL,
       txdata_ch3           => tx_data(3*8+7 downto 3*8),
       tx_k_ch3             => tx_k(3),
-      tx_force_disp_ch3    => '0',
+      tx_force_disp_ch3    => tx_cd(3),
       tx_disp_sel_ch3      => '0',
       rxdata_ch3           => rx_data(3*8+7 downto 3*8),
       rx_k_ch3             => rx_k(3),
@@ -296,6 +297,7 @@ gen_control : for i in 0 to 3 generate
         
         TX_DATA       => tx_data(i*8+7 downto i*8),
         TX_K          => tx_k(i),
+        TX_CD         => tx_cd(i),
         RX_DATA       => rx_data(i*8+7 downto i*8),
         RX_K          => rx_k(i),
         

diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd
index 715b2362e06f7e06f4f7b0bf6fa7e4093b64f261..1ed066eb6d3b95cd0a52599b5c9cc38801a66e5a 100644 (file)
--- a/media_interfaces/sync/med_sync_control.vhd
+++ b/media_interfaces/sync/med_sync_control.vhd
@@ -37,6 +37,7 @@ entity med_sync_control is
     
     TX_DATA       : out std_logic_vector(7 downto 0);
     TX_K          : out std_logic;
+    TX_CD         : out std_logic;
     RX_DATA       : in  std_logic_vector(7 downto 0);
     RX_K          : in  std_logic;
     
@@ -63,7 +64,7 @@ architecture med_sync_control_arch of med_sync_control is
 signal rx_fsm_state : std_logic_vector(3 downto 0);
 signal tx_fsm_state : std_logic_vector(3 downto 0);
 signal wa_position_rx : std_logic_vector(3 downto 0);
-signal start_timer       : unsigned(20 downto 0) := (others => '0');
+signal start_timer       : unsigned(21 downto 0) := (others => '0');
 
 signal request_retr_i     : std_logic;
 signal start_retr_i       : std_logic;
@@ -201,6 +202,7 @@ THE_TX : tx_control
 
     TX_DATA_OUT            => TX_DATA,
     TX_K_OUT               => TX_K,
+    TX_CD_OUT              => TX_CD,
 
     REQUEST_RETRANSMIT_IN  => request_retr_i,             --TODO
     REQUEST_POSITION_IN    => request_retr_position_i,    --TODO

diff --git a/media_interfaces/sync/med_sync_define.vhd b/media_interfaces/sync/med_sync_define.vhd
index c5cf3483053926603642625a2243b8c6aae1c02e..9eaf330fbd0d9bff557a1d518a01230723ce4fc3 100644 (file)
--- a/media_interfaces/sync/med_sync_define.vhd
+++ b/media_interfaces/sync/med_sync_define.vhd
@@ -65,6 +65,7 @@ component tx_control is
 
     TX_DATA_OUT                    : out std_logic_vector( 7 downto 0);
     TX_K_OUT                       : out std_logic;
+    TX_CD_OUT                      : out std_logic;
 
     REQUEST_RETRANSMIT_IN          : in  std_logic := '0';
     REQUEST_POSITION_IN            : in  std_logic_vector( 7 downto 0) := (others => '0');

diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd
index ccc72b07cc10898348e6ba3abb1b5d8d391008ca..2a049160cde165543177c976b6f8c901977556ed 100644 (file)
--- a/media_interfaces/sync/rx_control.vhd
+++ b/media_interfaces/sync/rx_control.vhd
@@ -64,7 +64,7 @@ signal ct_fifo_afull       : std_logic;
 signal last_ct_fifo_empty  : std_logic;
 signal last_ct_fifo_read   : std_logic;
 
-signal tmp_link_ready_i    : std_logic := '0';
+signal idle_hist_i         : std_logic_vector(3 downto 0) := x"0";
 signal got_link_ready_i    : std_logic := '0';
 signal start_retr_i        : std_logic;
 signal start_retr_pos_i    : std_logic_vector(7 downto 0);
@@ -139,6 +139,8 @@ PROC_RX_FSM : process begin
   ct_fifo_write        <= '0';
   start_retr_i         <= '0';
   rx_dlm_i             <= '0';
+  idle_hist_i(3 downto 1) <= idle_hist_i(2 downto 0);
+  idle_hist_i(0)       <= got_link_ready_i;
   
   case rx_state is
     when SLEEP =>
@@ -177,13 +179,10 @@ PROC_RX_FSM : process begin
       rx_state_bits         <= x"3";
       rx_state              <= FIRST;
       next_sop              <= '1';
-      if reg_rx_k_in = '0' and reg_rx_data_in = D_IDLE0 then
-        tmp_link_ready_i    <= '0';
-        got_link_ready_i    <= tmp_link_ready_i;
-      elsif  reg_rx_k_in = '0' and reg_rx_data_in = D_IDLE1 then
-        got_link_ready_i    <= '1';
-        tmp_link_ready_i    <= '1';
-      else
+      if  reg_rx_k_in = '0' and reg_rx_data_in = D_IDLE1 then
+        idle_hist_i(0)      <= '1';
+        got_link_ready_i    <= got_link_ready_i or (idle_hist_i(1) and idle_hist_i(3));
+      elsif  reg_rx_k_in = '1' then
         rx_state <= SLEEP;
       end if;
       
@@ -271,7 +270,7 @@ STAT_REG_OUT(4)            <= got_link_ready_i;
 STAT_REG_OUT(5)            <= ct_fifo_afull;
 STAT_REG_OUT(6)            <= ct_fifo_empty;
 STAT_REG_OUT(7)            <= ct_fifo_write;
-STAT_REG_OUT(15 downto 8)  <= rx_data(7 downto 0);
+STAT_REG_OUT(15 downto 8)  <= reg_rx_data_in when rising_edge(clk_100); --rx_data(7 downto 0);
 STAT_REG_OUT(16)           <= rx_data(16);
 STAT_REG_OUT(17)           <= '0';
 STAT_REG_OUT(31 downto 18) <= (others => '0');

diff --git a/media_interfaces/sync/tx_control.vhd b/media_interfaces/sync/tx_control.vhd
index 78e97767b1bea07418196c005d9f5814a3c83068..298e8d25167601d1cf12cedbea19a9545b207703 100644 (file)
--- a/media_interfaces/sync/tx_control.vhd
+++ b/media_interfaces/sync/tx_control.vhd
@@ -103,6 +103,7 @@ architecture arch of tx_control is
   signal crc_en                  : std_logic;
   signal crc_data                : std_logic_vector(7 downto 0);
   signal first_idle              : std_logic;
+  signal toggle_idle             : std_logic;
 begin
 
 ----------------------------------------------------------------------
@@ -248,10 +249,12 @@ begin
             first_idle         <= first_idle;
 
           when SEND_IDLE_H =>
-            if rx_allow_qtx = '1' then
+            if rx_allow_qtx = '1' or toggle_idle = '1' then
               TX_DATA_OUT        <= D_IDLE1;
+              toggle_idle        <= rx_allow_qtx;
             else
               TX_DATA_OUT        <= D_IDLE0;
+              toggle_idle        <= '1';
             end if;
             TX_CD_OUT            <= first_idle;
             first_idle           <= '0';

diff --git a/trb_net16_hub_streaming_port_sctrl_record.vhd b/trb_net16_hub_streaming_port_sctrl_record.vhd
index 5cca33b85395f5ae9fa81e8d6ea4f33d4f38c00f..0dfa337c7a9443f39c0f416a44bb92c8bfc858c7 100644 (file)
--- a/trb_net16_hub_streaming_port_sctrl_record.vhd
+++ b/trb_net16_hub_streaming_port_sctrl_record.vhd
@@ -223,11 +223,11 @@ begin
   
   make_gbe_reset : process begin
     wait until rising_edge(CLK);
-    if(EXTERNAL_SEND_RESET = '1') then
+    if EXTERNAL_SEND_RESET = '1' or med_stat_op((MII_NUMBER-1)*16+15) = '1' then
       external_send_reset_long <= '1';
       external_send_reset_timer <= '1';
     end if;
-    if timer_ticks(0) = '1' then
+    if timer_ticks(1) = '1' then
       external_send_reset_timer <= '0';
       external_send_reset_long  <= external_send_reset_timer;
     end if;
@@ -691,4 +691,4 @@ end generate;
 -- STAT_DEBUG(7) <= '0';
 
 
-end architecture;
\ No newline at end of file
+end architecture;