D16_PACKET_NUM_IN: in STD_LOGIC_VECTOR(1 downto 0)
);
end component;
-
-
+component DCM
+--
+ generic (
+ DFS_FREQUENCY_MODE : string := "LOW";
+ CLKFX_DIVIDE : integer := 4; -- Min 1 Max 32 (25MHz 3/4 M/D)
+ CLKFX_MULTIPLY : integer := 2 ; -- Min 2 Max 32 (60MHz 20/11 M/D)
+-- CLKFX_MULTIPLY : integer := 3 ; -- Min 2 Max 32 (63MHz 19/10 M/D)
+ CLKIN_PERIOD : real := 10.0 ; -- 30.30ns
+ STARTUP_WAIT : boolean := FALSE
+ );
+
+ port ( CLKIN : in std_logic;
+ CLKFB : in std_logic;
+ DSSEN : in std_logic;
+ PSINCDEC : in std_logic;
+ PSEN : in std_logic;
+ PSCLK : in std_logic;
+ RST : in std_logic;
+ CLK0 : out std_logic;
+ CLK90 : out std_logic;
+ CLK180 : out std_logic;
+ CLK270 : out std_logic;
+ CLK2X : out std_logic;
+ CLK2X180 : out std_logic;
+ CLKDV : out std_logic;
+ CLKFX : out std_logic;
+ CLKFX180 : out std_logic;
+ LOCKED : out std_logic;
+ PSDONE : out std_logic;
+ STATUS : out std_logic_vector(7 downto 0)
+ );
+end component;
+ component trb_net_sbuf
+ generic (DATA_WIDTH : integer := 16;
+ VERSION: integer := 0);
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+ -- port to combinatorial logic
+ COMB_DATAREADY_IN: in STD_LOGIC; --comb logic provides data word
+ COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle
+ COMB_READ_IN: in STD_LOGIC; --comb logic IS reading
+ COMB_DATA_IN: in STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ -- Port to synchronous output.
+ SYN_DATAREADY_OUT: out STD_LOGIC;
+ SYN_DATA_OUT: out STD_LOGIC_VECTOR (DATA_WIDTH-1 downto 0); -- Data word
+ SYN_READ_IN: in STD_LOGIC;
+ -- Status and control port
+ STAT_BUFFER: out STD_LOGIC
+ );
+ END component;
+
signal CLK_TRANS : std_logic;
signal fifo_data_in, next_fifo_data_in : std_logic_vector(17 downto 0);
signal next_next_fifo_data_in, buf_next_fifo_data_in : std_logic_vector(7 downto 0);
signal data_valid, next_data_valid : std_logic;
--signal next_recv_data, recv_data : std_logic_vector(15 downto 0);
-signal next_INT_DATA_OUT, buf_INT_DATA_OUT : std_logic_vector(15 downto 0);
+signal buf_INT_DATA_OUT : std_logic_vector(17 downto 0);
signal next_INT_DATAREADY_OUT, buf_INT_DATAREADY_OUT : std_logic;
signal next_int_packet_nr_out, buf_int_packet_nr_out : std_logic_vector(1 downto 0);
signal buf_INT_READ_OUT : std_logic;
signal next_send_dataready1, send_dataready1 : std_logic;
signal next_send_packet1, send_packet1 : std_logic;
signal next_fifo_data_ready, fifo_data_ready : std_logic;
-signal next_earlier_fifo_data_ready, earlier_fifo_data_ready : std_logic;
--signal recv_state, next_recv_state : std_logic_vector(1 downto 0);
signal CONV_DATA_OUT : std_logic_vector(15 downto 0);
signal CONV_READ_IN: std_logic;
signal CONV_PACKET_NR_IN, CONV_PACKET_NR_OUT: std_logic_vector(1 downto 0);
-
+signal CLK0_Out, FB_CLK, CLK2X_Out : std_logic;
+signal sbuff_status : std_logic;
+signal sbuff_next_read_out : std_logic;
+signal buf_comb_data_in : std_logic_vector(17 downto 0);
begin
-----------------------------------------------------------------------
+--
+-- CONV_DATAREADY_OUT <= INT_DATAREADY_IN;
+-- CONV_DATA_OUT <= INT_DATA_IN;
+-- CONV_PACKET_NR_OUT <= INT_PACKET_NR_IN;
+-- INT_READ_OUT <= CONV_READ_IN;
+
CONV16to18 : trb_net_18_to_16_converter
generic map(
VERSION => 0
-- Getting clock from LVDS
-----------------------------------------------------------------------
- buf_med_transmission_clk_in <= MED_TRANSMISSION_CLK_IN;
- -- BUFG Instantiation for CLKFX
- U0_BUFG: BUFG
- port map (
- I => buf_MED_TRANSMISSION_CLK_IN,
- O => CLK_TRANS
- );
+CLK_TRANS <= buf_MED_TRANSMISSION_CLK_IN;
+
+ U4_BUFG: BUFG
+ port map (
+ I => MED_TRANSMISSION_CLK_IN,
+ O => buf_MED_TRANSMISSION_CLK_IN
+ );
+--
+-- U_DCM: DCM
+-- generic map(
+-- CLKFX_DIVIDE => 1, -- Min 1 Max 32
+-- CLKFX_MULTIPLY => 2, -- Min 2 Max 32
+-- CLKIN_PERIOD => 20.20, -- 30.30ns
+-- STARTUP_WAIT => FALSE
+-- )
+-- port map (
+-- CLKIN => buf_MED_TRANSMISSION_CLK_IN,
+-- CLKFB => FB_CLK,
+-- DSSEN => '0',
+-- PSINCDEC => '0',
+-- PSEN => '0',
+-- PSCLK => '0',
+-- RST => RESET,
+-- CLK0 => CLK0_Out, -- for feedback
+-- CLK2X => CLK2X_Out
+-- );
+--
+-- -- BUFG Instantiation for CLKFX
+-- U0_BUFG: BUFG
+-- port map (
+-- I => CLK2X_Out,
+-- O => CLK_TRANS
+-- );
+-- -- BUFG Instantiation for CLK0
+-- U1_BUFG: BUFG
+-- port map (
+-- I => CLK0_Out,
+-- O => FB_CLK
+-- );
-----------------------------------------------------------------------
--BUG: No parity check for last part of packet, failure is passed to next packet!
- recv : process(packet_in_state, buf_next_fifo_data_in, buf_MED_DATA_IN, buf_MED_CARRIER_IN, buf_MED_PARITY_IN, data_valid)
+ recv : process(packet_in_state, buf_MED_DATA_IN, buf_MED_CARRIER_IN, buf_MED_PARITY_IN,
+ data_valid, fifo_data_in)
--variable data_valid : std_logic;
begin
- next_data_valid <= buf_MED_PARITY_IN xnor xor_all(buf_MED_DATA_IN(7 downto 0));
+ next_data_valid <= (buf_MED_PARITY_IN xnor xor_all(buf_MED_DATA_IN(7 downto 0)))
+ and (packet_in_state or data_valid);
next_fifo_write_enable <= buf_MED_CARRIER_IN AND NOT packet_in_state;
- next_next_fifo_data_in <= (others => '0');
next_fifo_data_in(17) <= data_valid;
next_fifo_data_in(16) <= buf_MED_DATA_IN(12);
- next_fifo_data_in(7 downto 0) <= (others => '0');
- next_fifo_data_in(15 downto 8) <= buf_next_fifo_data_in(7 downto 0);
+ next_fifo_data_in(7 downto 0) <= fifo_data_in(7 downto 0);
+ next_fifo_data_in(15 downto 8) <= fifo_data_in(7 downto 0);
next_packet_in_state <= packet_in_state;
if buf_MED_CARRIER_IN = '1' then
next_packet_in_state <= not packet_in_state;
- if packet_in_state ='0' then
- next_fifo_data_in(7 downto 0) <= buf_MED_data_in(7 downto 0);
- else
- next_next_fifo_data_in(7 downto 0) <= buf_MED_data_in(7 downto 0);
- end if;
+ next_fifo_data_in(7 downto 0) <= buf_MED_data_in(7 downto 0);
end if;
end process;
begin
if RESET = '1' then
fifo_write_enable <= '0';
- --data_valid <= '0';
fifo_data_in <= (others => '0');
- --buf_next_fifo_data_in <= (others => '0');
packet_in_state <= '0';
elsif rising_edge(CLK_TRANS) then
data_valid <= next_data_valid;
fifo_write_enable <= next_fifo_write_enable;
fifo_data_in <= next_fifo_data_in;
- buf_next_fifo_data_in <= next_next_fifo_data_in;
packet_in_state <= next_packet_in_state;
else
data_valid <= data_valid;
fifo_write_enable <= fifo_write_enable;
fifo_data_in <= fifo_data_in;
- buf_next_fifo_data_in <= buf_next_fifo_data_in;
packet_in_state <= packet_in_state;
end if;
end process;
-- Reading data from fifo, offering to INT
-----------------------------------------------------------------------
- process(fifo_empty_out, INT_READ_IN, buf_INT_DATAREADY_OUT, last_fifo_read_enable,
- fifo_data_out, buf_int_packet_nr_out, fifo_data_ready)
+ process(sbuff_next_read_out, fifo_empty_out, last_fifo_read_enable,
+ fifo_data_out, buf_int_packet_nr_out)
begin
- fifo_read_enable <= (not fifo_empty_out)
- and ((buf_int_dataready_out and int_read_in) or not buf_int_dataready_out);
- --set when fifo is not empty and available data is read or no data available
- next_int_dataready_out <= buf_int_dataready_out;
- next_int_data_out <= (others => '0');
- next_int_packet_nr_out <= buf_int_packet_nr_out;
- next_fifo_data_ready <= (not fifo_empty_out
- and ((buf_int_dataready_out and int_read_in) or not buf_int_dataready_out))
- or (fifo_data_ready and buf_int_dataready_out and not int_read_in);
- --data will be available when read_enable is set or when it was set before and
- --data is not read now
-
- if (buf_int_dataready_out = '1' and int_read_in = '1') then
- next_int_dataready_out <= '0';
- end if;
-
+ fifo_read_enable <= sbuff_next_read_out and not fifo_empty_out;
+
+
if last_fifo_read_enable = '1' and fifo_data_out(16) = '1' then
next_int_packet_nr_out <= "00";
elsif last_fifo_read_enable = '1' then
next_int_packet_nr_out <= buf_int_packet_nr_out + 1;
else
next_int_packet_nr_out <= buf_int_packet_nr_out;
- end if;
-
-
- if fifo_data_ready = '1' then
- next_int_data_out <= fifo_data_out(15 downto 0);
+ end if;
+
+ if last_fifo_read_enable = '1' then
+ --next_int_data_out <= fifo_data_out(15 downto 0);
next_int_dataready_out <= '1';
if fifo_data_out(17) = '0' then
next_int_error_out <= ERROR_FATAL;
- else
+ else
next_int_error_out <= ERROR_OK;
end if;
if fifo_data_out(16) = '1' and buf_int_packet_nr_out /= "11" then
next_int_error_out <= ERROR_ENCOD;
end if;
end if;
-
end process;
-
+
process(CLK,RESET)
begin
if RESET = '1' then
last_fifo_read_enable <= '0';
- buf_int_data_out <= (others => '0');
- buf_int_dataready_out <= '0';
buf_int_error_out <= ERROR_NC;
buf_int_packet_nr_out <= "00";
- fifo_data_ready <= '0';
elsif rising_edge(CLK) then
last_fifo_read_enable <= fifo_read_enable;
- buf_int_data_out <= next_int_data_out;
- buf_int_dataready_out <= next_int_dataready_out;
buf_int_error_out <= next_int_error_out;
buf_int_packet_nr_out <= next_int_packet_nr_out;
- fifo_data_ready <= next_fifo_data_ready;
else
last_fifo_read_enable <= last_fifo_read_enable;
- buf_int_data_out <= buf_int_data_out;
- buf_int_dataready_out <= buf_int_dataready_out;
buf_int_error_out <= buf_int_error_out;
buf_int_packet_nr_out <= buf_int_packet_nr_out;
- fifo_data_ready <= fifo_data_ready;
end if;
end process;
-
-INT_DATA_OUT <= buf_int_data_out;
+buf_comb_data_in(15 downto 0) <= fifo_data_out(15 downto 0);
+buf_comb_data_in(17 downto 16) <= next_int_packet_nr_out;
+
+ SBUF_fifo_to_int : trb_net_sbuf
+ generic map(DATA_WIDTH => 18, VERSION => 0)
+ port map (
+ CLK => CLK,
+ RESET => RESET,
+ CLK_EN => CLK_EN,
+ COMB_DATAREADY_IN => last_fifo_read_enable,
+ COMB_next_READ_OUT => sbuff_next_read_out,
+ COMB_READ_IN => '1',
+ COMB_DATA_IN => buf_comb_data_in,
+ -- Port to synchronous output.
+ SYN_DATAREADY_OUT => buf_INT_DATAREADY_OUT,
+ SYN_DATA_OUT => buf_INT_DATA_OUT,
+ SYN_READ_IN => INT_READ_IN,
+ -- Status and control port
+ STAT_BUFFER => sbuff_status
+ );
+
+
+INT_DATA_OUT <= buf_int_data_out(15 downto 0);
INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT;
-INT_PACKET_NR_OUT <= buf_int_packet_nr_out;
+INT_PACKET_NR_OUT <= buf_int_data_out(17 downto 16);
+INT_ERROR_OUT <= buf_int_error_out;
-----------------------------------------------------------------------
end process;
process(send_dataready, send_data_byte1, send_data_byte2,
- send_dataready1, send_data_byte1_parity, send_data_byte2_parity, send_packet1)
+ send_dataready1, send_data_byte1_parity, send_data_byte2_parity,
+ send_packet1, buf_INT_DATAREADY_OUT, INT_READ_IN, data_valid)
begin
- next_MED_DATA_OUT(11 downto 8) <= (others => '0');
+ next_MED_DATA_OUT(9 downto 8) <= (others => '0');
next_MED_DATA_OUT(12) <= send_packet1;
- next_MED_DATA_OUT(7 downto 0) <= (others => '0');
- next_MED_CARRIER_OUT <= '0';
- next_MED_PARITY_OUT <= '0';
- next_send_dataready1 <= '0';
- if send_dataready = '1' and send_dataready1 = '0' then
- next_MED_DATA_OUT(7 downto 0) <= send_data_byte1;
- next_MED_PARITY_OUT <= send_data_byte1_parity;
- next_MED_CARRIER_OUT <= '1';
- next_send_dataready1 <= '1';
+ next_MED_DATA_OUT(11) <= buf_INT_DATAREADY_OUT and INT_READ_IN;
+ next_MED_DATA_OUT(10) <= data_valid;
- elsif send_dataready1 = '1' then
+
+ if send_dataready1 = '1' then
next_MED_DATA_OUT(7 downto 0) <= send_data_byte2;
next_MED_PARITY_OUT <= send_data_byte2_parity;
next_MED_CARRIER_OUT <= '1';
+ next_send_dataready1 <= '0';
+ elsif send_dataready = '1' then
+ next_MED_DATA_OUT(7 downto 0) <= send_data_byte1;
+ next_MED_PARITY_OUT <= send_data_byte1_parity;
+ next_MED_CARRIER_OUT <= '1';
+ next_send_dataready1 <= '1';
+ else
+ next_MED_DATA_OUT(7 downto 0) <= (others => '0');
+ next_MED_CARRIER_OUT <= '0';
+ next_MED_PARITY_OUT <= '0';
+ next_send_dataready1 <= '0';
end if;
end process;
buf_MED_CARRIER_OUT <= '0';
buf_MED_PARITY_OUT <= '0';
send_dataready1 <= '0';
- elsif rising_edge(CLK_LVDS) then
+ elsif falling_edge(CLK_LVDS) then
buf_MED_DATA_OUT <= next_MED_DATA_OUT;
buf_MED_CARRIER_OUT <= next_MED_CARRIER_OUT;
buf_MED_PARITY_OUT <= next_MED_PARITY_OUT;
MED_PARITY_OUT <= buf_MED_PARITY_OUT;
MED_CARRIER_OUT <= buf_MED_CARRIER_OUT;
-MED_TRANSMISSION_CLK_OUT <= not CLK_LVDS;
-MED_DATA_OUT <= buf_MED_DATA_OUT;
+MED_TRANSMISSION_CLK_OUT <= CLK_LVDS;
+MED_DATA_OUT(7 downto 0) <= buf_MED_DATA_OUT(7 downto 0);
+
+MED_DATA_OUT(12 downto 8) <= buf_MED_DATA_OUT(12 downto 8);
+--MED_DATA_OUT(12) <= buf_MED_DATA_OUT(12);
+--MED_DATA_OUT(9 downto 8) <= buf_int_packet_nr_out;
+--MED_DATA_OUT(11 downto 10) <= CONV_PACKET_NR_OUT;
+--MED_DATA_OUT(9) <= CLK_TRANS;
+--MED_DATA_OUT(8) <= buf_MED_TRANSMISSION_CLK_IN;
end architecture;
jspc29 / trbnet.git / commitdiff