More information about CTS ports

diff --git a/daqnet.kilepr b/daqnet.kilepr
index cdf552a4fac7288bbb1daf5f3be28542c4e6f566..6b9b3e938115fb6ac85785a904ffd6ac046d59cb 100755 (executable)
--- a/daqnet.kilepr
+++ b/daqnet.kilepr
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diff --git a/trb3/CtsHowtos.tex b/trb3/CtsHowtos.tex
index 946f800142b0348afd17141883654eb37375d7d1..7386cc657bbf784ea9f7cac39721a08b1a3cf0a3 100644 (file)
--- a/trb3/CtsHowtos.tex
+++ b/trb3/CtsHowtos.tex
@@ -38,18 +38,21 @@ for the ETM.
 \begin{table}
   \begin{center}
     \begin{tabularx}{\textwidth}{lllllX} \hline
-      Signal      & FPGA Loc & RJ45 Socket      & RJ45 Pin & RJ45 Cable\\
+      Signal      & FPGA Loc & Conn.      & Wire  & Usage\\
       \hline\hline    
-      CLK\_EXT(3) & U9 (P)   & EXTERNAL\_CLOCK1 & 4        & blue      \\
-                  & U8 (N)   & EXTERNAL\_CLOCK1 & 5        & white/blue\\
-      CLK\_EXT(4) & Y34 (P)  & EXTERNAL\_CLOCK1 & 7        & white/brown\\
-                  & Y33 (N)  & EXTERNAL\_CLOCK1 & 8        & brown\\ \hline  
-      TRIGGER\_EXT(2) & W2 (P) & TRIGGER\_INP1   & 3        & white/green\\
-                      & W1 (N) & TRIGGER\_INP1   & 6        & green\\    
-      TRIGGER\_EXT(3) & W4 (P) & TRIGGER\_INP1   & 7        & white/brown\\
-                      & W3 (N) & TRIGGER\_INP1   & 8        & brown\\    
-      TRIGGER\_OUT2   & W8 (P) & TRIGGER\_INP1   & 4        & blue\\
-                      & W9 (N) & TRIGGER\_INP1   & 5        & white/blue\\
+      CLK\_EXT(3) & U9 (P)   & Clock & 4  blue      & TriggerIn0 / MbsIn / A2Data\\
+                  & U8 (N)   & Clock & 5  wh/blue & \\
+      CLK\_EXT(4) & Y34 (P)  & Clock & 7  wh/brown & TriggerIn1 / A2Clk\\
+                  & Y33 (N)  & Clock & 8  brown & \\
+      \hline
+      TRIGGER\_IN     & -- & Trigger   & 1 wh/orange & Global Trigger (on non-CTS)\\
+                      & -- & Trigger   & 2 orange & \\
+      TRIGGER\_EXT(2) & W2 (P) & Trigger   & 3 wh/green & TriggerIn2\\
+                      & W1 (N) & Trigger   & 6 green & \\
+      TRIGGER\_EXT(3) & W4 (P) & Trigger   & 7 wh/brown & TriggerIn3\\
+                      & W3 (N) & Trigger   & 8 brown & \\
+      TRIGGER\_OUT2   & W8 (P) & Trigger   & 4 blue & Trigger Output\\
+                      & W9 (N) & Trigger   & 5 wh/blue & \\
       \hline
     \end{tabularx}
     \caption[RJ45 Connections of the Central FPGA]{All signals are