CLK : in std_logic;
CLK_SYS : in std_logic;
RESET : in std_logic;
-
+
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(15 downto 0);
-
+
ACTIVE : out std_logic;
-
+
BUS_RX : in CTRLBUS_RX;
BUS_TX : out CTRLBUS_TX
);
signal data_i : std_logic_vector(15 downto 0);
signal add_reg : std_logic_vector(31 downto 0);
-
+
type state_t is (START, LISTEN, STEP, CALC, SET0, SET1, SET2, SET3, ENDWAIT);
type state_arrt is array (0 to 7) of state_t;
-
+
type unsigned_arr is array(0 to 7) of unsigned(6 downto 0);
signal sample_good, sample_bad : unsigned_arr := (others => (others => '0'));
signal first_good, first_bad : unsigned_arr := (others => (others => '1'));
signal last_good, last_bad, posi : unsigned_arr := (others => (others => '0'));
signal active_i : std_logic_vector(7 downto 0);
-
+
begin
reset_i <= RESET when rising_edge(CLK);
THE_IN : entity work.mimosis_inp
port map (
- clkin=>CLK,
- reset=>reset_i,
- sclk=>clk_rx,
- data_cflag(7 downto 0)=>s_cflag,
- data_direction(7 downto 0)=>(others => '0'),
- data_loadn(7 downto 0)=>s_loadn,
- data_move(7 downto 0)=>s_move,
- datain(7 downto 0)=>DIN,
+ clkin=>CLK,
+ reset=>reset_i,
+ sclk=>clk_rx,
+ data_cflag(7 downto 0)=>s_cflag,
+ data_direction(7 downto 0)=>(others => '0'),
+ data_loadn(7 downto 0)=>s_loadn,
+ data_move(7 downto 0)=>s_move,
+ datain(7 downto 0)=>DIN,
q(15 downto 0)=>data_i
);
-
+
DOUT <= data_i;
ACTIVE <= and(active_i);
-gen_finders : for i in 0 to 7 generate
+gen_finders : for i in 0 to 7 generate
signal timer : unsigned(14 downto 0);
signal state : state_t;
signal count : unsigned(11 downto 0);
signal lastsample : std_logic;
signal train : unsigned(3 downto 0);
signal last : std_logic_vector(1 downto 0);
-
-begin
+
+begin
PROC_FIND : process begin
wait until rising_edge(CLK);
s_loadn(i) <= not add_reg(i+16);
count <= 0;
s_move(i) <= '0';
state <= LISTEN;
-
+
when LISTEN =>
if timer(timer'left) = '1' then
state <= STEP;
if last_bad(i) < pos and lastsample = '0' then
last_bad(i) <= pos;
end if;
-
+
else
lastsample <= '0';
- sample_bad(i) <= sample_bad(i) + 1;
+ sample_bad(i) <= sample_bad(i) + 1;
if first_bad(i) > pos then
first_bad(i) <= pos;
end if;
if last_good(i) < pos and lastsample = '1' then
last_good(i) <= pos;
- end if;
+ end if;
end if;
- else
+ else
timer <= timer + 1;
end if;
-
+
last <= data_i(i*2+1 downto i*2);
-
- if (data_i(i*2+1 downto i*2) = "01" or data_i(i*2+1 downto i*2) = "10") and
+
+ if (data_i(i*2+1 downto i*2) = "01" or data_i(i*2+1 downto i*2) = "10") and
data_i(i*2+1 downto i*2) = last then
train <= train + 1;
else
train <= x"0";
end if;
-
+
if train = x"3" then
count <= count + 1;
end if;
-
-
+
+
when STEP =>
if s_cflag(i) = '0' then
s_move(i) <= '1';
state <= START;
else
state <= CALC;
- s_loadn(i) <= '0';
- end if;
-
+ s_loadn(i) <= '0';
+ end if;
+
when CALC =>
if first_good(i) = "0000000" then
pos <= (('0' & last_bad(i)) + ('0' & first_bad(i)))(7 downto 1) + "1000000";
- else
+ else
pos <= (('0' & last_good(i)) + ('0' & first_good(i)))(7 downto 1);
- end if;
+ end if;
state <= SET0;
-
+
when SET0 =>
posi(i) <= pos;
state <= SET1;
-
+
when SET1 =>
state <= SET2;
s_move(i) <= '1';
-
+
when SET2 =>
s_move(i) <= '0';
if pos = 0 then
state <= ENDWAIT;
- else
+ else
state <= SET3;
pos <= pos - 1;
- end if;
+ end if;
when SET3 =>
state <= SET1;
-
+
when ENDWAIT =>
active_i(i) <= '1';
state <= ENDWAIT;
-
+
end case;
-
+
if reset_i = '1' or add_reg(0) = '1' then
state <= START;
pos <= 0;
sample_bad(i) <= 0;
last_good(i) <= 0;
last_bad(i) <= 0;
- first_good(i) <= (others => '1');
- first_bad(i) <= (others => '1');
+ first_good(i) <= (others => '1');
+ first_bad(i) <= (others => '1');
end if;
end process;
-end generate;
+end generate;
-PROC_REGS : process
+PROC_REGS : process
variable addr : integer range 0 to 7;
begin
wait until rising_edge(CLK_SYS);
else
BUS_TX.ack <= '0';
BUS_TX.unknown <= '1';
-
+
end if;
end if;
end process;
CLK : in std_logic;
CLK_SYS : in std_logic;
RESET : in std_logic;
-
+
DIN : in std_logic_vector(15 downto 0);
DOUT : out std_logic_vector(31 downto 0);
VALID : out std_logic;
-
+
ACTIVE : in std_logic;
-
+
BUS_RX : in CTRLBUS_RX;
BUS_TX : out CTRLBUS_TX
);
architecture arch of WordAlign is
constant IDLE_WORD : std_logic_vector(15 downto 0) := x"FCAA";
constant HDR_WORD : std_logic_vector(15 downto 0) := x"FE00";
-
-
+
+
signal reset_i : std_logic;
type word_arr is array(0 to 7) of std_logic_vector(23 downto 0);
signal shift_reg, words, data_reg : word_arr;
-
+
signal doubleword : std_logic_vector(31 downto 0);
signal doubleword_valid : std_logic;
-
+
signal control_reg : std_logic_vector(31 downto 0);
alias CONF_channel_enable : std_logic_vector is control_reg(7 downto 0);
alias CONF_fixalign : std_logic is control_reg(8);
alias CONF_writeall : std_logic is control_reg(9);
alias CONF_ignoreactive : std_logic is control_reg(10);
-
+
signal bittime : integer range 0 to 31 := 0;
signal word_update : std_logic_vector(7 downto 0);
signal found_idle : std_logic_vector(7 downto 0) := (others => '0');
signal last_word_update, next_last_word_update : std_logic;
signal copycnt : integer range 0 to 4;
-
+
begin
bittime <= bittime + 1 when rising_edge(CLK);
bitcnt <= bitcnt + 1;
word_update(i) <= '0';
shift_reg <= shift_reg(14 downto 0) & DIN(i*2) & DIN(i*2+1);
-
+
if CONF_fixalign = '0' and (ACTIVE = '1' or CONF_ignoreactive = '1') then
if shift_reg(15 downto 0) = IDLE_WORD then
oddeven <= '1';
found_idle(i) <= '1';
end if;
end if;
-
+
if bitcnt = 0 then
word_update(i) <= '1';
if oddeven = '1' then
words(i) <= std_logic_vector(to_unsigned(bittime,4)) & "000" & oddeven & shift_reg(16 downto 1);
end if;
end if;
-
+
end process;
end generate;
elsif copycnt = 3 then
doubleword <= data_reg(6)(15 downto 0) & data_reg(7)(15 downto 0);
doubleword_valid <= '1';
- elsif copycnt = 4 then
+ elsif copycnt = 4 then
copycnt <= copycnt;
end if;
end process;
end process;
-PROC_REGS : process
+PROC_REGS : process
variable addr : integer range 0 to 7;
begin
wait until rising_edge(CLK_SYS);
else
BUS_TX.ack <= '0';
BUS_TX.unknown <= '1';
-
+
end if;
end if;
end process;
CLK_200 : in std_logic;\r
CLK_125 : in std_logic;\r
CLK_EXT : in std_logic;\r
- \r
+\r
TRIG_IN_BACKPL : in std_logic; --Reference Time\r
TRIG_IN_RJ45 : in std_logic; --Reference Time\r
IN_SELECT_EXT_CLOCK : in std_logic;\r
\r
SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3\r
BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1\r
- \r
+\r
SFP_TX_DIS : out std_logic;\r
SFP_LOS : in std_logic;\r
SFP_MOD_0 : in std_logic;\r
- \r
+\r
--AddOn\r
-- FE_GPIO : inout std_logic_vector(11 downto 0);\r
-- FE_CLK : out std_logic_vector( 2 downto 1);\r
LED_ADDON_RJ : out std_logic_vector(1 downto 0);\r
SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0);\r
SFP_ADDON_LOS : in std_logic_vector(1 downto 0);\r
- \r
+\r
RJ : inout std_logic_vector(3 downto 0);\r
H1 : inout std_logic_vector(4 downto 0);\r
H2 : inout std_logic_vector(4 downto 0);\r
H5 : inout std_logic_vector(3 downto 0);\r
H6 : inout std_logic_vector(4 downto 0);\r
H7 : inout std_logic_vector(4 downto 0);\r
- \r
+\r
PIN : out std_logic_vector(8 downto 1);\r
- \r
+\r
MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic;\r
- \r
+\r
--ADC\r
ADC_SCLK : out std_logic;\r
ADC_NCS : out std_logic;\r
LED_RJ_GREEN : out std_logic_vector(1 downto 0);\r
LED_RJ_RED : out std_logic_vector(1 downto 0);\r
LED_EXT_CLOCK : out std_logic;\r
- \r
+\r
--Other Connectors\r
TEST : inout std_logic_vector(14 downto 1); --on v1 only\r
--COMMON_SDA, COMMON_SCL : inout std_logic\r
signal reset_i : std_logic;\r
signal clear_i : std_logic;\r
signal trigger_in_i : std_logic;\r
- \r
- \r
+\r
+\r
attribute syn_keep of GSR_N : signal is true;\r
- attribute syn_preserve of GSR_N : signal is true; \r
+ attribute syn_preserve of GSR_N : signal is true;\r
\r
signal debug_clock_reset : std_logic_vector(31 downto 0);\r
signal external_clock_lock : std_logic := '0';\r
signal int2med : int2med_array_t(0 to 0);\r
signal med_stat_debug : std_logic_vector (1*64-1 downto 0);\r
signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic;\r
- \r
+\r
\r
signal readout_rx : READOUT_RX;\r
signal readout_tx : readout_tx_array_t(0 to 0);\r
signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);\r
signal header_io_i : std_logic_vector(10 downto 1);\r
signal timer : TIMERS;\r
- signal add_reg : std_logic_vector(31 downto 0); \r
+ signal add_reg : std_logic_vector(31 downto 0);\r
alias led_off : std_logic is add_reg(0);\r
- \r
+\r
signal out_data : std_logic_vector(15 downto 0);\r
signal out_i : std_logic_vector( 7 downto 0);\r
signal inp_i : std_logic_vector( 7 downto 0);\r
signal gbe_status : std_logic_vector(15 downto 0);\r
- \r
- \r
+\r
+\r
signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0);\r
signal i2c_reg_2 : std_logic_vector(31 downto 0);\r
signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0);\r
--signal fwd_sop : std_logic;\r
--signal fwd_eop : std_logic;\r
--signal fwd_ready : std_logic;\r
- --signal fwd_full : std_logic; \r
+ --signal fwd_full : std_logic;\r
--signal fwd_length : std_logic_vector(15 downto 0);\r
- --signal fwd_do_send : std_logic; \r
- \r
+ --signal fwd_do_send : std_logic;\r
+\r
begin\r
\r
\r
\r
gen_sfp_con : if SERDES_NUM = 1 generate\r
sfp_los_i <= SFP_LOS;\r
- sfp_prsnt_i <= SFP_MOD_0; \r
+ sfp_prsnt_i <= SFP_MOD_0;\r
SFP_TX_DIS <= sfp_txdis_i;\r
- end generate; \r
+ end generate;\r
gen_bpl_con : if SERDES_NUM = 0 generate\r
sfp_los_i <= BACK_GPIO(1);\r
- sfp_prsnt_i <= BACK_GPIO(1); \r
+ sfp_prsnt_i <= BACK_GPIO(1);\r
BACK_GPIO(0) <= sfp_txdis_i;\r
- end generate; \r
- \r
+ end generate;\r
+\r
\r
---------------------------------------------------------------------------\r
-- Endpoint\r
BUS_RX(3) => busmimosis_rx,\r
BUS_RX(4) => busi2c_rx,\r
--BUS_RX(5) => busgbeip_rx,\r
- --BUS_RX(6) => busgbereg_rx, \r
+ --BUS_RX(6) => busgbereg_rx,\r
--BUS_RX(7) => busfwd_rx,\r
BUS_TX(0) => bustools_tx,\r
BUS_TX(1) => bussci_tx,\r
ADC_CMD_2 => x"1d5cb",\r
ADC_CMD_3 => x"1e3cb",\r
ADC_CMD_4 => x"2f5cb",\r
- ADC_CMD_T => x"1F393" \r
+ ADC_CMD_T => x"1F393"\r
)\r
port map(\r
CLK => clk_sys,\r
ADC_MOSI => ADC_MOSI,\r
ADC_MISO => ADC_MISO,\r
ADC_CLK => ADC_SCLK,\r
- --Trigger & Monitor \r
+ --Trigger & Monitor\r
MONITOR_INPUTS => (others => '0'),\r
TRIG_GEN_INPUTS => (others => '0'),\r
TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2),\r
\r
--COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z';\r
--COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z';\r
- \r
+\r
FLASH_HOLD <= '1';\r
FLASH_WP <= '1';\r
- \r
+\r
---------------------------------------------------------------------------\r
-- I2C\r
---------------------------------------------------------------------------\r
-THE_I2C : entity work.i2c_slim2 \r
+THE_I2C : entity work.i2c_slim2\r
port map(\r
CLOCK => clk_40,\r
RESET => reset_i,\r
busi2c_tx.nack <= '0';\r
busi2c_tx.data <= (others => '0');\r
i2c_go_100 <= '0';\r
- \r
+\r
if busi2c_rx.write = '1' then\r
busi2c_tx.ack <= '1';\r
if busi2c_rx.addr(3 downto 0) = x"0" then\r
else\r
busi2c_tx.ack <= '0';\r
busi2c_tx.unknown <= '1';\r
- \r
+\r
end if;\r
end if;\r
end process;\r
PULSE_B_OUT => i2c_go\r
);\r
\r
- THE_MIMOSIS_SIGNAL_SYNC : signal_sync \r
+ THE_MIMOSIS_SIGNAL_SYNC : signal_sync\r
generic map(\r
WIDTH => 32,\r
DEPTH => 2\r
D_IN => i2c_reg_5,\r
D_OUT => i2c_reg_5_40\r
);\r
- \r
+\r
\r
\r
---------------------------------------------------------------------------\r
LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used\r
LED_RJ_RED(0) <= '1' when SERDES_NUM = 1 or led_off = '1' else '0'; --on if backplane is used (next to SFP)\r
LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used\r
- \r
+\r
TEST(13 downto 1) <= (others => '0');\r
TEST(14) <= flash_ncs_i; --for v1 boards\r
\r
- FLASH_NCS <= flash_ncs_i; \r
+ FLASH_NCS <= flash_ncs_i;\r
\r
LED_ADDON_RJ <= "00";\r
LED_ADDON_SFP_GREEN(0) <= (gbe_status(0) and gbe_status(1) and gbe_status(2));\r
LED_ADDON_SFP_GREEN(1) <= '0';\r
LED_ADDON_SFP_ORANGE(0) <= (gbe_status(3) or gbe_status(4));\r
LED_ADDON_SFP_ORANGE(1) <= '0';\r
- \r
+\r
-----------------------------------------------------------------------------\r
---- GbE\r
-----------------------------------------------------------------------------\r
--RESET => reset_i,\r
--GSR_N => GSR_N,\r
---- Trigger\r
- --TRIGGER_IN => '0', \r
+ --TRIGGER_IN => '0',\r
---- SFP\r
--SD_PRSNT_N_IN(0) => SFP_MOD_0,\r
--SD_LOS_IN(0) => SFP_LOS,\r
--CTS_INFORMATION_IN => (others => '0'),\r
--CTS_READOUT_TYPE_IN => (others => '0'),\r
--CTS_START_READOUT_IN => '0',\r
- --CTS_DATA_OUT => open, \r
- --CTS_DATAREADY_OUT => open, \r
+ --CTS_DATA_OUT => open,\r
+ --CTS_DATAREADY_OUT => open,\r
--CTS_READOUT_FINISHED_OUT => open,\r
- --CTS_READ_IN => '1', \r
- --CTS_LENGTH_OUT => open, \r
+ --CTS_READ_IN => '1',\r
+ --CTS_LENGTH_OUT => open,\r
--CTS_ERROR_PATTERN_OUT => open,\r
- ---- data channel \r
+ ---- data channel\r
---- only for LINK_HAS_READOUT\r
--FEE_DATA_IN => (others => '0'),\r
--FEE_DATAREADY_IN => '0',\r
--MY_TRBNET_ADDRESS_IN => timer.network_address,\r
--ISSUE_REBOOT_OUT => open, --BUG: needs to be connected\r
---- slow control by GbE\r
- --GSC_CLK_IN => open, \r
- --GSC_INIT_DATAREADY_OUT => open, \r
- --GSC_INIT_DATA_OUT => open, \r
- --GSC_INIT_PACKET_NUM_OUT => open, \r
- --GSC_INIT_READ_IN => '1', \r
- --GSC_REPLY_DATAREADY_IN => '0', \r
- --GSC_REPLY_DATA_IN => (others => '0'), \r
- --GSC_REPLY_PACKET_NUM_IN => (others => '0'), \r
- --GSC_REPLY_READ_OUT => open, \r
+ --GSC_CLK_IN => open,\r
+ --GSC_INIT_DATAREADY_OUT => open,\r
+ --GSC_INIT_DATA_OUT => open,\r
+ --GSC_INIT_PACKET_NUM_OUT => open,\r
+ --GSC_INIT_READ_IN => '1',\r
+ --GSC_REPLY_DATAREADY_IN => '0',\r
+ --GSC_REPLY_DATA_IN => (others => '0'),\r
+ --GSC_REPLY_PACKET_NUM_IN => (others => '0'),\r
+ --GSC_REPLY_READ_OUT => open,\r
--GSC_BUSY_IN => '0',\r
---- readout\r
--BUS_IP_RX => busgbeip_rx, -- registers inside GbE\r
--STATUS_OUT => open,\r
--DEBUG_OUT => open\r
--);\r
- \r
+\r
\r
\r
-----------------------------------------------------------------------------\r
---- Test registers\r
------------------------------------------------------------------------------ \r
+-----------------------------------------------------------------------------\r
--THE_REGS : process begin\r
--wait until rising_edge(clk_sys);\r
--busfwd_tx.ack <= '0';\r
--busfwd_tx.nack <= '0';\r
--busfwd_tx.unknown <= '0';\r
- \r
+\r
--if busfwd_rx.write = '1' then\r
--busfwd_tx.ack <= '1';\r
--case busfwd_rx.addr(7 downto 0) is\r
--when x"04" => busfwd_tx.data <= x"0000" & fwd_length;\r
--when x"05" => busfwd_tx.data <= x"0000000" & fwd_full & fwd_ready & "0" & fwd_do_send;\r
--when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1';\r
- --end case; \r
+ --end case;\r
--end if;\r
--if reset_i = '1' then\r
--fwd_do_send <= '0';\r
--end if;\r
---end process; \r
- \r
- \r
+--end process;\r
+\r
+\r
---------------------------------------------------------------------------\r
-- Output stage\r
---------------------------------------------------------------------------- \r
+---------------------------------------------------------------------------\r
THE_OUT : entity work.testout\r
port map(\r
clkout => open,\r
data_move => (others => '0'),\r
dout => out_i\r
);\r
- \r
- PROC_OUT : process \r
+\r
+ PROC_OUT : process\r
variable cnt : integer range 0 to 7;\r
begin\r
wait until rising_edge(clk_160);\r
cnt := cnt + 1;\r
- case cnt is \r
+ case cnt is\r
when 0 => out_data <= x"ffff";\r
when 1 => out_data <= x"ffff";\r
when 2 => out_data <= x"ffff";\r
when 6 => out_data <= x"5555";\r
when 7 => out_data <= x"5555";\r
end case;\r
- end process; \r
+ end process;\r
\r
H3(3 downto 0) <= out_i(3 downto 0);\r
H4(3 downto 0) <= out_i(7 downto 4);\r
\r
- \r
+\r
---------------------------------------------------------------------------\r
-- Input stage\r
---------------------------------------------------------------------------\r
CLK => clk_160,\r
CLK_SYS => clk_sys,\r
RESET => reset_i,\r
- \r
+\r
INPUT => inp_i,\r
- \r
+\r
BUSRDO_RX => readout_rx,\r
BUSRDO_TX => readout_tx(0),\r
- \r
+\r
BUS_RX => busmimosis_rx,\r
BUS_TX => busmimosis_tx\r
);\r
-------------------------------------------------------------------------------\r
-- readout_tx(0).data_finished <= '1';\r
-- readout_tx(0).data_write <= '0';\r
--- readout_tx(0).busy_release <= '1'; \r
- \r
-SFP_ADDON_TX_DIS <= (others => '0'); \r
+-- readout_tx(0).busy_release <= '1';\r
+\r
+SFP_ADDON_TX_DIS <= (others => '0');\r
end architecture;\r
\r
\r
--- /dev/null
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+
+entity InputStage is
+ port (
+ CLK : in std_logic;
+ CLK_SYS : in std_logic;
+ RESET : in std_logic;
+
+ DIN : in std_logic_vector(7 downto 0);
+ DOUT : out std_logic_vector(15 downto 0);
+
+ ACTIVE : out std_logic;
+
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX
+ );
+end entity;
+
+
+architecture arch of InputStage is
+
+ signal clk_rx : std_logic;
+ signal reset_i : std_logic;
+ signal s_cflag, s_loadn, s_move : std_logic_vector(7 downto 0) := (others => '0');
+
+ signal data_i : std_logic_vector(15 downto 0);
+ signal add_reg : std_logic_vector(31 downto 0);
+
+ type state_t is (START, LISTEN, STEP, CALC, SET0, SET1, SET2, SET3, ENDWAIT);
+ type state_arrt is array (0 to 7) of state_t;
+
+ type unsigned_arr is array(0 to 7) of unsigned(6 downto 0);
+ signal sample_good, sample_bad : unsigned_arr := (others => (others => '0'));
+ signal first_good, first_bad : unsigned_arr := (others => (others => '1'));
+ signal last_good, last_bad, posi : unsigned_arr := (others => (others => '0'));
+ signal active_i : std_logic_vector(7 downto 0);
+
+begin
+
+reset_i <= RESET when rising_edge(CLK);
+
+THE_IN : entity work.mimosis_inp
+ port map (
+ clkin=>CLK,
+ reset=>reset_i,
+ sclk=>clk_rx,
+ data_cflag(7 downto 0)=>s_cflag,
+ data_direction(7 downto 0)=>(others => '0'),
+ data_loadn(7 downto 0)=>s_loadn,
+ data_move(7 downto 0)=>s_move,
+ datain(7 downto 0)=>DIN,
+ q(15 downto 0)=>data_i
+ );
+
+
+DOUT <= data_i;
+ACTIVE <= and(active_i);
+
+gen_finders : for i in 0 to 7 generate
+ signal timer : unsigned(14 downto 0);
+ signal state : state_t;
+ signal count : unsigned(11 downto 0);
+ signal pos : unsigned(6 downto 0);
+ signal lastsample : std_logic;
+ signal train : unsigned(3 downto 0);
+ signal last : std_logic_vector(1 downto 0);
+
+begin
+ PROC_FIND : process begin
+ wait until rising_edge(CLK);
+ s_loadn(i) <= not add_reg(i+16);
+ active_i(i) <= '0';
+
+ case state is
+ when START =>
+ timer <= 0;
+ count <= 0;
+ s_move(i) <= '0';
+ state <= LISTEN;
+
+ when LISTEN =>
+ if timer(timer'left) = '1' then
+ state <= STEP;
+ if count >= 2047 and count <= 2049 then
+ sample_good(i) <= sample_good(i) + 1;
+ lastsample <= '1';
+ if first_good(i) > pos then
+ first_good(i) <= pos;
+ end if;
+ if last_bad(i) < pos and lastsample = '0' then
+ last_bad(i) <= pos;
+ end if;
+
+ else
+ lastsample <= '0';
+ sample_bad(i) <= sample_bad(i) + 1;
+ if first_bad(i) > pos then
+ first_bad(i) <= pos;
+ end if;
+ if last_good(i) < pos and lastsample = '1' then
+ last_good(i) <= pos;
+ end if;
+ end if;
+ else
+ timer <= timer + 1;
+ end if;
+
+ last <= data_i(i*2+1 downto i*2);
+
+ if (data_i(i*2+1 downto i*2) = "01" or data_i(i*2+1 downto i*2) = "10") and
+ data_i(i*2+1 downto i*2) = last then
+ train <= train + 1;
+ else
+ train <= x"0";
+ end if;
+
+ if train = x"3" then
+ count <= count + 1;
+ end if;
+
+
+ when STEP =>
+ if s_cflag(i) = '0' then
+ s_move(i) <= '1';
+ pos <= pos + 1;
+ state <= START;
+ else
+ state <= CALC;
+ s_loadn(i) <= '0';
+ end if;
+
+ when CALC =>
+ if first_good(i) = "0000000" then
+ pos <= (('0' & last_bad(i)) + ('0' & first_bad(i)))(7 downto 1) + "1000000";
+ else
+ pos <= (('0' & last_good(i)) + ('0' & first_good(i)))(7 downto 1);
+ end if;
+ state <= SET0;
+
+ when SET0 =>
+ posi(i) <= pos;
+ state <= SET1;
+
+ when SET1 =>
+ state <= SET2;
+ s_move(i) <= '1';
+
+ when SET2 =>
+ s_move(i) <= '0';
+ if pos = 0 then
+ state <= ENDWAIT;
+ else
+ state <= SET3;
+ pos <= pos - 1;
+ end if;
+
+ when SET3 =>
+ state <= SET1;
+
+ when ENDWAIT =>
+ active_i(i) <= '1';
+ state <= ENDWAIT;
+
+ end case;
+
+ if reset_i = '1' or add_reg(0) = '1' then
+ state <= START;
+ pos <= 0;
+ s_loadn(i) <= '0';
+ active_i(i) <= '0';
+ sample_good(i) <= 0;
+ sample_bad(i) <= 0;
+ last_good(i) <= 0;
+ last_bad(i) <= 0;
+ first_good(i) <= (others => '1');
+ first_bad(i) <= (others => '1');
+ end if;
+ end process;
+end generate;
+
+PROC_REGS : process
+ variable addr : integer range 0 to 7;
+begin
+ wait until rising_edge(CLK_SYS);
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '0';
+ BUS_TX.nack <= '0';
+ BUS_TX.data <= (others => '0');
+ addr := to_integer(unsigned(BUS_RX.addr(2 downto 0)));
+ if BUS_RX.write = '1' then
+ if BUS_RX.addr(15 downto 0) = x"0010" then
+ BUS_TX.ack <= '1';
+ add_reg <= BUS_RX.data;
+ else
+ BUS_TX.unknown <= '1';
+ end if;
+ elsif BUS_RX.read = '1' then
+ BUS_TX.ack <= '1';
+ if BUS_RX.addr(15 downto 0) = x"0010" then
+ BUS_TX.data <= add_reg;
+ elsif BUS_RX.addr(15 downto 4) = x"000" then
+ if BUS_RX.addr(3) = '0' then
+ BUS_TX.data(6 downto 0) <= std_logic_vector(sample_good(addr));
+ BUS_TX.data(14 downto 8) <= std_logic_vector(sample_bad(addr));
+ BUS_TX.data(16) <= s_cflag(addr);
+ BUS_TX.data(20) <= active_i(addr);
+ BUS_TX.data(30 downto 24)<= std_logic_vector(posi(addr));
+ else
+ BUS_TX.data(6 downto 0) <= std_logic_vector(first_good(addr));
+ BUS_TX.data(14 downto 8) <= std_logic_vector(last_good(addr));
+ BUS_TX.data(22 downto 16) <= std_logic_vector(first_bad(addr));
+ BUS_TX.data(30 downto 24) <= std_logic_vector(last_bad(addr));
+ end if;
+ else
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+
+ end if;
+ end if;
+end process;
+
+
+
+
+end architecture;
--- /dev/null
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+
+entity MimosisInput is
+ port (
+ CLK : in std_logic;
+ CLK_SYS : in std_logic;
+ RESET : in std_logic;
+
+ INPUT : in std_logic_vector(7 downto 0);
+
+ BUSRDO_RX : in READOUT_RX;
+ BUSRDO_TX : out READOUT_TX;
+
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX
+ );
+end entity;
+
+
+architecture arch of MimosisInput is
+ constant HDR_WORD : std_logic_vector(15 downto 0) := x"FE00";
+ constant WORD_LIMIT : integer := 8500;
+ signal input_active_i : std_logic;
+ signal data_i : std_logic_vector(15 downto 0);
+ signal inp_i : std_logic_vector(7 downto 0);
+ signal word_i : std_logic_vector(31 downto 0);
+ signal word_valid : std_logic;
+
+ signal businp_rx, busword_rx, busmimosis_rx : CTRLBUS_RX;
+ signal businp_tx, busword_tx, busmimosis_tx : CTRLBUS_TX;
+
+ signal ct_fifo_afull, ct_fifo_full, ct_fifo_empty : std_logic;
+ signal ct_fifo_read, ct_fifo_valid, ct_fifo_nextvalid : std_logic;
+ signal ct_fifo_data_out : std_logic_vector(31 downto 0);
+
+ signal buffer_empty, buffer_full : std_logic;
+ signal buffer_write, buffer_read : std_logic;
+ signal buffer_valid, buffer_nextvalid : std_logic;
+ signal buffer_din, buffer_dout : std_logic_vector(31 downto 0);
+ signal buffer_fill : std_logic_vector(13 downto 0);
+
+ type state_t is (IDLE,START_COPY, START_COPY2, COPY,FINISH,DONE);
+ signal state : state_t;
+ signal word_count : integer range 0 to 8191;
+
+ signal frame_number : std_logic_vector(31 downto 0);
+ signal frame_length : std_logic_vector(15 downto 0);
+ signal count_words : unsigned(15 downto 0);
+ signal count_header : unsigned(31 downto 0);
+ signal count_trailer : unsigned(31 downto 0);
+ signal count_fe : unsigned(31 downto 0);
+ signal count_ff : unsigned(31 downto 0);
+ signal count_oof : unsigned(31 downto 0);
+ signal pulse_stats : std_logic_vector(31 downto 0);
+ signal buffer_blocked : std_logic;
+ type frame_state_t is (IDLE,HDR1,HDR2,HDR3,WRITING);
+ signal frame_state : frame_state_t;
+
+
+begin
+
+ THE_IN : entity work.InputStage
+ port map (
+ CLK => CLK,
+ CLK_SYS => CLK_SYS,
+ RESET => RESET,
+
+ DIN => INPUT,
+ DOUT => data_i,
+ ACTIVE => input_active_i,
+
+ BUS_RX => businp_rx,
+ BUS_TX => businp_tx
+ );
+
+
+ THE_WORDS: entity work.WordAlign
+ port map(
+ CLK => CLK,
+ CLK_SYS => CLK_SYS,
+ RESET => RESET,
+
+ DIN => data_i,
+ DOUT => word_i,
+ VALID => word_valid,
+
+ ACTIVE => input_active_i,
+
+ BUS_RX => busword_rx,
+ BUS_TX => busword_tx
+ );
+
+
+----------------------------------------------------------------------
+-- Clock Domain Transfer
+----------------------------------------------------------------------
+THE_CT_FIFO : entity work.lattice_ecp5_fifo_36x16_dualport_oreg
+ port map(
+ Data(31 downto 0) => word_i(31 downto 0),
+ Data(35 downto 32) => "0000",
+ WrClock => CLK,
+ RdClock => CLK_SYS,
+ WrEn => word_valid,
+ RdEn => ct_fifo_read,
+ Reset => RESET,
+ RPReset => RESET,
+ Q(31 downto 0) => ct_fifo_data_out(31 downto 0),
+ Empty => ct_fifo_empty,
+ Full => ct_fifo_full,
+ AlmostFull => ct_fifo_afull
+ );
+
+ ct_fifo_read <= '1';
+ ct_fifo_nextvalid <= ct_fifo_read and not ct_fifo_empty when rising_edge(CLK_SYS);
+ ct_fifo_valid <= ct_fifo_nextvalid when rising_edge(CLK_SYS);
+
+----------------------------------------------------------------------
+-- Frame Copy
+----------------------------------------------------------------------
+
+PROC_FRAMES : process begin
+ wait until rising_edge(CLK_SYS);
+ buffer_write <= '0';
+ buffer_din <= ct_fifo_data_out;
+
+ if ct_fifo_valid = '1' then
+ count_words <= count_words + 1;
+ end if;
+
+ if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" then
+ count_fe <= count_fe + 1;
+ end if;
+
+ if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FF" then
+ count_ff <= count_ff + 1;
+ end if;
+
+ if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) < x"FC" and frame_state = IDLE then
+ count_oof <= count_oof + 1;
+ end if;
+
+ case frame_state is
+ when IDLE =>
+ count_words <= (others => '0');
+ if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" then
+ frame_state <= HDR1;
+ frame_number(15 downto 0) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16);
+ buffer_write <= '1' when buffer_full = '0' and state = IDLE else '0';
+ buffer_blocked <= '0' when buffer_full = '0' and state = IDLE else '1';
+ count_header <= count_header + 1;
+ end if;
+ when HDR1 =>
+ if ct_fifo_valid = '1' then
+ frame_state <= HDR2;
+ frame_number(31 downto 16) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16);
+ buffer_write <= not buffer_blocked;
+ end if;
+ when HDR2 =>
+ if ct_fifo_valid = '1' then
+ frame_state <= HDR3;
+ buffer_din(23 downto 16) <= pulse_stats(7 downto 0);
+ buffer_din(7 downto 0) <= pulse_stats(15 downto 8);
+ buffer_write <= not buffer_blocked;
+ end if;
+ when HDR3 =>
+ if ct_fifo_valid = '1' then
+ frame_state <= WRITING;
+ buffer_din(23 downto 16) <= pulse_stats(23 downto 16);
+ buffer_din(7 downto 0) <= pulse_stats(31 downto 24);
+ buffer_write <= not buffer_blocked;
+ end if;
+ when WRITING =>
+ buffer_write <= ct_fifo_valid and not buffer_blocked;
+ if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FF" then
+ frame_state <= IDLE;
+ frame_length <= std_logic_vector(count_words);
+ count_trailer <= count_trailer + 1;
+ end if;
+ if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" and count_words >= x"0004" then
+ frame_state <= HDR1;
+ count_header <= count_header + 1;
+ frame_number(15 downto 0) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16);
+ buffer_write <= not buffer_full;
+ buffer_blocked <= buffer_full;
+ end if;
+ end case;
+
+ end process;
+
+
+
+----------------------------------------------------------------------
+-- Main Fifo
+----------------------------------------------------------------------
+THE_FIFO : entity work.fifo_36x8k_oreg
+ port map(
+ Data(31 downto 0) => buffer_din,
+ Clock => CLK_SYS,
+ WrEn => buffer_write,
+ RdEn => buffer_read,
+ Reset => RESET,
+ AmFullThresh => "1000000000000",
+ Q(31 downto 0) => buffer_dout,
+ WCNT => buffer_fill,
+ Empty => buffer_empty,
+ Full => open,
+ AlmostFull => buffer_full
+ );
+
+ buffer_nextvalid <= buffer_read and not buffer_empty when rising_edge(CLK_SYS);
+ buffer_valid <= buffer_nextvalid when rising_edge(CLK_SYS);
+
+---------------------------------------------------------------------------
+-- Buffer Handler
+---------------------------------------------------------------------------
+PROC_RDO : process begin
+ wait until rising_edge(CLK_SYS);
+-- if state = IDLE and buffer_full = '1' then
+-- buffer_read <= '1';
+-- else
+ buffer_read <= '0';
+-- end if;
+
+
+ BUSRDO_TX.busy_release <= '0';
+ BUSRDO_TX.data_write <= '0';
+ BUSRDO_TX.data_finished <= '0';
+
+ case state is
+ when IDLE =>
+ if BUSRDO_RX.valid_timing_trg = '1' or BUSRDO_RX.valid_notiming_trg = '1' then
+ state <= START_COPY;
+ buffer_read <= '1';
+ word_count <= 0;
+ end if;
+ if BUSRDO_RX.invalid_trg = '1' then
+ state <= FINISH;
+ end if;
+
+ when START_COPY =>
+ state <= START_COPY2;
+ buffer_read <= '1';
+ word_count <= word_count + 1;
+
+ when START_COPY2 =>
+ state <= COPY;
+ buffer_read <= '1';
+ word_count <= word_count + 1;
+
+ when COPY =>
+
+ if word_count = WORD_LIMIT or buffer_valid = '0' then
+ state <= FINISH;
+ else
+ buffer_read <= '1';
+ word_count <= word_count + 1;
+ BUSRDO_TX.data <= buffer_dout;
+ BUSRDO_TX.data_write <= '1';
+ end if;
+
+ when FINISH =>
+ BUSRDO_TX.data_finished <= '1';
+ state <= DONE;
+
+ when DONE =>
+ BUSRDO_TX.busy_release <= '1';
+ state <= IDLE;
+ end case;
+
+end process;
+
+---------------------------------------------------------------------------
+-- Bus Handler
+---------------------------------------------------------------------------
+
+
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record
+ generic map(
+ PORT_NUMBER => 3,
+ PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", 2 => x"0200", others => x"0000"),
+ PORT_ADDR_MASK => (0 => 5, 1 => 5, 2 => 4, others => 0),
+ PORT_MASK_ENABLE => 1
+ )
+ port map(
+ CLK => CLK_SYS,
+ RESET => RESET,
+
+ REGIO_RX => BUS_RX,
+ REGIO_TX => BUS_TX,
+
+ BUS_RX(0) => businp_rx,
+ BUS_RX(1) => busword_rx,
+ BUS_RX(2) => busmimosis_rx,
+
+ BUS_TX(0) => businp_tx,
+ BUS_TX(1) => busword_tx,
+ BUS_TX(2) => busmimosis_tx,
+ STAT_DEBUG => open
+ );
+
+PROC_REGS : process
+ variable addr : integer range 0 to 7;
+begin
+ wait until rising_edge(CLK_SYS);
+ busmimosis_tx.ack <= '0';
+ busmimosis_tx.unknown <= '0';
+ busmimosis_tx.nack <= '0';
+ busmimosis_tx.data <= (others => '0');
+
+ if busmimosis_rx.write = '1' then
+ if busmimosis_rx.addr = x"0009" then
+ pulse_stats <= busmimosis_rx.data;
+ busmimosis_tx.ack <= '1';
+ else
+ busmimosis_tx.unknown <= '1';
+ end if;
+ elsif busmimosis_rx.read = '1' then
+ busmimosis_tx.ack <= '1';
+ if busmimosis_rx.addr = x"0000" then
+ busmimosis_tx.data <= std_logic_vector(count_header);
+ elsif busmimosis_rx.addr = x"0001" then
+ busmimosis_tx.data <= std_logic_vector(count_trailer);
+ elsif busmimosis_rx.addr = x"0002" then
+ busmimosis_tx.data <= x"0000" & frame_length;
+ elsif busmimosis_rx.addr = x"0003" then
+ busmimosis_tx.data <= frame_number;
+ elsif busmimosis_rx.addr = x"0004" then
+ busmimosis_tx.data <= x"0000" & std_logic_vector(count_words);
+ elsif busmimosis_rx.addr = x"0005" then
+ busmimosis_tx.data <= x"0000" & "00" & buffer_fill;
+ elsif busmimosis_rx.addr = x"0006" then
+ busmimosis_tx.data <= std_logic_vector(count_fe);
+ elsif busmimosis_rx.addr = x"0007" then
+ busmimosis_tx.data <= std_logic_vector(count_ff);
+ elsif busmimosis_rx.addr = x"0008" then
+ busmimosis_tx.data <= std_logic_vector(count_oof);
+ elsif busmimosis_rx.addr = x"0009" then
+ busmimosis_tx.data <= pulse_stats;
+ else
+ busmimosis_tx.ack <= '0';
+ busmimosis_tx.unknown <= '1';
+
+ end if;
+ end if;
+end process;
+
+end architecture;
--- /dev/null
+library IEEE;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+
+entity WordAlign is
+ port (
+ CLK : in std_logic;
+ CLK_SYS : in std_logic;
+ RESET : in std_logic;
+
+ DIN : in std_logic_vector(15 downto 0);
+ DOUT : out std_logic_vector(31 downto 0);
+ VALID : out std_logic;
+
+ ACTIVE : in std_logic;
+
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX
+ );
+end entity;
+
+
+architecture arch of WordAlign is
+ constant IDLE_WORD : std_logic_vector(15 downto 0) := x"FCAA";
+ constant HDR_WORD : std_logic_vector(15 downto 0) := x"FE00";
+
+
+ signal reset_i : std_logic;
+ type word_arr is array(0 to 7) of std_logic_vector(23 downto 0);
+ signal shift_reg, words, data_reg : word_arr;
+
+ signal doubleword : std_logic_vector(31 downto 0);
+ signal doubleword_valid : std_logic;
+
+ signal control_reg : std_logic_vector(31 downto 0);
+ alias CONF_channel_enable : std_logic_vector is control_reg(7 downto 0);
+ alias CONF_fixalign : std_logic is control_reg(8);
+ alias CONF_writeall : std_logic is control_reg(9);
+ alias CONF_ignoreactive : std_logic is control_reg(10);
+
+ signal bittime : integer range 0 to 31 := 0;
+
+ signal word_update : std_logic_vector(7 downto 0);
+ signal found_idle : std_logic_vector(7 downto 0) := (others => '0');
+ signal last_word_update, next_last_word_update : std_logic;
+ signal copycnt : integer range 0 to 4;
+
+begin
+
+bittime <= bittime + 1 when rising_edge(CLK);
+
+gen_links: for i in 0 to 7 generate
+ signal bitcnt : integer range 0 to 7 := 0;
+ signal oddeven : std_logic;
+ signal shift_reg : std_logic_vector(16 downto 0);
+begin
+ process begin
+ wait until rising_edge(CLK);
+ bitcnt <= bitcnt + 1;
+ word_update(i) <= '0';
+ shift_reg <= shift_reg(14 downto 0) & DIN(i*2) & DIN(i*2+1);
+
+ if CONF_fixalign = '0' and (ACTIVE = '1' or CONF_ignoreactive = '1') then
+ if shift_reg(15 downto 0) = IDLE_WORD then
+ oddeven <= '1';
+ bitcnt <= 1;
+ found_idle(i) <= '1';
+ elsif shift_reg(16 downto 1) = IDLE_WORD then
+ oddeven <= '0';
+ bitcnt <= 1;
+ found_idle(i) <= '1';
+ end if;
+ end if;
+
+ if bitcnt = 0 then
+ word_update(i) <= '1';
+ if oddeven = '1' then
+ words(i) <= std_logic_vector(to_unsigned(bittime,4)) & "000" & oddeven & shift_reg(15 downto 0);
+ else
+ words(i) <= std_logic_vector(to_unsigned(bittime,4)) & "000" & oddeven & shift_reg(16 downto 1);
+ end if;
+ end if;
+
+ end process;
+end generate;
+
+next_last_word_update <= word_update(0) when rising_edge(CLK);
+last_word_update <= next_last_word_update when rising_edge(CLK);
+
+PROC_COPY_MUX : process begin
+ wait until rising_edge(CLK);
+ doubleword_valid <= '0';
+ copycnt <= copycnt + 1;
+ if last_word_update = '1' then
+ data_reg <= words;
+ copycnt <= 0;
+ elsif copycnt = 0 then
+ doubleword <= data_reg(0)(15 downto 0) & data_reg(1)(15 downto 0);
+ doubleword_valid <= '1';
+ elsif copycnt = 1 then
+ doubleword <= data_reg(2)(15 downto 0) & data_reg(3)(15 downto 0);
+ doubleword_valid <= '1';
+ elsif copycnt = 2 then
+ doubleword <= data_reg(4)(15 downto 0) & data_reg(5)(15 downto 0);
+ doubleword_valid <= '1';
+ elsif copycnt = 3 then
+ doubleword <= data_reg(6)(15 downto 0) & data_reg(7)(15 downto 0);
+ doubleword_valid <= '1';
+ elsif copycnt = 4 then
+ copycnt <= copycnt;
+ end if;
+end process;
+
+PROC_FIFO_WRITE : process begin
+ wait until rising_edge(CLK);
+ DOUT <= doubleword;
+ VALID <= '0';
+ if doubleword_valid = '1' and (doubleword /= IDLE_WORD & IDLE_WORD or CONF_writeall = '1') then
+ VALID <= '1';
+ end if;
+end process;
+
+
+PROC_REGS : process
+ variable addr : integer range 0 to 7;
+begin
+ wait until rising_edge(CLK_SYS);
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '0';
+ BUS_TX.nack <= '0';
+ BUS_TX.data <= (others => '0');
+ addr := to_integer(unsigned(BUS_RX.addr(2 downto 0)));
+ if BUS_RX.write = '1' then
+ if BUS_RX.addr(15 downto 0) = x"0000" then
+ BUS_TX.ack <= '1';
+ control_reg <= BUS_RX.data;
+ else
+ BUS_TX.unknown <= '1';
+ end if;
+ elsif BUS_RX.read = '1' then
+ BUS_TX.ack <= '1';
+ if BUS_RX.addr(15 downto 0) = x"0000" then
+ BUS_TX.data <= control_reg;
+ elsif BUS_RX.addr(15 downto 4) = x"001" then
+ if BUS_RX.addr(3) = '0' then
+ BUS_TX.data <= "000" & found_idle(addr) & x"0" & words(addr);
+ else
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+ end if;
+ else
+ BUS_TX.ack <= '0';
+ BUS_TX.unknown <= '1';
+
+ end if;
+ end if;
+end process;
+
+
+
+end architecture;
--- /dev/null
+../../trb3sc/scripts/compile.pl
\ No newline at end of file
--- /dev/null
+library ieee;
+USE IEEE.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+use work.trb_net_std.all;
+
+package config is
+
+
+------------------------------------------------------------------------------
+--Begin of design configuration
+------------------------------------------------------------------------------
+
+
+--set to 0 for backplane serdes, set to 1 for SFP serdes
+ constant SERDES_NUM : integer := 1;
+
+--TDC settings
+ constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5
+ constant FPGA_SIZE : string := "85KUM";
+-- constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement
+-- constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module
+-- constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons
+-- constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3
+-- -- 0: single edge only,
+-- -- 1: same channel,
+-- -- 2: alternating channels,
+-- -- 3: same channel with stretcher
+-- constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size
+-- -- mode: 0, 1, 2, 3, 7
+-- -- size: 32, 64, 96, 128, dyn
+-- constant TDC_DATA_FORMAT : integer range 0 to 3 := 0; --type of data format for the TDC
+-- -- 0: Single fine time as the sum of the two transitions
+-- -- 1: Double fine time, individual transitions
+-- -- 13: Debug - fine time + (if 0x3ff full chain)
+-- -- 14: Debug - single fine time and the ROM addresses for the two transitions
+-- -- 15: Debug - complete carry chain dump
+
+ constant EVENT_BUFFER_SIZE : integer range 9 to 15 := 15; -- size of the event buffer, 2**N
+ constant EVENT_MAX_SIZE : integer := 15000; --maximum event size. Must not exceed EVENT_BUFFER_SIZE/2
+ constant USE_GBE : integer := c_YES;
+
+--Runs with 120 MHz instead of 100 MHz
+ constant USE_120_MHZ : integer := c_NO;
+
+--Use sync mode, RX clock for all parts of the FPGA
+ constant USE_RXCLOCK : integer := c_NO;
+
+--Address settings
+ constant INIT_ADDRESS : std_logic_vector := x"F575";
+ constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"82";
+
+ constant INCLUDE_UART : integer := c_NO;
+ constant INCLUDE_SPI : integer := c_NO;
+ constant INCLUDE_ADC : integer := c_YES;
+ constant INCLUDE_I2C : integer := c_YES;
+ constant INCLUDE_DEBUG_INTERFACE: integer := c_NO;
+
+ --input monitor and trigger generation logic
+ constant INCLUDE_TRIGGER_LOGIC : integer := c_NO;
+ constant INCLUDE_STATISTICS : integer := c_NO;
+ constant TRIG_GEN_INPUT_NUM : integer := 32;
+ constant TRIG_GEN_OUTPUT_NUM : integer := 4;
+ constant MONITOR_INPUT_NUM : integer := 32;
+
+------------------------------------------------------------------------------
+--End of design configuration
+------------------------------------------------------------------------------
+
+------------------------------------------------------------------------------
+--Select settings by configuration
+------------------------------------------------------------------------------
+ type intlist_t is array(0 to 7) of integer;
+ type hw_info_t is array(0 to 7) of unsigned(31 downto 0);
+ constant HW_INFO_BASE : unsigned(31 downto 0) := x"A5000000";
+
+ constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0);
+ constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0);
+
+ --declare constants, filled in body
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0);
+ constant CLOCK_FREQUENCY : integer;
+ constant MEDIA_FREQUENCY : integer;
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0);
+ constant BROADCAST_BITMASK : std_logic_vector(7 downto 0) := (7 => (not std_logic_vector(to_unsigned(USE_GBE,1))(0)), others => '1');
+
+end;
+
+package body config is
+--compute correct configuration mode
+
+ constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( HW_INFO_BASE );
+ constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ);
+ constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ);
+
+function generateIncludedFeatures return std_logic_vector is
+ variable t : std_logic_vector(63 downto 0);
+ begin
+ t := (others => '0');
+ t(63 downto 56) := std_logic_vector(to_unsigned(2,8)); --table version 1
+
+-- t(7 downto 0) := std_logic_vector(to_unsigned(1,8));
+-- t(11 downto 8) := std_logic_vector(to_unsigned(DOUBLE_EDGE_TYPE,4));
+-- t(14 downto 12) := std_logic_vector(to_unsigned(RING_BUFFER_SIZE,3));
+-- t(15) := '1'; --TDC
+-- t(17 downto 16) := std_logic_vector(to_unsigned(NUM_TDC_MODULES-1,2));
+ t(16 downto 16) := std_logic_vector(to_unsigned(USE_GBE,1));
+ t(28 downto 28) := std_logic_vector(to_unsigned(1-SERDES_NUM,1));
+
+ t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1));
+ t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1));
+ t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1));
+ t(47 downto 47) := std_logic_vector(to_unsigned(INCLUDE_I2C,1));
+ t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4));
+ t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1));
+ t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1));
+ t(54 downto 54) := "0";--std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1));
+ return t;
+ end function;
+
+ constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures;
+
+end package body;
--- /dev/null
+Familyname => 'ECP5UM',
+Devicename => 'LFE5UM-85F',
+Package => 'CABGA756',
+Speedgrade => '8',
+
+
+TOPNAME => "trb5sc_vldb",
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par => "1702\@jspc29",
+lattice_path => '/d/jspc29/lattice/diamond/3.12',
+synplify_path => '/d/jspc29/lattice/synplify/S-2021.09-SP2/',
+
+nodelist_file => '../nodelist_frankfurt.txt',
+pinout_file => 'trb5sc_hdmi',
+par_options => '../par.p2t',
+
+
+#Include only necessary lpf files
+include_TDC => 0,
+include_GBE => 0,
+
+#Report settings
+firefox_open => 0,
+twr_number_of_errors => 20,
+no_ltxt2ptxt => 1, #if there is no serdes being used
--- /dev/null
+###==== Start Configuration
+
--- /dev/null
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG756C
+SpeedGrade=8
+Package=CABGA756
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=DDR_GENERIC
+CoreRevision=6.0
+ModuleName=mimosis_inp
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=06/03/2019
+Time=14:45:56
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+mode=Receive
+trioddr=0
+io_type=LVDS
+width=8
+freq_in=160
+bandwidth=2560
+aligned=Edge-to-Edge
+pre-configuration=DISABLED
+mode2=Receive
+trioddr2=0
+io_type2=LVDS
+freq_in2=160
+gear=2:1
+aligned2=Centered
+width2=8
+DataLane=By Lane
+EnECLK=0
+Interface=GDDRX1_RX.SCLK.Centered
+Delay=Dynamic User Defined
+DelVal=1
+EnInEdge=
+NumEdge=BOTH
+EnDynamic=0
+GenPll=0
+Freq=
+AFreq=
+Reference=0
+IOBUF=
+ReceiverSync=0
+EnDynamicAlign=
+DynamicAlign=
+MIPIFilter=0
+enClkIBuf=0
+ClkIBuf=LVDS
+
+[Command]
+cmd_line= -w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane
--- /dev/null
+<!DOCTYPE mimosis_inp>
+<lattice:project mode="SingleComponent">
+ <spirit:component>
+ <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+ <spirit:library>LEGACY</spirit:library>
+ <spirit:name>DDR_GENERIC</spirit:name>
+ <spirit:version>6.0</spirit:version>
+ <spirit:fileSets>
+ <spirit:fileset>
+ <spirit:name>Diamond_Simulation</spirit:name>
+ <spirit:group>simulation</spirit:group>
+ <spirit:file>
+ <spirit:name>./mimosis_inp.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ <spirit:fileset>
+ <spirit:name>Diamond_Synthesis</spirit:name>
+ <spirit:group>synthesis</spirit:group>
+ <spirit:file>
+ <spirit:name>./mimosis_inp.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ </spirit:fileSets>
+ <spirit:componentGenerators>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Configuration</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>CONFIG</spirit:group>
+ </spirit:componentGenerator>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Generation</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>GENERATE</spirit:group>
+ </spirit:componentGenerator>
+ </spirit:componentGenerators>
+ <spirit:model>
+ <spirit:views/>
+ <spirit:ports/>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <lattice:device>LFE5UM-85F-8BG756C</lattice:device>
+ <lattice:synthesis>synplify</lattice:synthesis>
+ <lattice:date>2019-05-31.19:33:04</lattice:date>
+ <lattice:modified>2019-06-03.14:45:58</lattice:modified>
+ <lattice:diamond>3.10.3.144</lattice:diamond>
+ <lattice:language>VHDL</lattice:language>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+ <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+ <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+ <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+ <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+ </lattice:attributes>
+ <lattice:elements/>
+ <lattice:lpc>
+ <lattice:lpcsection lattice:name="Device"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>Family</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>OperatingCondition</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Package</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SpeedGrade</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Status</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="IP"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DDR_GENERIC</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreRevision</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">6.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreStatus</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Date</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">06/03/2019</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ModuleName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">mimosis_inp</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SourceFormat</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Time</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">14:45:56</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VendorName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Parameters"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>AFreq</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ClkIBuf</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>DataLane</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">By Lane</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>DelVal</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Delay</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Dynamic User Defined</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Destination</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>DynamicAlign</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EDIF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnDynamic</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnDynamicAlign</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnECLK</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnInEdge</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Expression</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Freq</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>GenPll</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IO</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IOBUF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Interface</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">GDDRX1_RX.SCLK.Centered</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>MIPIFilter</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>NumEdge</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BOTH</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Order</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ReceiverSync</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reference</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VHDL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Verilog</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>aligned</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Edge-to-Edge</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>aligned2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Centered</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>bandwidth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2560</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>enClkIBuf</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>freq_in</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">160</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>freq_in2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">160</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>gear</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2:1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>io_type</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>io_type2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>mode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Receive</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>mode2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Receive</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>pre-configuration</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>trioddr</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>trioddr2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>width</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>width2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Command"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>cmd_line</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">-w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane</lattice:lpcvalue>
+ </lattice:lpcentry>
+ </lattice:lpc>
+ <lattice:groups/>
+ </spirit:vendorExtensions>
+ </spirit:component>
+ <spirit:design>
+ <spirit:vendor>LATTICE</spirit:vendor>
+ <spirit:library>LOCAL</spirit:library>
+ <spirit:name>mimosis_inp</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances/>
+ <spirit:adHocConnections/>
+ </spirit:design>
+</lattice:project>
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144
+-- Module Version: 5.8
+--/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n mimosis_inp -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Receive -io_type LVDS -width 8 -freq_in 160 -gear 2 -del 1 -dynamic_delay -data_lane -fdc /d/jspc22/trb/lattice/sio/mimosis_inp/mimosis_inp.fdc
+
+-- Mon Jun 3 14:45:58 2019
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity mimosis_inp is
+ port (
+ clkin: in std_logic;
+ reset: in std_logic;
+ sclk: out std_logic;
+ data_cflag: out std_logic_vector(7 downto 0);
+ data_direction: in std_logic_vector(7 downto 0);
+ data_loadn: in std_logic_vector(7 downto 0);
+ data_move: in std_logic_vector(7 downto 0);
+ datain: in std_logic_vector(7 downto 0);
+ q: out std_logic_vector(15 downto 0));
+end mimosis_inp;
+
+architecture Structure of mimosis_inp is
+
+ -- internal signal declarations
+ signal buf_clkin: std_logic;
+ signal qb7: std_logic;
+ signal qa7: std_logic;
+ signal qb6: std_logic;
+ signal qa6: std_logic;
+ signal qb5: std_logic;
+ signal qa5: std_logic;
+ signal qb4: std_logic;
+ signal qa4: std_logic;
+ signal qb3: std_logic;
+ signal qa3: std_logic;
+ signal qb2: std_logic;
+ signal qa2: std_logic;
+ signal qb1: std_logic;
+ signal qa1: std_logic;
+ signal qb0: std_logic;
+ signal qa0: std_logic;
+ signal sclk_t: std_logic;
+ signal dataini_t7: std_logic;
+ signal dataini_t6: std_logic;
+ signal dataini_t5: std_logic;
+ signal dataini_t4: std_logic;
+ signal dataini_t3: std_logic;
+ signal dataini_t2: std_logic;
+ signal dataini_t1: std_logic;
+ signal dataini_t0: std_logic;
+ signal buf_dataini7: std_logic;
+ signal buf_dataini6: std_logic;
+ signal buf_dataini5: std_logic;
+ signal buf_dataini4: std_logic;
+ signal buf_dataini3: std_logic;
+ signal buf_dataini2: std_logic;
+ signal buf_dataini1: std_logic;
+ signal buf_dataini0: std_logic;
+
+ attribute IO_TYPE : string;
+-- attribute IO_TYPE of Inst3_IB : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB7 : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB6 : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB5 : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB4 : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB3 : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB2 : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB1 : label is "LVDS";
+ attribute IO_TYPE of Inst1_IB0 : label is "LVDS";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+-- Inst3_IB: IB
+-- port map (I=>clkin, O=>buf_clkin);
+buf_clkin <= clkin;
+
+ Inst2_IDDRX1F7: IDDRX1F
+ port map (D=>dataini_t7, SCLK=>sclk_t, RST=>reset, Q0=>qa7,
+ Q1=>qb7);
+
+ Inst2_IDDRX1F6: IDDRX1F
+ port map (D=>dataini_t6, SCLK=>sclk_t, RST=>reset, Q0=>qa6,
+ Q1=>qb6);
+
+ Inst2_IDDRX1F5: IDDRX1F
+ port map (D=>dataini_t5, SCLK=>sclk_t, RST=>reset, Q0=>qa5,
+ Q1=>qb5);
+
+ Inst2_IDDRX1F4: IDDRX1F
+ port map (D=>dataini_t4, SCLK=>sclk_t, RST=>reset, Q0=>qa4,
+ Q1=>qb4);
+
+ Inst2_IDDRX1F3: IDDRX1F
+ port map (D=>dataini_t3, SCLK=>sclk_t, RST=>reset, Q0=>qa3,
+ Q1=>qb3);
+
+ Inst2_IDDRX1F2: IDDRX1F
+ port map (D=>dataini_t2, SCLK=>sclk_t, RST=>reset, Q0=>qa2,
+ Q1=>qb2);
+
+ Inst2_IDDRX1F1: IDDRX1F
+ port map (D=>dataini_t1, SCLK=>sclk_t, RST=>reset, Q0=>qa1,
+ Q1=>qb1);
+
+ Inst2_IDDRX1F0: IDDRX1F
+ port map (D=>dataini_t0, SCLK=>sclk_t, RST=>reset, Q0=>qa0,
+ Q1=>qb0);
+
+ udel_dataini7: DELAYF
+ generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini7, LOADN=>data_loadn(7),
+ MOVE=>data_move(7), DIRECTION=>data_direction(7),
+ Z=>dataini_t7, CFLAG=>data_cflag(7));
+
+ udel_dataini6: DELAYF
+ generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini6, LOADN=>data_loadn(6),
+ MOVE=>data_move(6), DIRECTION=>data_direction(6),
+ Z=>dataini_t6, CFLAG=>data_cflag(6));
+
+ udel_dataini5: DELAYF
+ generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini5, LOADN=>data_loadn(5),
+ MOVE=>data_move(5), DIRECTION=>data_direction(5),
+ Z=>dataini_t5, CFLAG=>data_cflag(5));
+
+ udel_dataini4: DELAYF
+ generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini4, LOADN=>data_loadn(4),
+ MOVE=>data_move(4), DIRECTION=>data_direction(4),
+ Z=>dataini_t4, CFLAG=>data_cflag(4));
+
+ udel_dataini3: DELAYF
+ generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini3, LOADN=>data_loadn(3),
+ MOVE=>data_move(3), DIRECTION=>data_direction(3),
+ Z=>dataini_t3, CFLAG=>data_cflag(3));
+
+ udel_dataini2: DELAYF
+ generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini2, LOADN=>data_loadn(2),
+ MOVE=>data_move(2), DIRECTION=>data_direction(2),
+ Z=>dataini_t2, CFLAG=>data_cflag(2));
+
+ udel_dataini1: DELAYF
+ generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini1, LOADN=>data_loadn(1),
+ MOVE=>data_move(1), DIRECTION=>data_direction(1),
+ Z=>dataini_t1, CFLAG=>data_cflag(1));
+
+ udel_dataini0: DELAYF
+ generic map (DEL_VALUE=> 0, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_dataini0, LOADN=>data_loadn(0),
+ MOVE=>data_move(0), DIRECTION=>data_direction(0),
+ Z=>dataini_t0, CFLAG=>data_cflag(0));
+
+ Inst1_IB7: IB
+ port map (I=>datain(7), O=>buf_dataini7);
+
+ Inst1_IB6: IB
+ port map (I=>datain(6), O=>buf_dataini6);
+
+ Inst1_IB5: IB
+ port map (I=>datain(5), O=>buf_dataini5);
+
+ Inst1_IB4: IB
+ port map (I=>datain(4), O=>buf_dataini4);
+
+ Inst1_IB3: IB
+ port map (I=>datain(3), O=>buf_dataini3);
+
+ Inst1_IB2: IB
+ port map (I=>datain(2), O=>buf_dataini2);
+
+ Inst1_IB1: IB
+ port map (I=>datain(1), O=>buf_dataini1);
+
+ Inst1_IB0: IB
+ port map (I=>datain(0), O=>buf_dataini0);
+
+ sclk <= sclk_t;
+ q(15) <= qb7;
+ q(14) <= qa7;
+ q(13) <= qb6;
+ q(12) <= qa6;
+ q(11) <= qb5;
+ q(10) <= qa5;
+ q(9) <= qb4;
+ q(8) <= qa4;
+ q(7) <= qb3;
+ q(6) <= qa3;
+ q(5) <= qb2;
+ q(4) <= qa2;
+ q(3) <= qb1;
+ q(2) <= qa1;
+ q(1) <= qb0;
+ q(0) <= qa0;
+ sclk_t <= buf_clkin;
+end Structure;
--- /dev/null
+###==== Start Configuration
+
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_200_160" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2021 11 12 15:18:46.939" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="pll_200_160.lpc" type="lpc" modified="2021 11 12 15:18:43.000"/>
+ <File name="pll_200_160.vhd" type="top_level_vhdl" modified="2021 11 12 15:18:43.000"/>
+ <File name="pll_200_160_tmpl.vhd" type="template_vhdl" modified="2021 11 12 15:18:43.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG756C
+SpeedGrade=8
+Package=CABGA756
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll_200_160
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=11/12/2021
+Time=15:18:43
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+CLKI_FREQ=200
+CLKI_DIV=5
+ENABLE_HBW=DISABLED
+REFERENCE=0
+IOBUF=LVDS
+CLKOP_FREQ=160
+CLKOP_TOL=0.0
+CLKOP_DIV=4
+CLKOP_ACTUAL_FREQ=160.000000
+CLKOP_MUXA=DISABLED
+CLKOS_Enable=ENABLED
+CLKOS_FREQ=320
+CLKOS_TOL=0.0
+CLKOS_DIV=2
+CLKOS_ACTUAL_FREQ=320.000000
+CLKOS_MUXB=DISABLED
+CLKOS2_Enable=ENABLED
+CLKOS2_FREQ=40.00
+CLKOS2_TOL=0.0
+CLKOS2_DIV=16
+CLKOS2_ACTUAL_FREQ=40.000000
+CLKOS2_MUXC=DISABLED
+CLKOS3_Enable=DISABLED
+CLKOS3_FREQ=100.00
+CLKOS3_TOL=0.0
+CLKOS3_DIV=1
+CLKOS3_ACTUAL_FREQ=
+CLKOS3_MUXD=DISABLED
+FEEDBK_PATH=CLKOP
+CLKFB_DIV=4
+FRACN_ENABLE=DISABLED
+FRACN_DIV=
+VCO_RATE=640.000
+PLL_BW=4.655
+CLKOP_DPHASE=0
+CLKOP_APHASE=0.00
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+CLKOS_DPHASE=0
+CLKOS_APHASE=0.00
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+CLKOS2_DPHASE=0
+CLKOS2_APHASE=0.00
+CLKOS2_TRIM_POL=Rising
+CLKOS2_TRIM_DELAY=0
+CLKOS3_DPHASE=0
+CLKOS3_APHASE=0.00
+CLKOS3_TRIM_POL=Rising
+CLKOS3_TRIM_DELAY=0
+CLKSEL_ENA=DISABLED
+DPHASE_SOURCE=STATIC
+ENABLE_CLKOP=DISABLED
+ENABLE_CLKOS=DISABLED
+ENABLE_CLKOS2=DISABLED
+ENABLE_CLKOS3=DISABLED
+STDBY_ENABLE=DISABLED
+PLLRST_ENA=DISABLED
+PLL_LOCK_MODE=DISABLED
+PLL_LOCK_STK=DISABLED
+PLL_USE_SMI=DISABLED
+
+[Command]
+cmd_line= -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -fclkos2 40.00 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -fb_mode 1
--- /dev/null
+<!DOCTYPE pll_200_160>
+<lattice:project mode="SingleComponent">
+ <spirit:component>
+ <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+ <spirit:library>LEGACY</spirit:library>
+ <spirit:name>PLL</spirit:name>
+ <spirit:version>5.8</spirit:version>
+ <spirit:fileSets>
+ <spirit:fileset>
+ <spirit:name>Diamond_Simulation</spirit:name>
+ <spirit:group>simulation</spirit:group>
+ <spirit:file>
+ <spirit:name>./pll_200_160.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ <spirit:fileset>
+ <spirit:name>Diamond_Synthesis</spirit:name>
+ <spirit:group>synthesis</spirit:group>
+ <spirit:file>
+ <spirit:name>./pll_200_160.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ </spirit:fileSets>
+ <spirit:componentGenerators>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Configuration</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>CONFIG</spirit:group>
+ </spirit:componentGenerator>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Generation</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>GENERATE</spirit:group>
+ </spirit:componentGenerator>
+ </spirit:componentGenerators>
+ <spirit:model>
+ <spirit:views/>
+ <spirit:ports/>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <lattice:device>LFE5UM-85F-8BG756C</lattice:device>
+ <lattice:synthesis>synplify</lattice:synthesis>
+ <lattice:date>2019-06-04.11:21:55</lattice:date>
+ <lattice:modified>2021-07-02.12:08:04</lattice:modified>
+ <lattice:diamond>3.11.2.446</lattice:diamond>
+ <lattice:language>VHDL</lattice:language>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+ <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+ <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+ <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+ <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+ </lattice:attributes>
+ <lattice:elements/>
+ <lattice:lpc>
+ <lattice:lpcsection lattice:name="Device"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>Family</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>OperatingCondition</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Package</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SpeedGrade</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Status</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="IP"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">PLL</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreRevision</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">5.8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreStatus</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Date</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">07/02/2021</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ModuleName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">pll_200_160</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SourceFormat</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Time</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">12:07:59</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VendorName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Parameters"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKFB_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">4</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKI_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">5</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKI_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">200</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_ACTUAL_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">160.000000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_APHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">4</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_DPHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">160</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_MUXA</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_TOL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_TRIM_DELAY</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOP_TRIM_POL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_ACTUAL_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_APHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_DPHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_Enable</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_MUXC</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_TOL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_TRIM_DELAY</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS2_TRIM_POL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_ACTUAL_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_APHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_DPHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_Enable</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">100.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_MUXD</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_TOL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_TRIM_DELAY</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS3_TRIM_POL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_ACTUAL_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">320.000000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_APHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.00</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_DPHASE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_Enable</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ENABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_FREQ</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">320</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_MUXB</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_TOL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_TRIM_DELAY</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKOS_TRIM_POL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Rising</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CLKSEL_ENA</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>DPHASE_SOURCE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">STATIC</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Destination</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EDIF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ENABLE_CLKOP</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ENABLE_CLKOS</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ENABLE_CLKOS2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ENABLE_CLKOS3</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ENABLE_HBW</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Expression</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FEEDBK_PATH</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CLKOP</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FRACN_DIV</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>FRACN_ENABLE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IO</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IOBUF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Order</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PLLRST_ENA</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PLL_BW</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">4.655</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PLL_LOCK_MODE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PLL_LOCK_STK</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PLL_USE_SMI</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>REFERENCE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>STDBY_ENABLE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VCO_RATE</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">640.000</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VHDL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Verilog</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Command"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>cmd_line</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">-w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -phase_cntl STATIC -fb_mode 1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ </lattice:lpc>
+ <lattice:groups/>
+ </spirit:vendorExtensions>
+ </spirit:component>
+ <spirit:design>
+ <spirit:vendor>LATTICE</spirit:vendor>
+ <spirit:library>LOCAL</spirit:library>
+ <spirit:name>pll_200_160</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances/>
+ <spirit:adHocConnections/>
+ </spirit:design>
+</lattice:project>
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454
+-- Module Version: 5.7
+--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -fclkos2 40.00 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -fb_mode 1
+
+-- Fri Nov 12 15:18:43 2021
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity pll_200_160 is
+ port (
+ CLKI: in std_logic;
+ CLKOP: out std_logic;
+ CLKOS: out std_logic;
+ CLKOS2: out std_logic);
+end pll_200_160;
+
+architecture Structure of pll_200_160 is
+
+ -- internal signal declarations
+ signal REFCLK: std_logic;
+ signal LOCK: std_logic;
+ signal CLKOS2_t: std_logic;
+ signal CLKOS_t: std_logic;
+ signal CLKOP_t: std_logic;
+ signal scuba_vhi: std_logic;
+ signal scuba_vlo: std_logic;
+
+ attribute FREQUENCY_PIN_CLKOS2 : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute ICP_CURRENT : string;
+ attribute LPF_RESISTOR : string;
+ attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "40.000000";
+ attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "320.000000";
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "160.000000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+ attribute ICP_CURRENT of PLLInst_0 : label is "12";
+ attribute LPF_RESISTOR of PLLInst_0 : label is "8";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLL
+ generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
+ STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
+ CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0,
+ CLKOS2_CPHASE=> 15, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 1,
+ CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 3, PLL_LOCK_MODE=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING",
+ OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED",
+ OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "ENABLED",
+ OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED",
+ OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1,
+ CLKOS2_DIV=> 16, CLKOS_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 4,
+ CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP")
+ port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo,
+ PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
+ PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo,
+ STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo,
+ ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo,
+ ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
+ CLKOS2=>CLKOS2_t, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open,
+ REFCLK=>REFCLK, CLKINTFB=>open);
+
+ CLKOS2 <= CLKOS2_t;
+ CLKOS <= CLKOS_t;
+ CLKOP <= CLKOP_t;
+end Structure;
--- /dev/null
+[Device]
+Family=ecp5um
+PartType=LFE5UM-85F
+PartName=LFE5UM-85F-8BG756C
+SpeedGrade=8
+Package=CABGA756
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=DDR_GENERIC
+CoreRevision=6.0
+ModuleName=testout
+SourceFormat=vhdl
+ParameterFileVersion=1.0
+Date=06/05/2019
+Time=14:55:39
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+mode=Transmit
+trioddr=0
+io_type=LVDS
+width=8
+freq_in=160
+bandwidth=2560
+aligned=Edge-to-Edge
+pre-configuration=DISABLED
+mode2=Transmit
+trioddr2=0
+io_type2=LVDS
+freq_in2=160
+gear=2:1
+aligned2=Edge-to-Edge
+width2=8
+DataLane=By Lane
+EnECLK=0
+Interface=GDDRX1_TX.SCLK.Aligned
+Delay=Dynamic User Defined
+DelVal=1
+EnInEdge=
+NumEdge=BOTH
+EnDynamic=0
+GenPll=0
+Freq=
+AFreq=
+Reference=0
+IOBUF=
+ReceiverSync=0
+EnDynamicAlign=
+DynamicAlign=
+MIPIFilter=0
+enClkIBuf=0
+ClkIBuf=LVDS
+
+[Command]
+cmd_line= -w -n testout -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 8 -freq_in 160 -gear 2 -aligned -del 1 -dynamic_delay -data_lane
--- /dev/null
+<!DOCTYPE testout>
+<lattice:project mode="SingleComponent">
+ <spirit:component>
+ <spirit:vendor>Lattice Semiconductor Corporation</spirit:vendor>
+ <spirit:library>LEGACY</spirit:library>
+ <spirit:name>DDR_GENERIC</spirit:name>
+ <spirit:version>6.0</spirit:version>
+ <spirit:fileSets>
+ <spirit:fileset>
+ <spirit:name>Diamond_Simulation</spirit:name>
+ <spirit:group>simulation</spirit:group>
+ <spirit:file>
+ <spirit:name>./testout.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ <spirit:fileset>
+ <spirit:name>Diamond_Synthesis</spirit:name>
+ <spirit:group>synthesis</spirit:group>
+ <spirit:file>
+ <spirit:name>./testout.vhd</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileset>
+ </spirit:fileSets>
+ <spirit:componentGenerators>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Configuration</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>CONFIG</spirit:group>
+ </spirit:componentGenerator>
+ <spirit:componentGenerator spirit:hidden="true" spirit:scope="instance">
+ <spirit:name>Generation</spirit:name>
+ <spirit:apiType>none</spirit:apiType>
+ <spirit:generatorExe>${sbp_path}/${instance}/generate_core.tcl</spirit:generatorExe>
+ <spirit:group>GENERATE</spirit:group>
+ </spirit:componentGenerator>
+ </spirit:componentGenerators>
+ <spirit:model>
+ <spirit:views/>
+ <spirit:ports/>
+ </spirit:model>
+ <spirit:vendorExtensions>
+ <lattice:device>LFE5UM-85F-8BG756C</lattice:device>
+ <lattice:synthesis>synplify</lattice:synthesis>
+ <lattice:date>2019-06-05.14:55:41</lattice:date>
+ <lattice:modified>2019-06-05.14:55:41</lattice:modified>
+ <lattice:diamond>3.10.3.144</lattice:diamond>
+ <lattice:language>VHDL</lattice:language>
+ <lattice:attributes>
+ <lattice:attribute lattice:name="AddComponent">false</lattice:attribute>
+ <lattice:attribute lattice:name="BBox">false</lattice:attribute>
+ <lattice:attribute lattice:name="Change4to5">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConfig">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeConnect">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeDevice">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeLocate">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePack">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangePart">false</lattice:attribute>
+ <lattice:attribute lattice:name="ChangeSynthesis">false</lattice:attribute>
+ <lattice:attribute lattice:name="CoreType">LPM</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_RXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="DCU_TXREFCLK">PRIMARY</lattice:attribute>
+ <lattice:attribute lattice:name="Migrate">false</lattice:attribute>
+ <lattice:attribute lattice:name="RemovedComponent">false</lattice:attribute>
+ </lattice:attributes>
+ <lattice:elements/>
+ <lattice:lpc>
+ <lattice:lpcsection lattice:name="Device"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>Family</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">ecp5um</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>OperatingCondition</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">COM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Package</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">CABGA756</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F-8BG756C</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>PartType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LFE5UM-85F</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SpeedGrade</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Status</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">P</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="IP"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DDR_GENERIC</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreRevision</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">6.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreStatus</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Demo</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>CoreType</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LPM</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Date</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">06/05/2019</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ModuleName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">testout</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ParameterFileVersion</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1.0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>SourceFormat</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">vhdl</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Time</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">14:55:39</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VendorName</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Lattice Semiconductor Corporation</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Parameters"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>AFreq</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ClkIBuf</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>DataLane</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">By Lane</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>DelVal</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Delay</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Dynamic User Defined</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Destination</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Synplicity</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>DynamicAlign</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EDIF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnDynamic</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnDynamicAlign</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnECLK</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>EnInEdge</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Expression</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BusA(0 to 7)</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Freq</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>GenPll</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IO</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>IOBUF</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant"></lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Interface</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">GDDRX1_TX.SCLK.Aligned</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>MIPIFilter</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>NumEdge</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">BOTH</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Order</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Big Endian [MSB:LSB]</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>ReceiverSync</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Reference</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>VHDL</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>Verilog</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>aligned</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Edge-to-Edge</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>aligned2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Edge-to-Edge</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>bandwidth</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2560</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>enClkIBuf</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>freq_in</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">160</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>freq_in2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">160</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>gear</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">2:1</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>io_type</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>io_type2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">LVDS</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>mode</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Transmit</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>mode2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">Transmit</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>pre-configuration</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">DISABLED</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>trioddr</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>trioddr2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">0</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>width</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcentry>
+ <lattice:lpckey>width2</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">8</lattice:lpcvalue>
+ </lattice:lpcentry>
+ <lattice:lpcsection lattice:name="Command"/>
+ <lattice:lpcentry>
+ <lattice:lpckey>cmd_line</lattice:lpckey>
+ <lattice:lpcvalue lattice:resolve="constant">-w -n testout -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 8 -freq_in 160 -gear 2 -aligned -del 1 -dynamic_delay -data_lane</lattice:lpcvalue>
+ </lattice:lpcentry>
+ </lattice:lpc>
+ <lattice:groups/>
+ </spirit:vendorExtensions>
+ </spirit:component>
+ <spirit:design>
+ <spirit:vendor>LATTICE</spirit:vendor>
+ <spirit:library>LOCAL</spirit:library>
+ <spirit:name>testout</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:componentInstances/>
+ <spirit:adHocConnections/>
+ </spirit:design>
+</lattice:project>
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144
+-- Module Version: 5.8
+--/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n testout -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type iol -mode Transmit -io_type LVDS -width 8 -freq_in 160 -gear 2 -aligned -del 1 -dynamic_delay -data_lane -fdc /d/jspc22/trb/lattice/sio/testout/testout.fdc
+
+-- Wed Jun 5 14:55:41 2019
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+library ecp5um;
+use ecp5um.components.all;
+
+entity testout is
+ port (
+ clkout: out std_logic;
+ refclk: in std_logic;
+ reset: in std_logic;
+ data: in std_logic_vector(15 downto 0);
+ data_cflag: out std_logic_vector(7 downto 0);
+ data_direction: in std_logic_vector(7 downto 0);
+ data_loadn: in std_logic_vector(7 downto 0);
+ data_move: in std_logic_vector(7 downto 0);
+ dout: out std_logic_vector(7 downto 0));
+end testout;
+
+architecture Structure of testout is
+
+ -- internal signal declarations
+ signal db7: std_logic;
+ signal da7: std_logic;
+ signal db6: std_logic;
+ signal da6: std_logic;
+ signal db5: std_logic;
+ signal da5: std_logic;
+ signal db4: std_logic;
+ signal da4: std_logic;
+ signal db3: std_logic;
+ signal da3: std_logic;
+ signal db2: std_logic;
+ signal da2: std_logic;
+ signal db1: std_logic;
+ signal da1: std_logic;
+ signal db0: std_logic;
+ signal da0: std_logic;
+ signal scuba_vlo: std_logic;
+ signal scuba_vhi: std_logic;
+ signal sclk_t: std_logic;
+ signal clkos: std_logic;
+ signal clkop: std_logic;
+ signal buf_clkout: std_logic;
+ signal douto_t7: std_logic;
+ signal buf_douto7: std_logic;
+ signal douto_t6: std_logic;
+ signal buf_douto6: std_logic;
+ signal douto_t5: std_logic;
+ signal buf_douto5: std_logic;
+ signal douto_t4: std_logic;
+ signal buf_douto4: std_logic;
+ signal douto_t3: std_logic;
+ signal buf_douto3: std_logic;
+ signal douto_t2: std_logic;
+ signal buf_douto2: std_logic;
+ signal douto_t1: std_logic;
+ signal buf_douto1: std_logic;
+ signal douto_t0: std_logic;
+ signal buf_douto0: std_logic;
+
+ attribute IO_TYPE : string;
+ attribute IO_TYPE of Inst2_OB : label is "LVDS";
+ attribute IO_TYPE of Inst1_OB7 : label is "LVDS";
+ attribute IO_TYPE of Inst1_OB6 : label is "LVDS";
+ attribute IO_TYPE of Inst1_OB5 : label is "LVDS";
+ attribute IO_TYPE of Inst1_OB4 : label is "LVDS";
+ attribute IO_TYPE of Inst1_OB3 : label is "LVDS";
+ attribute IO_TYPE of Inst1_OB2 : label is "LVDS";
+ attribute IO_TYPE of Inst1_OB1 : label is "LVDS";
+ attribute IO_TYPE of Inst1_OB0 : label is "LVDS";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ Inst4_ODDRX1F7: ODDRX1F
+ port map (SCLK=>sclk_t, RST=>reset, D0=>da7, D1=>db7,
+ Q=>buf_douto7);
+
+ Inst4_ODDRX1F6: ODDRX1F
+ port map (SCLK=>sclk_t, RST=>reset, D0=>da6, D1=>db6,
+ Q=>buf_douto6);
+
+ Inst4_ODDRX1F5: ODDRX1F
+ port map (SCLK=>sclk_t, RST=>reset, D0=>da5, D1=>db5,
+ Q=>buf_douto5);
+
+ Inst4_ODDRX1F4: ODDRX1F
+ port map (SCLK=>sclk_t, RST=>reset, D0=>da4, D1=>db4,
+ Q=>buf_douto4);
+
+ Inst4_ODDRX1F3: ODDRX1F
+ port map (SCLK=>sclk_t, RST=>reset, D0=>da3, D1=>db3,
+ Q=>buf_douto3);
+
+ Inst4_ODDRX1F2: ODDRX1F
+ port map (SCLK=>sclk_t, RST=>reset, D0=>da2, D1=>db2,
+ Q=>buf_douto2);
+
+ Inst4_ODDRX1F1: ODDRX1F
+ port map (SCLK=>sclk_t, RST=>reset, D0=>da1, D1=>db1,
+ Q=>buf_douto1);
+
+ Inst4_ODDRX1F0: ODDRX1F
+ port map (SCLK=>sclk_t, RST=>reset, D0=>da0, D1=>db0,
+ Q=>buf_douto0);
+
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ scuba_vhi_inst: VHI
+ port map (Z=>scuba_vhi);
+
+ Inst3_ODDRX1F: ODDRX1F
+ port map (SCLK=>clkos, RST=>reset, D0=>scuba_vhi, D1=>scuba_vlo,
+ Q=>buf_clkout);
+
+ Inst2_OB: OB
+ port map (I=>buf_clkout, O=>clkout);
+
+ Inst1_OB7: OB
+ port map (I=>douto_t7, O=>dout(7));
+
+ Inst1_OB6: OB
+ port map (I=>douto_t6, O=>dout(6));
+
+ Inst1_OB5: OB
+ port map (I=>douto_t5, O=>dout(5));
+
+ Inst1_OB4: OB
+ port map (I=>douto_t4, O=>dout(4));
+
+ Inst1_OB3: OB
+ port map (I=>douto_t3, O=>dout(3));
+
+ Inst1_OB2: OB
+ port map (I=>douto_t2, O=>dout(2));
+
+ Inst1_OB1: OB
+ port map (I=>douto_t1, O=>dout(1));
+
+ Inst1_OB0: OB
+ port map (I=>douto_t0, O=>dout(0));
+
+ udel_douto7: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_douto7, LOADN=>data_loadn(7),
+ MOVE=>data_move(7), DIRECTION=>data_direction(7),
+ Z=>douto_t7, CFLAG=>data_cflag(7));
+
+ udel_douto6: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_douto6, LOADN=>data_loadn(6),
+ MOVE=>data_move(6), DIRECTION=>data_direction(6),
+ Z=>douto_t6, CFLAG=>data_cflag(6));
+
+ udel_douto5: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_douto5, LOADN=>data_loadn(5),
+ MOVE=>data_move(5), DIRECTION=>data_direction(5),
+ Z=>douto_t5, CFLAG=>data_cflag(5));
+
+ udel_douto4: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_douto4, LOADN=>data_loadn(4),
+ MOVE=>data_move(4), DIRECTION=>data_direction(4),
+ Z=>douto_t4, CFLAG=>data_cflag(4));
+
+ udel_douto3: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_douto3, LOADN=>data_loadn(3),
+ MOVE=>data_move(3), DIRECTION=>data_direction(3),
+ Z=>douto_t3, CFLAG=>data_cflag(3));
+
+ udel_douto2: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_douto2, LOADN=>data_loadn(2),
+ MOVE=>data_move(2), DIRECTION=>data_direction(2),
+ Z=>douto_t2, CFLAG=>data_cflag(2));
+
+ udel_douto1: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_douto1, LOADN=>data_loadn(1),
+ MOVE=>data_move(1), DIRECTION=>data_direction(1),
+ Z=>douto_t1, CFLAG=>data_cflag(1));
+
+ udel_douto0: DELAYF
+ generic map (DEL_VALUE=> 1, DEL_MODE=> "USER_DEFINED")
+ port map (A=>buf_douto0, LOADN=>data_loadn(0),
+ MOVE=>data_move(0), DIRECTION=>data_direction(0),
+ Z=>douto_t0, CFLAG=>data_cflag(0));
+
+ db7 <= data(15);
+ da7 <= data(14);
+ db6 <= data(13);
+ da6 <= data(12);
+ db5 <= data(11);
+ da5 <= data(10);
+ db4 <= data(9);
+ da4 <= data(8);
+ db3 <= data(7);
+ da3 <= data(6);
+ db2 <= data(5);
+ da2 <= data(4);
+ db1 <= data(3);
+ da1 <= data(2);
+ db0 <= data(1);
+ da0 <= data(0);
+ sclk_t <= clkop;
+ clkos <= refclk;
+ clkop <= refclk;
+end Structure;
--- /dev/null
+-w
+#-y
+-l 5
+#-m nodelist.txt # Controlled by the compile.pl script.
+#-n 1 # Controlled by the compile.pl script.
+-s 10
+-t 6
+-c 2
+-e 2
+-i 10
+#-exp parPlcInLimit=0
+#-exp parPlcInNeighborSize=1
+#General PAR Command Line Options
+# -w With this option, any files generated will overwrite existing files
+# (e.g., any .par, .pad files).
+# -y Adds the Delay Summary Report in the .par file and creates the delay
+# file (in .dly format) at the end of the par run.
+#
+#PAR Placement Command Line Options
+# -l Specifies the effort level of the design from 1 (simplest designs)
+# to 5 (most complex designs).
+# -m Multi-tasking option. Controlled by the compile.pl script.
+# -n Sets the number of iterations performed at the effort level
+# specified by the -l option. Controlled by the compile.pl script.
+# -s Save the number of best results for this run.
+# -t Start placement at the specified cost table. Default is 1.
+#
+#PAR Routing Command Line Options
+# -c Run number of cost-based cleanup passes of the router.
+# -e Run number of delay-based cleanup passes of the router on
+# completely-routed designs only.
+# -i Run a maximum number of passes, stopping earlier only if the routing
+# goes to 100 percent completion and all constraints are met.
+#
+#PAR Explorer Command Line Options
+# parCDP Enable the congestion-driven placement (CDP) algorithm. CDP is
+# compatible with all Lattice FPGA device families; however, most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M, LatticeECP3, and LatticeXP2 device families.
+# parCDR Enable the congestion-driven router (CDR) algorithm.
+# Congestion-driven options like parCDR and parCDP can improve
+# performance given a design with multiple congestion “hotspots.” The
+# Layer > Congestion option of the Design Planner Floorplan View can
+# help visualize routing congestion. Large congested areas may prevent
+# the options from finding a successful solution.
+# CDR is compatible with all Lattice FPGA device families however most
+# benefit has been demonstrated with benchmarks targeted to ECP5,
+# LatticeECP2/M,LatticeECP3, and LatticeXP2 device families.
+# paruseNBR NBR Router or Negotiation-based routing option. Supports all
+# FPGA device families except LatticeXP and MachXO.
+# When turned on, an alternate routing engine from the traditional
+# Rip-up-based routing selection (RBR) is used. This involves an
+# iterative routing algorithm that routes connections to achieve
+# minimum delay cost. It does so by computing the demand on each
+# routing resource and applying cost values per node. It will
+# complete when an optimal solution is arrived at or the number of
+# iterations is reached.
+# parPathBased Path-based placement option. Path-based timing driven
+# placement will yield better performance and more
+# predictable results in many cases.
+# parHold Additional hold time correction option. This option
+# forces the router to automatically insert extra wires to compensate for the
+# hold time violation.
+# parHoldLimit This option allows you to set a limit on the number of
+# hold time violations to be processed by the auto hold time correction option
+# parHold.
+# parPlcInLimit Cannot find in the online help
+# parPlcInNeighborSize Cannot find in the online help
+-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1
--- /dev/null
+
+#################################################################
+# Basic Settings
+#################################################################
+
+FREQUENCY PORT CLK_200 200 MHz;
+FREQUENCY PORT CLK_125 125 MHz;
+FREQUENCY PORT CLK_EXT 200 MHz;
+
+FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
+FREQUENCY NET "THE_MEDIA_INTERFACE/gen_pcs1.THE_SERDES/serdes_sync_0_inst/clk_tx_full" 200 MHz;
+# FREQUENCY NET "med_stat_debug[11]" 200 MHz;
+
+FREQUENCY NET "med2int_0.clk_full" 200 MHz;
+# FREQUENCY NET THE_MEDIA_INTERFACE/clk_rx_full 200 MHz;
+
+
+BLOCK PATH TO PORT "LED*";
+BLOCK PATH TO PORT "PROGRAMN";
+BLOCK PATH TO PORT "TEMP_LINE";
+BLOCK PATH FROM PORT "TEMP_LINE";
+BLOCK PATH TO PORT "TEST_LINE*";
+
+#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns;
+#MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns;
+#MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
+MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns;
+
+MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns;
+MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns;
+
+GSR_NET NET "clear_i";
+
+# LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ;
+
+
+REGION "MEDIA" "R81C44D" 13 25;
+LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA" ;
+
+
+BLOCK NET "THE_MIMOSIS/THE_IN/reset_i";
+BLOCK NET "THE_MIMOSIS/THE_WORDS/reset_i";
+MULTICYCLE FROM CELL "THE_MIMOSIS/THE_IN/PROC_REGS.add_re*" 20 ns;
+MULTICYCLE FROM CELL "THE_MIMOSIS/THE_IN/add_re*" 20 ns;
+MULTICYCLE FROM CELL "THE_MIMOSIS/THE_WORDS/CONF*" 20 ns;
+MULTICYCLE FROM CELL "THE_MIMOSIS/THE_WORDS/PROC_REGS.control_re*" 20 ns;
+
+BLOCK PATH TO CELL "THE_MIMOSIS/THE_IN/PROC_REGS.BUS_TX.dat*";
+BLOCK PATH TO CELL "THE_MIMOSIS/THE_WORDS/PROC_REGS.BUS_TX.dat*";
--- /dev/null
+
+# implementation: "workdir"
+impl -add workdir -type fpga
+
+# device options
+set_option -technology ECP5UM
+set_option -part LFE5UM_85F
+set_option -package BG756C
+set_option -speed_grade -8
+set_option -part_companion ""
+
+# compilation/mapping options
+set_option -default_enum_encoding sequential
+set_option -symbolic_fsm_compiler 1
+set_option -top_module "trb5sc_mimosis"
+set_option -resource_sharing false
+set_option -vhdl2008 true
+
+# map options
+set_option -frequency 120
+set_option -fanout_limit 100
+set_option -disable_io_insertion 0
+set_option -retiming 1
+set_option -pipe 1
+set_option -forcegsr false
+set_option -fixgatedclocks 3
+set_option -fixgeneratedclocks 3
+set_option -compiler_compatible true
+set_option -multi_file_compilation_unit 1
+
+set_option -max_parallel_jobs 3
+#set_option -automatic_compile_point 1
+#set_option -continue_on_error 1
+set_option -resolve_multiple_driver 1
+
+# simulation options
+set_option -write_verilog 0
+set_option -write_vhdl 1
+
+# automatic place and route (vendor) options
+set_option -write_apr_constraint 0
+
+# set result format/file last
+project -result_format "edif"
+project -result_file "workdir/trb5sc_mimosis.edf"
+set_option log_file "workdir/trb5sc_project.srf"
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+impl -active "workdir"
+
+####################
+
+add_file -vhdl -lib work "workdir/lattice-diamond/cae_library/synthesis/vhdl/ecp5um.vhd"
+
+#Packages
+add_file -vhdl -lib work "workdir/version.vhd"
+add_file -vhdl -lib work "config.vhd"
+add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
+
+#Basic Infrastructure
+add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd"
+add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd"
+
+
+#Fifos
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net16_fifo_arch.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/RAM/spi_dpram_32_to_8/spi_dpram_32_to_8.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x1k/lattice_ecp5_fifo_18x1k.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16bit_dualport/lattice_ecp5_fifo_16bit_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/trb_net_fifo_16bit_bram_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x256_oreg/fifo_36x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x512_oreg/fifo_36x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x1k_oreg/fifo_36x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x2k_oreg/fifo_36x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x4k_oreg/fifo_36x4k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x8k_oreg/fifo_36x8k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x16k_oreg/fifo_36x16k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_36x32k_oreg/fifo_36x32k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x256_oreg/fifo_18x256_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x512_oreg/fifo_18x512_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x1k_oreg/fifo_18x1k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_18x2k_oreg/fifo_18x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_9x2k_oreg/fifo_9x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/fifo_19x16_obuf/fifo_19x16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_16x16_dualport/lattice_ecp5_fifo_16x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_18x16_dualport/lattice_ecp5_fifo_18x16_dualport.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp3_fifo_18x16_dualport_oreg/lattice_ecp3_fifo_18x16_dualport_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/lattice/ecp5/FIFO/lattice_ecp5_fifo_36x16_dualport_oreg/lattice_ecp5_fifo_36x16_dualport_oreg.vhd"
+
+
+#Flash & Reload, Tools
+add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/common_i2c.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
+add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd"
+add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_19x8_preset.vhd"
+add_file -vhdl -lib work "../../trb3sc/code/adc_controller.vhd"
+
+#SlowControl files
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd"
+
+#Media interface
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd"
+
+
+#########################################
+#channel 0, backplane
+#add_file -vhdl -lib work "../../dirich/cores/serdes_sync_0.vhd"
+#add_file -verilog -lib work "../../dirich/cores/serdes_sync_0_softlogic.v"
+
+#channel 1, SFP
+#add_file -vhdl -lib work "../cores/serdes_sync_0/serdes_sync_0.vhd"
+#add_file -verilog -lib work "../cores/serdes_sync_0/serdes_sync_0_softlogic.v"
+##########################################
+
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd"
+add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v"
+
+
+#TrbNet Endpoint
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd"
+add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd"
+add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd"
+add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
+
+add_file -vhdl -lib work "../../trbnet/special/trb_net_i2cwire.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim.vhd"
+
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_gstart2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_sendb2.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/i2c_slim2.vhd"
+
+add_file -vhdl -lib work "./cores/mimosis_inp.vhd"
+add_file -vhdl -lib work "./cores/testout.vhd"
+add_file -vhdl -lib work "./code/MimosisInput.vhd"
+add_file -vhdl -lib work "./code/InputStage.vhd"
+add_file -vhdl -lib work "./code/WordAlign.vhd"
+add_file -vhdl -lib work "./cores/pll_200_160/pll_200_160.vhd"
+
+
+
+#GbE
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/base/gbe_med_interface_single.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd"
+add_file -verilog -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/serdes_gbe_softlogic.v"
+# Choose your SerDes location here
+#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch0/serdes_gbe.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d0ch1/serdes_gbe.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch0/serdes_gbe.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp5/media/ecp5/d1ch1/serdes_gbe.vhd"
+
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4096x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x32x8.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_512x72.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx16x8_mb2.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2048x8x16.vhd"
+#add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_65536x18x9.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/ip_mem.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_32kx18x9_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_64kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_8kx9_af_cnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_2kx9x18_wcnt.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp5/fifo_4kx18x9_wcnt.vhd"
+
+
+
+
+
+
+
+
+
+add_file -vhdl -lib work "./trb5sc_mimosis.vhd"
+#add_file -fpga_constraint "./synplify.fdc"
+
+
+
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.version.all;\r
+use work.config.all;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.trb3_components.all;\r
+use work.med_sync_define.all;\r
+\r
+entity trb5sc_mimosis is\r
+ port(\r
+ CLK_200 : in std_logic;\r
+ CLK_125 : in std_logic;\r
+ CLK_EXT : in std_logic;\r
+\r
+ TRIG_IN_BACKPL : in std_logic; --Reference Time\r
+ TRIG_IN_RJ45 : in std_logic; --Reference Time\r
+ IN_SELECT_EXT_CLOCK : in std_logic;\r
+\r
+ SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3\r
+ BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1\r
+\r
+ SFP_TX_DIS : out std_logic;\r
+ SFP_LOS : in std_logic;\r
+ SFP_MOD_0 : in std_logic;\r
+\r
+ --AddOn\r
+ --FE_GPIO : inout std_logic_vector(11 downto 0);\r
+ --FE_CLK : out std_logic_vector( 2 downto 1);\r
+ --FE_DIFF : inout std_logic_vector(63 downto 0);\r
+ --INP : inout std_logic_vector(63 downto 0);\r
+ --LED_ADDON : out std_logic_vector(5 downto 0);\r
+ LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0);\r
+ LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0);\r
+ LED_ADDON_RJ : out std_logic_vector(1 downto 0);\r
+ SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0);\r
+ SFP_ADDON_LOS : in std_logic_vector(1 downto 0);\r
+\r
+ RJ : inout std_logic_vector(3 downto 0);\r
+ H1 : inout std_logic_vector(4 downto 0);\r
+ H2 : inout std_logic_vector(4 downto 0);\r
+ H3 : inout std_logic_vector(4 downto 0);\r
+ H4 : inout std_logic_vector(4 downto 0);\r
+ H5 : inout std_logic_vector(3 downto 0);\r
+ H6 : inout std_logic_vector(4 downto 0);\r
+ H7 : inout std_logic_vector(4 downto 0);\r
+\r
+ PIN : out std_logic_vector(8 downto 1);\r
+\r
+ MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic;\r
+\r
+ --ADC\r
+ ADC_SCLK : out std_logic;\r
+ ADC_NCS : out std_logic;\r
+ ADC_MOSI : out std_logic;\r
+ ADC_MISO : in std_logic;\r
+ --Flash, Reload\r
+ FLASH_SCLK : out std_logic;\r
+ FLASH_NCS : out std_logic;\r
+ FLASH_MOSI : out std_logic;\r
+ FLASH_MISO : in std_logic;\r
+ FLASH_HOLD : out std_logic;\r
+ FLASH_WP : out std_logic;\r
+ PROGRAMN : out std_logic;\r
+ --I2C\r
+ I2C_SDA : inout std_logic;\r
+ I2C_SCL : inout std_logic;\r
+ TMP_ALERT : in std_logic;\r
+\r
+ --GBTSCA\r
+ SCA_RX : in std_logic(1 downto 0);\r
+ SCA_TX : out std_logic(1 downto 0);\r
+ SCA_CLK : out std_logic(1 downto 0);\r
+\r
+ --LED\r
+ LED : out std_logic_vector(8 downto 1);\r
+ LED_SFP_YELLOW : out std_logic;\r
+ LED_SFP_GREEN : out std_logic;\r
+ LED_SFP_RED : out std_logic;\r
+ LED_RJ_GREEN : out std_logic_vector(1 downto 0);\r
+ LED_RJ_RED : out std_logic_vector(1 downto 0);\r
+ LED_EXT_CLOCK : out std_logic;\r
+\r
+ --Other Connectors\r
+ TEST : inout std_logic_vector(14 downto 1); --on v1 only\r
+ --COMMON_SDA, COMMON_SCL : inout std_logic\r
+ HDR_IO : inout std_logic_vector(15 downto 0) --23..16 on v2 only\r
+ );\r
+\r
+ attribute syn_useioff : boolean;\r
+ attribute syn_useioff of FLASH_NCS : signal is true;\r
+ attribute syn_useioff of FLASH_SCLK : signal is true;\r
+ attribute syn_useioff of FLASH_MOSI : signal is true;\r
+ attribute syn_useioff of FLASH_MISO : signal is true;\r
+\r
+end entity;\r
+\r
+\r
+architecture arch of trb5sc_mimosis is\r
+\r
+ attribute syn_keep : boolean;\r
+ attribute syn_preserve : boolean;\r
+\r
+ signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320, clk_40 : std_logic;\r
+ signal GSR_N : std_logic;\r
+ signal reset_i : std_logic;\r
+ signal clear_i : std_logic;\r
+ signal trigger_in_i : std_logic;\r
+\r
+ attribute syn_keep of GSR_N : signal is true;\r
+ attribute syn_preserve of GSR_N : signal is true;\r
+\r
+ signal debug_clock_reset : std_logic_vector(31 downto 0);\r
+ signal external_clock_lock : std_logic := '0';\r
+ signal debug_tools : std_logic_vector(31 downto 0);\r
+\r
+ --Media Interface\r
+ signal med2int : med2int_array_t(0 to 0);\r
+ signal int2med : int2med_array_t(0 to 0);\r
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);\r
+ signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic;\r
+\r
+\r
+ signal readout_rx : READOUT_RX;\r
+ signal readout_tx : readout_tx_array_t(0 to 0);\r
+\r
+ signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx, busgbtsca_tx, busgbeip_tx, busgbereg_tx, busfwd_tx : CTRLBUS_TX;\r
+ signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx, busgbtsca_rx, busgbeip_rx, busgbereg_rx, busfwd_rx : CTRLBUS_RX;\r
+\r
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+\r
+ signal sed_error_i : std_logic;\r
+ signal clock_select : std_logic;\r
+ signal bus_master_active : std_logic;\r
+ signal flash_ncs_i : std_logic;\r
+\r
+ signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);\r
+ signal header_io_i : std_logic_vector(10 downto 1);\r
+ signal timer : TIMERS;\r
+ signal add_reg : std_logic_vector(31 downto 0);\r
+ alias led_off : std_logic is add_reg(0);\r
+\r
+ signal out_data : std_logic_vector(15 downto 0);\r
+ signal out_i : std_logic_vector( 7 downto 0);\r
+ signal inp_i : std_logic_vector( 7 downto 0);\r
+ signal gbe_status : std_logic_vector(15 downto 0);\r
+\r
+\r
+ signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0);\r
+ signal i2c_reg_2 : std_logic_vector(31 downto 0);\r
+ signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0);\r
+ signal mimosis_scl_drv, mimosis_sda_drv : std_logic;\r
+ signal i2c_go_100, i2c_go : std_logic;\r
+ signal i2c_reg_5_40 : std_logic_vector(31 downto 0);\r
+ signal counter : unsigned(23 downto 0);\r
+\r
+ --signal fwd_dst_mac : std_logic_vector(47 downto 0);\r
+ --signal fwd_dst_ip : std_logic_vector(31 downto 0);\r
+ --signal fwd_dst_port : std_logic_vector(15 downto 0);\r
+ --signal fwd_data : std_logic_vector(7 downto 0);\r
+ --signal fwd_datavalid : std_logic;\r
+ --signal fwd_sop : std_logic;\r
+ --signal fwd_eop : std_logic;\r
+ --signal fwd_ready : std_logic;\r
+ --signal fwd_full : std_logic;\r
+ --signal fwd_length : std_logic_vector(15 downto 0);\r
+ --signal fwd_do_send : std_logic;\r
+\r
+ -- -- GBTSCA\r
+ -- -- Clock & reset\r
+ -- signal gbtsc_tx_clk_i : in std_logic; --! Tx clock (Tx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency\r
+ -- signal gbtsc_tx_clk_en : in std_logic := '1'; --! Tx clock enable signal must be used in case of multi-cycle path(tx_clk_i > LHC frequency). By default: always enabled\r
+ -- signal gbtsc_rx_clk_i : in std_logic; --! Rx clock (Rx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency\r
+ -- signal gbtsc_rx_clk_en : in std_logic := '1'; --! Rx clock enable signal must be used in case of multi-cycle path(rx_clk_i > LHC frequency). By default: always enabled\r
+ -- signal gbtsc_rx_reset_i : in std_logic; --! Reset RX datapath\r
+ -- signal gbtsc_tx_reset_i : in std_logic; --! Reset TX datapath\r
+ -- -- IC control\r
+ -- signal gbtsc_tx_start_write_i : in std_logic; --! Request a write config. to the GBTx (IC)\r
+ -- signal gbtsc_tx_start_read_i : in std_logic; --! Request a read config. to the GBTx (IC)\r
+ -- -- IC configuration\r
+ -- signal gbtsc_tx_GBTx_address_i : in std_logic_vector(7 downto 0); --! I2C address of the GBTx\r
+ -- signal gbtsc_tx_register_addr_i : in std_logic_vector(15 downto 0); --! Address of the first register to be accessed\r
+ -- signal gbtsc_tx_nb_to_be_read_i : in std_logic_vector(15 downto 0); --! Number of words/bytes to be read (only for read transactions)\r
+ -- -- IC FIFO control\r
+ -- signal gbtsc_wr_clk_i : in std_logic; --! Fifo's writing clock\r
+ -- signal gbtsc_tx_wr_i : in std_logic; --! Request a write operation into the internal FIFO (Data to GBTx)\r
+ -- signal gbtsc_tx_data_to_gbtx_i : in std_logic_vector(7 downto 0); --! Data to be written into the internal FIFO\r
+ -- signal gbtsc_rd_clk_i : in std_logic;\r
+ -- signal gbtsc_rx_rd_i : in std_logic; --! Request a read operation of the internal FIFO (GBTx reply)\r
+ -- signal gbtsc_rx_data_from_gbtx_o : out std_logic_vector(7 downto 0); --! Data from the FIFO\r
+ -- -- IC Status\r
+ -- signal gbtsc_tx_ready_o : out std_logic; --! IC core ready for a transaction\r
+ -- signal gbtsc_rx_empty_o : out std_logic; --! Rx FIFO is empty (no reply from GBTx)\r
+ -- -- SCA control\r
+ -- signal gbtsc_sca_enable_i : in std_logic_vector((g_SCA_COUNT-1) downto 0); --! Enable flag to select SCAs\r
+ -- signal gbtsc_start_reset_cmd_i : in std_logic; --! Send a reset command to the enabled SCAs\r
+ -- signal gbtsc_start_connect_cmd_i : in std_logic; --! Send a connect command to the enabled SCAs\r
+ -- signal gbtsc_start_command_i : in std_logic; --! Send the command set in input to the enabled SCAs\r
+ -- signal gbtsc_inject_crc_error : in std_logic; --! Emulate a CRC error\r
+ -- -- SCA command\r
+ -- signal gbtsc_tx_address_i : in std_logic_vector(7 downto 0); --! Command: address field (According to the SCA manual)\r
+ -- signal gbtsc_tx_transID_i : in std_logic_vector(7 downto 0); --! Command: transaction ID field (According to the SCA manual)\r
+ -- signal gbtsc_tx_channel_i : in std_logic_vector(7 downto 0); --! Command: channel field (According to the SCA manual)\r
+ -- signal gbtsc_tx_command_i : in std_logic_vector(7 downto 0); --! Command: command field (According to the SCA manual)\r
+ -- signal gbtsc_tx_data_i : in std_logic_vector(31 downto 0); --! Command: data field (According to the SCA manual)\r
+ -- signal gbtsc_rx_received_o : out std_logic_vector((g_SCA_COUNT-1) downto 0); --! Reply received flag (pulse)\r
+ -- signal gbtsc_rx_address_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: address field (According to the SCA manual)\r
+ -- signal gbtsc_rx_control_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: control field (According to the SCA manual)\r
+ -- signal gbtsc_rx_transID_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: transaction ID field (According to the SCA manual)\r
+ -- signal gbtsc_rx_channel_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: channel field (According to the SCA manual)\r
+ -- signal gbtsc_rx_len_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: len field (According to the SCA manual)\r
+ -- signal gbtsc_rx_error_o : out reg8_arr((g_SCA_COUNT-1) downto 0); --! Reply: error field (According to the SCA manual)\r
+ -- signal gbtsc_rx_data_o : out reg32_arr((g_SCA_COUNT-1) downto 0); --! Reply: data field (According to the SCA manual)\r
+ -- -- EC line\r
+ -- signal gbtsc_ec_data_o : out reg2_arr((g_SCA_COUNT-1) downto 0); --! (TX) Array of bits to be mapped to the TX GBT-Frame\r
+ -- signal gbtsc_ec_data_i : in reg2_arr((g_SCA_COUNT-1) downto 0); --! (RX) Array of bits to be mapped to the RX GBT-Frame\r
+ -- -- IC lines\r
+ -- signal gbtsc_ic_data_o : out std_logic_vector(1 downto 0); --! (TX) Array of bits to be mapped to the TX GBT-Frame (bits 83/84)\r
+ -- signal gbtsc_ic_data_i : in std_logic_vector(1 downto 0) --! (RX) Array of bits to be mapped to the RX GBT-Frame (bits 83/84)\r
+\r
+\r
+ -- GBT-SCA\r
+ variable g_SCA_COUNT : integer := 1;\r
+ signal sca_clk : std_logic; --! Rx clock (Rx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency\r
+ signal sca_reset_i : std_logic := '0'; --! Reset RX datapath\r
+\r
+ signal sca_enable_i : std_logic := '0'; --! Enable flag, bit position correspond to the SCA ID ('1': enabled / '0': Disabled)\r
+ signal sca_start_reset_cmd_i : std_logic; --! Send a reset command to the enabled SCAs\r
+ signal sca_start_connect_cmd_i : std_logic; --! Send a connect command to the enabled SCAs\r
+ signal sca_start_command_i : std_logic; --! Send the command set in input to the enabled SCAs\r
+\r
+ signal sca_tx_address_i : std_logic_vector(7 downto 0); --! Command: address field (According to the SCA manual)\r
+ signal sca_tx_transID_i : std_logic_vector(7 downto 0); --! Command: transaction ID field (According to the SCA manual)\r
+ signal sca_tx_channel_i : std_logic_vector(7 downto 0); --! Command: channel field (According to the SCA manual)\r
+ signal sca_tx_len_i : std_logic_vector(7 downto 0); --! Command: Len field (not used anymore, fixed to 4 bytes)\r
+ signal sca_tx_command_i : std_logic_vector(7 downto 0); --! Command: command field (According to the SCA manual)\r
+ signal sca_tx_data_i : std_logic_vector(31 downto 0); --! Command: data field (According to the SCA manual)\r
+\r
+ signal sca_rx_received_o : std_logic; --! Reply received flag (pulse), bit position correspond to the SCA ID\r
+ signal sca_rx_address_o : std_logic_vector(7 downto 0); --! Reply: address field (According to the SCA manual)\r
+ signal sca_rx_control_o : std_logic_vector(7 downto 0); --! Reply: control field (According to the SCA manual)\r
+ signal sca_rx_transID_o : std_logic_vector(7 downto 0); --! Reply: transaction ID field (According to the SCA manual)\r
+ signal sca_rx_channel_o : std_logic_vector(7 downto 0); --! Reply: channel field (According to the SCA manual)\r
+ signal sca_rx_len_o : std_logic_vector(7 downto 0); --! Reply: len field (According to the SCA manual)\r
+ signal sca_rx_error_o : std_logic_vector(7 downto 0); --! Reply: error field (According to the SCA manual)\r
+ signal sca_rx_data_o : std_logic_vector(31 downto 0); --! Reply: data field (According to the SCA manual)\r
+\r
+ signal sca_out : std_logic_vector(1 downto 0); --! (TX) Array of 2 bits to be mapped to the TX GBT-Frame\r
+ signal sca_in : std_logic_vector(1 downto 0); --! (RX) Array of 2 bits to be mapped to the RX GBT-Frame\r
+\r
+ signal shiftreg2 : std_logic_vector(1 downto 0) := "00";\r
+\r
+begin\r
+\r
+\r
+trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK);\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Clock & Reset Handling\r
+---------------------------------------------------------------------------\r
+ THE_CLOCK_RESET : entity work.clock_reset_handler\r
+ port map(\r
+ CLOCK_IN => CLK_200,\r
+ RESET_FROM_NET => med2int(0).stat_op(13),\r
+ SEND_RESET_IN => med2int(0).stat_op(15),\r
+\r
+ BUS_RX => bustc_rx,\r
+ BUS_TX => bustc_tx,\r
+\r
+ RESET_OUT => reset_i,\r
+ CLEAR_OUT => clear_i,\r
+ GSR_OUT => GSR_N,\r
+\r
+ REF_CLK_OUT => clk_full,\r
+ SYS_CLK_OUT => clk_sys,\r
+ RAW_CLK_OUT => clk_full_osc,\r
+\r
+ DEBUG_OUT => debug_clock_reset\r
+ );\r
+\r
+THE_160_PLL : entity work.pll_200_160\r
+ port map(\r
+ CLKI => clk_full_osc,\r
+ CLKOP => clk_160,\r
+ CLKOS => clk_320,\r
+ CLKOS2=> clk_40\r
+ );\r
+\r
+H5(3) <= clk_320;\r
+RJ(0) <= clk_40;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- TrbNet Uplink\r
+---------------------------------------------------------------------------\r
+\r
+ THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync\r
+ generic map(\r
+ SERDES_NUM => SERDES_NUM,\r
+ USE_NEW_ECP5_RESET => 0,\r
+ IS_SYNC_SLAVE => c_YES\r
+ )\r
+ port map(\r
+ CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full,\r
+ CLK_INTERNAL_FULL => clk_full_osc,\r
+ SYSCLK => clk_sys,\r
+ RESET => reset_i,\r
+ CLEAR => clear_i,\r
+ --Internal Connection\r
+ MEDIA_MED2INT => med2int(0),\r
+ MEDIA_INT2MED => int2med(0),\r
+\r
+ --Sync operation\r
+ RX_DLM => open,\r
+ RX_DLM_WORD => open,\r
+ TX_DLM => open,\r
+ TX_DLM_WORD => open,\r
+\r
+ --SFP Connection\r
+ SD_PRSNT_N_IN => sfp_prsnt_i,\r
+ SD_LOS_IN => sfp_los_i,\r
+ SD_TXDIS_OUT => sfp_txdis_i,\r
+ --Control Interface\r
+ BUS_RX => bussci_rx,\r
+ BUS_TX => bussci_tx,\r
+ -- Status and control port\r
+ STAT_DEBUG => med_stat_debug(63 downto 0),\r
+ CTRL_DEBUG => open\r
+ );\r
+\r
+ gen_sfp_con : if SERDES_NUM = 1 generate\r
+ sfp_los_i <= SFP_LOS;\r
+ sfp_prsnt_i <= SFP_MOD_0;\r
+ SFP_TX_DIS <= sfp_txdis_i;\r
+ end generate;\r
+ gen_bpl_con : if SERDES_NUM = 0 generate\r
+ sfp_los_i <= BACK_GPIO(1);\r
+ sfp_prsnt_i <= BACK_GPIO(1);\r
+ BACK_GPIO(0) <= sfp_txdis_i;\r
+ end generate;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Endpoint\r
+---------------------------------------------------------------------------\r
+ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record\r
+ generic map (\r
+ ADDRESS_MASK => x"FFFF",\r
+ BROADCAST_BITMASK => BROADCAST_BITMASK,\r
+ REGIO_INIT_ENDPOINT_ID => x"0001",\r
+ REGIO_USE_1WIRE_INTERFACE => c_I2C,\r
+ TIMING_TRIGGER_RAW => c_YES,\r
+ --Configure data handler\r
+ DATA_INTERFACE_NUMBER => 1,\r
+ DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,\r
+ DATA_BUFFER_WIDTH => 32,\r
+ DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,\r
+ TRG_RELEASE_AFTER_DATA => c_YES,\r
+ HEADER_BUFFER_DEPTH => 9,\r
+ HEADER_BUFFER_FULL_THRESH => 2**9-16,\r
+ USE_GBE => USE_GBE\r
+ )\r
+\r
+ port map(\r
+ -- Misc\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+ CLK_125 => CLK_125,\r
+ CLEAR_N => GSR_N,\r
+\r
+ -- Media direction port\r
+ MEDIA_MED2INT => med2int(0),\r
+ MEDIA_INT2MED => int2med(0),\r
+\r
+ --Timing trigger in\r
+ TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i,\r
+\r
+ READOUT_RX => readout_rx,\r
+ READOUT_TX => readout_tx,\r
+\r
+ --Slow Control Port\r
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00\r
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20\r
+ BUS_RX => ctrlbus_rx,\r
+ BUS_TX => ctrlbus_tx,\r
+ BUS_MASTER_IN => bus_master_in,\r
+ BUS_MASTER_OUT => bus_master_out,\r
+ BUS_MASTER_ACTIVE => bus_master_active,\r
+\r
+ ONEWIRE_INOUT => open,\r
+ I2C_SCL => I2C_SCL,\r
+ I2C_SDA => I2C_SDA,\r
+ --Timing registers\r
+ TIMERS_OUT => timer,\r
+ STATUS_GBE_OUT=> gbe_status\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Bus Handler\r
+---------------------------------------------------------------------------\r
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record\r
+ generic map(\r
+ PORT_NUMBER => 5,\r
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", 5 => x"8100", 6 => x"8300", 7 => x"8400", others => x"0000"),\r
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, 5 => 8, 6 => 8, 7 => 8, others => 0),\r
+ PORT_MASK_ENABLE => 1\r
+ )\r
+ port map(\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+\r
+ REGIO_RX => ctrlbus_rx,\r
+ REGIO_TX => ctrlbus_tx,\r
+\r
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED\r
+ BUS_RX(1) => bussci_rx, --SCI Serdes\r
+ BUS_RX(2) => bustc_rx, --Clock switch\r
+ BUS_RX(3) => busmimosis_rx,\r
+ BUS_RX(4) => busgbtsca_rx,\r
+ -- BUS_RX(4) => busi2c_rx,\r
+ -- BUS_RX(5) => busgbeip_rx,\r
+ -- BUS_RX(6) => busgbereg_rx,\r
+ -- BUS_RX(7) => busfwd_rx,\r
+ BUS_TX(0) => bustools_tx,\r
+ BUS_TX(1) => bussci_tx,\r
+ BUS_TX(2) => bustc_tx,\r
+ BUS_TX(3) => busmimosis_tx,\r
+ BUS_TX(4) => busgbtsca_tx,\r
+ -- BUS_TX(4) => busi2c_tx,\r
+ -- BUS_TX(5) => busgbeip_tx,\r
+ -- BUS_TX(6) => busgbereg_tx,\r
+ -- BUS_TX(7) => busfwd_tx,\r
+ STAT_DEBUG => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Control Tools\r
+---------------------------------------------------------------------------\r
+ THE_TOOLS : entity work.trb3sc_tools\r
+ generic map(\r
+ ADC_CMD_1 => x"2c3cb",\r
+ ADC_CMD_2 => x"1d5cb",\r
+ ADC_CMD_3 => x"1e3cb",\r
+ ADC_CMD_4 => x"2f5cb",\r
+ ADC_CMD_T => x"1F393"\r
+ )\r
+ port map(\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+\r
+ --Flash & Reload\r
+ FLASH_CS => flash_ncs_i,\r
+ FLASH_CLK => FLASH_SCLK,\r
+ FLASH_IN => FLASH_MISO,\r
+ FLASH_OUT => FLASH_MOSI,\r
+ PROGRAMN => PROGRAMN,\r
+ REBOOT_IN => common_ctrl_reg(15),\r
+ --SPI\r
+ SPI_CS_OUT => spi_cs,\r
+ SPI_MOSI_OUT => spi_mosi,\r
+ SPI_MISO_IN => spi_miso,\r
+ SPI_CLK_OUT => spi_clk,\r
+ --Header\r
+ --HEADER_IO => open,\r
+ HEADER_IO(7) => HDR_IO(6),\r
+ HEADER_IO(8) => HDR_IO(7),\r
+ ADDITIONAL_REG => add_reg,\r
+ --ADC\r
+ ADC_CS => ADC_NCS,\r
+ ADC_MOSI => ADC_MOSI,\r
+ ADC_MISO => ADC_MISO,\r
+ ADC_CLK => ADC_SCLK,\r
+ --Trigger & Monitor\r
+ MONITOR_INPUTS => (others => '0'),\r
+ TRIG_GEN_INPUTS => (others => '0'),\r
+ TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2),\r
+ TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0),\r
+ --SED\r
+ SED_ERROR_OUT => sed_error_i,\r
+ --Slowcontrol\r
+ BUS_RX => bustools_rx,\r
+ BUS_TX => bustools_tx,\r
+ --Control master for default settings\r
+ BUS_MASTER_IN => bus_master_in,\r
+ BUS_MASTER_OUT => bus_master_out,\r
+ BUS_MASTER_ACTIVE => bus_master_active,\r
+ DEBUG_OUT => debug_tools\r
+ );\r
+\r
+--counter <= counter + '1' when rising_edge(clk_sys);\r
+--HDR_IO <= std_logic_vector(counter(15 downto 0));\r
+--LED <= std_logic_vector(counter(23 downto 16));\r
+\r
+ --COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z';\r
+ --COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z';\r
+\r
+ FLASH_HOLD <= '1';\r
+ FLASH_WP <= '1';\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- GBT-SCA\r
+---------------------------------------------------------------------------\r
+-- THE_GBTSCA : entity work.gbtsc_top\r
+-- generic map(\r
+-- -- IC configuration\r
+-- -- g_IC_FIFO_DEPTH => , -- : integer := 20; --! Defines the depth of the FIFO used to handle the Internal control (Max. number of words/bytes can be read/write from/to a GBTx)\r
+-- -- g_ToLpGBT => , -- : integer range 0 to 1 := 0; --! 1 to use LpGBT. Otherwise, it should be 0\r
+-- -- g_LPGBT_VERS => , -- : std_logic := '1'; --! Select lpGBT version ('0': 0, '1': 1)\r
+\r
+-- -- EC configuration\r
+-- g_SCA_COUNT => 1, -- : integer := 1 --! Defines the maximum number of SCA that can be connected to this module\r
+-- )\r
+-- port map(\r
+-- -- Clock & reset\r
+-- tx_clk_i => gbtsc_tx_clk_i, --! Tx clock (Tx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency\r
+-- tx_clk_en => gbtsc_tx_clk_e, --! Tx clock enable signal must be used in case of multi-cycle path(tx_clk_i > LHC frequency). By default: always enabled\r
+\r
+-- rx_clk_i => gbtsc_rx_clk_i, --! Rx clock (Rx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency\r
+-- rx_clk_en => gbtsc_rx_clk_e, --! Rx clock enable signal must be used in case of multi-cycle path(rx_clk_i > LHC frequency). By default: always enabled\r
+\r
+-- rx_reset_i => gbtsc_rx_reset_i, --! Reset RX datapath\r
+-- tx_reset_i => gbtsc_tx_reset_i, --! Reset TX datapath\r
+\r
+-- -- IC control\r
+-- tx_start_write_i => gbtsc_tx_start_write_i, --! Request a write config. to the GBTx (IC)\r
+-- tx_start_read_i => gbtsc_tx_start_read_i, --! Request a read config. to the GBTx (IC)\r
+\r
+-- -- IC configuration\r
+-- tx_GBTx_address_i => gbtsc_tx_GBTx_address_i, --! I2C address of the GBTx\r
+-- tx_register_addr_i => gbtsc_tx_register_addr_i, --! Address of the first register to be accessed\r
+-- tx_nb_to_be_read_i => gbtsc_tx_nb_to_be_read_i, --! Number of words/bytes to be read (only for read transactions)\r
+\r
+-- -- IC FIFO control\r
+-- wr_clk_i => gbtsc_wr_clk_i, --! Fifo's writing clock\r
+-- tx_wr_i => gbtsc_tx_wr_i, --! Request a write operation into the internal FIFO (Data to GBTx)\r
+-- tx_data_to_gbtx_i => gbtsc_tx_data_to_gbtx_i, --! Data to be written into the internal FIFO\r
+\r
+-- rd_clk_i => gbtsc_rd_clk_i, --\r
+-- rx_rd_i => gbtsc_rx_rd_i, --! Request a read operation of the internal FIFO (GBTx reply)\r
+-- rx_data_from_gbtx_o => gbtsc_rx_data_from_gbtx_o, --! Data from the FIFO\r
+\r
+-- -- IC Status\r
+-- tx_ready_o => gbtsc_tx_ready_o, --! IC core ready for a transaction\r
+-- rx_empty_o => gbtsc_rx_empty_o, --! Rx FIFO is empty (no reply from GBTx)\r
+\r
+-- -- SCA control\r
+-- sca_enable_i => gbtsc_sca_enable_i, --! Enable flag to select SCAs\r
+-- start_reset_cmd_i => gbtsc_start_reset_cmd_i, --! Send a reset command to the enabled SCAs\r
+-- start_connect_cmd_i => gbtsc_start_connect_cmd_i, --! Send a connect command to the enabled SCAs\r
+-- start_command_i => gbtsc_start_command_i, --! Send the command set in input to the enabled SCAs\r
+-- inject_crc_error => gbtsc_inject_crc_e, --! Emulate a CRC error\r
+\r
+-- -- SCA command\r
+-- tx_address_i => gbtsc_tx_address_i, --! Command: address field (According to the SCA manual)\r
+-- tx_transID_i => gbtsc_tx_transID_i, --! Command: transaction ID field (According to the SCA manual)\r
+-- tx_channel_i => gbtsc_tx_channel_i, --! Command: channel field (According to the SCA manual)\r
+-- tx_command_i => gbtsc_tx_command_i, --! Command: command field (According to the SCA manual)\r
+-- tx_data_i => gbtsc_tx_data_i, --! Command: data field (According to the SCA manual)\r
+\r
+-- rx_received_o => gbtsc_rx_received_o, --! Reply received flag (pulse)\r
+-- rx_address_o => gbtsc_rx_address_o, --! Reply: address field (According to the SCA manual)\r
+-- rx_control_o => gbtsc_rx_control_o, --! Reply: control field (According to the SCA manual)\r
+-- rx_transID_o => gbtsc_rx_transID_o, --! Reply: transaction ID field (According to the SCA manual)\r
+-- rx_channel_o => gbtsc_rx_channel_o, --! Reply: channel field (According to the SCA manual)\r
+-- rx_len_o => gbtsc_rx_len_o, --! Reply: len field (According to the SCA manual)\r
+-- rx_error_o => gbtsc_rx_error_o, --! Reply: error field (According to the SCA manual)\r
+-- rx_data_o => gbtsc_rx_data_o, --! Reply: data field (According to the SCA manual)\r
+\r
+-- -- EC line\r
+-- ec_data_o => gbtsc_ec_data_o, --! (TX) Array of bits to be mapped to the TX GBT-Frame\r
+-- ec_data_i => gbtsc_ec_data_i, --! (RX) Array of bits to be mapped to the RX GBT-Frame\r
+\r
+-- -- IC lines\r
+-- ic_data_o => open, --! (TX) Array of bits to be mapped to the TX GBT-Frame (bits 83/84)\r
+-- ic_data_i => "00" --! (RX) Array of bits to be mapped to the RX GBT-Frame (bits 83/84)\r
+-- );\r
+\r
+\r
+PROC_GEN_CLK80 : process begin\r
+ wait until rising_edge(clk_160);\r
+ sca_clk <= shiftreg2(1);\r
+ shiftreg2 = shiftreg2 + 1;\r
+end process\r
+\r
+THE_GBTSCA : entity work.sca_top\r
+ generic map(\r
+ g_SCA_COUNT => g_SCA_COUNT, --! Number of SCAs to be controlled through the link (up to 41)\r
+ )\r
+ port map(\r
+ rx_clk_en => '1', --! Rx clock enable signal must be used in case of multi-cycle path(rx_clk_i > LHC frequency). By default: always enabled\r
+ tx_clk_en => '1', --! Tx clock enable signal must be used in case of multi-cycle path(tx_clk_i > LHC frequency). By default: always enabled\r
+\r
+ rx_clk_i => sca_clk, --! Rx clock (Rx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency\r
+ tx_clk_i => sca_clk, --! Tx clock (Tx_frameclk_o from GBT-FPGA IP): must be a multiple of the LHC frequency\r
+\r
+ rx_reset_i => sca_reset_i, --! Reset RX datapath\r
+ tx_reset_i => sca_reset_i, --! Reset TX datapath\r
+\r
+ enable_i(0) => sca_enable_i, --! Enable flag, bit position correspond to the SCA ID ('1': enabled / '0': Disabled)\r
+ start_reset_cmd_i => sca_start_reset_cmd_i, --! Send a reset command to the enabled SCAs\r
+ start_connect_cmd_i => sca_start_connect_cmd_i, --! Send a connect command to the enabled SCAs\r
+ start_command_i => sca_start_command_i, --! Send the command set in input to the enabled SCAs\r
+ inject_crc_error => '0', --! Emulate a CRC error\r
+\r
+ tx_address_i => sca_tx_address_i, --! Command: address field (According to the SCA manual)\r
+ tx_transID_i => sca_tx_transID_i, --! Command: transaction ID field (According to the SCA manual)\r
+ tx_channel_i => sca_tx_channel_i, --! Command: channel field (According to the SCA manual)\r
+ tx_len_i => sca_tx_len_i, --! Command: Len field (not used anymore, fixed to 4 bytes)\r
+ tx_command_i => sca_tx_command_i, --! Command: command field (According to the SCA manual)\r
+ tx_data_i => sca_tx_data_i, --! Command: data field (According to the SCA manual)\r
+\r
+ rx_received_o(0) => sca_rx_received_o, --! Reply received flag (pulse), bit position correspond to the SCA ID\r
+ rx_address_o(0) => sca_rx_address_o, --! Reply: address field (According to the SCA manual)\r
+ rx_control_o(0) => sca_rx_control_o, --! Reply: control field (According to the SCA manual)\r
+ rx_transID_o(0) => sca_rx_transID_o, --! Reply: transaction ID field (According to the SCA manual)\r
+ rx_channel_o(0) => sca_rx_channel_o, --! Reply: channel field (According to the SCA manual)\r
+ rx_len_o(0) => sca_rx_len_o, --! Reply: len field (According to the SCA manual)\r
+ rx_error_o(0) => sca_rx_error_o, --! Reply: error field (According to the SCA manual)\r
+ rx_data_o(0) => sca_rx_data_o, --! Reply: data field (According to the SCA manual)\r
+\r
+ tx_data_o(0) => sca_out, --! (TX) Array of 2 bits to be mapped to the TX GBT-Frame\r
+ rx_data_i(0) => sca_in, --! (RX) Array of 2 bits to be mapped to the RX GBT-Frame\r
+ );\r
+\r
+\r
+PROC_GBTSCA_REGS : process begin\r
+ wait until rising_edge(CLK_SYS);\r
+ busgbtsca_tx.ack <= '0';\r
+ busgbtsca_tx.unknown <= '0';\r
+ busgbtsca_tx.nack <= '0';\r
+ busgbtsca_tx.data <= (others => '0');\r
+ sca_enable_i <= '0';\r
+ sca_reset_i <= '0';\r
+\r
+ if busgbtsca_rx.write = '1' then\r
+ busgbtsca_tx.ack <= '1';\r
+ if busgbtsca_rx.addr(3 downto 0) = x"0" then\r
+ sca_tx_address_i <= busgbtsca_rx.data(7 downto 0);\r
+ sca_enable_i <= busgbtsca_rx.data(8);\r
+ sca_start_reset_cmd_i <= busgbtsca_rx.data(9);\r
+ sca_start_connect_i <= busgbtsca_rx.data(10);\r
+ sca_reset_i <= busgbtsca_rx.data(11);\r
+ elsif busgbtsca_rx.addr(3 downto 0) = x"1" then\r
+ sca_tx_transID_i <= busgbtsca_rx.data(7 downto 0);\r
+ sca_tx_channel_i <= busgbtsca_rx.data(15 downto 8);\r
+ sca_tx_len_i <= busgbtsca_rx.data(23 downto 16);\r
+ sca_tx_command_i <= busgbtsca_rx.data(31 downto 24);\r
+ elsif busgbtsca_rx.addr(3 downto 0) = x"2" then\r
+ sca_tx_data_i <= busgbtsca_rx.data(31 downto 0);\r
+ else\r
+ busgbtsca_tx.ack <= '0';\r
+ busgbtsca_tx.unknown <= '1';\r
+ end if;\r
+\r
+ elsif busgbtsca_rx.read = '1' then\r
+ busgbtsca_tx.ack <= '1';\r
+ if busgbtsca_rx.addr(3 downto 0) = x"0" then\r
+ busgbtsca_tx.data(7 downto 0) <= sca_rx_address_o;\r
+ elsif busgbtsca_rx.addr(3 downto 0) = x"1" then\r
+ busgbtsca_tx.data( 7 downto 0 ) <= sca_rx_transID_o;\r
+ busgbtsca_tx.data(15 downto 8 ) <= sca_rx_channel_o;\r
+ busgbtsca_tx.data(23 downto 16) <= sca_rx_len_o;\r
+ -- busgbtsca_tx.data(31 downto 24) <= sca_rx_len_o;\r
+ elsif busgbtsca_rx.addr(3 downto 0) = x"2" then\r
+ busgbtsca_tx.data(31 downto 0) <= sca_rx_data_o;\r
+ elsif busgbtsca_rx.addr(3 downto 0) = x"3" then\r
+ busgbtsca_tx.data(7 downto 0) <= sca_rx_control_o;\r
+ busgbtsca_tx.data(15 downto 8) <= sca_rx_error_o;\r
+ busgbtsca_tx.data(16) <= sca_rx_received_o;\r
+ else\r
+ busgbtsca_tx.ack <= '0';\r
+ busgbtsca_tx.unknown <= '1';\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+sca_in <= SCA_RX;\r
+SCA_TX <= sca_out;\r
+SCA_CLK <= sca_clk & not sca_clk;\r
+\r
+---------------------------------------------------------------------------\r
+-- LED\r
+---------------------------------------------------------------------------\r
+\r
+ LED_SFP_GREEN <= not med2int(0).stat_op(9);\r
+ LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11));\r
+ LED_SFP_YELLOW <= not med2int(0).stat_op(8);\r
+ LED <= x"FF";\r
+ LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used\r
+ LED_RJ_GREEN(0)<= '1' when SERDES_NUM = 0 or led_off = '1' else '0'; --on if SFP is used (next to SFP)\r
+ LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used\r
+ LED_RJ_RED(0) <= '1' when SERDES_NUM = 1 or led_off = '1' else '0'; --on if backplane is used (next to SFP)\r
+ LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used\r
+\r
+ TEST(13 downto 1) <= (others => '0');\r
+ TEST(14) <= flash_ncs_i; --for v1 boards\r
+\r
+ FLASH_NCS <= flash_ncs_i;\r
+\r
+ LED_ADDON_RJ <= "00";\r
+ LED_ADDON_SFP_GREEN(0) <= (gbe_status(0) and gbe_status(1) and gbe_status(2));\r
+ LED_ADDON_SFP_GREEN(1) <= '0';\r
+ LED_ADDON_SFP_ORANGE(0) <= (gbe_status(3) or gbe_status(4));\r
+ LED_ADDON_SFP_ORANGE(1) <= '0';\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Output stage\r
+---------------------------------------------------------------------------\r
+ THE_OUT : entity work.testout\r
+ port map(\r
+ clkout => open,\r
+ refclk => clk_160,\r
+ reset => reset_i,\r
+ data => out_data,\r
+ data_cflag => open,\r
+ data_direction => (others => '0'),\r
+ data_loadn => (others => '1'),\r
+ data_move => (others => '0'),\r
+ dout => out_i\r
+ );\r
+\r
+ PROC_OUT : process\r
+ variable cnt : integer range 0 to 7;\r
+ begin\r
+ wait until rising_edge(clk_160);\r
+ cnt := cnt + 1;\r
+ case cnt is\r
+ when 0 => out_data <= x"ffff";\r
+ when 1 => out_data <= x"ffff";\r
+ when 2 => out_data <= x"ffff";\r
+ when 3 => out_data <= x"0000";\r
+ when 4 => out_data <= x"5555";\r
+ when 5 => out_data <= x"5555";\r
+ when 6 => out_data <= x"5555";\r
+ when 7 => out_data <= x"5555";\r
+ end case;\r
+ end process;\r
+\r
+ H3(3 downto 0) <= out_i(3 downto 0);\r
+ H4(3 downto 0) <= out_i(7 downto 4);\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Input stage\r
+---------------------------------------------------------------------------\r
+ THE_MIMOSIS : entity work.MimosisInput\r
+ port map(\r
+ CLK => clk_160,\r
+ CLK_SYS => clk_sys,\r
+ RESET => reset_i,\r
+\r
+ INPUT => inp_i,\r
+\r
+ BUSRDO_RX => readout_rx,\r
+ BUSRDO_TX => readout_tx(0),\r
+\r
+ BUS_RX => busmimosis_rx,\r
+ BUS_TX => busmimosis_tx\r
+ );\r
+\r
+-- inp_i <= H2(3 downto 0) & H1(3 downto 0);\r
+ inp_i <= H2(3) & H1(3) & H2(2) & H1(2) & H2(1) & H1(1) & H2(0) & H1(0);\r
+-------------------------------------------------------------------------------\r
+-- No trigger/data endpoint included\r
+-------------------------------------------------------------------------------\r
+-- readout_tx(0).data_finished <= '1';\r
+-- readout_tx(0).data_write <= '0';\r
+-- readout_tx(0).busy_release <= '1';\r
+\r
+SFP_ADDON_TX_DIS <= (others => '0');\r
+end architecture;\r
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.version.all;\r
+use work.config.all;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.trb3_components.all;\r
+use work.med_sync_define.all;\r
+\r
+entity trb5sc_mimosis is\r
+ port(\r
+ CLK_200 : in std_logic;\r
+ CLK_125 : in std_logic;\r
+ CLK_EXT : in std_logic;\r
+\r
+ TRIG_IN_BACKPL : in std_logic; --Reference Time\r
+ TRIG_IN_RJ45 : in std_logic; --Reference Time\r
+ IN_SELECT_EXT_CLOCK : in std_logic;\r
+\r
+ SPARE : out std_logic_vector(1 downto 0); -- trigger output 2+3\r
+ BACK_GPIO : inout std_logic_vector(3 downto 0); --0: Serdes out, 1: Serdes in, 2,3: trigger output 0+1\r
+\r
+ SFP_TX_DIS : out std_logic;\r
+ SFP_LOS : in std_logic;\r
+ SFP_MOD_0 : in std_logic;\r
+\r
+ --AddOn\r
+-- FE_GPIO : inout std_logic_vector(11 downto 0);\r
+-- FE_CLK : out std_logic_vector( 2 downto 1);\r
+-- FE_DIFF : inout std_logic_vector(63 downto 0);\r
+ --INP : inout std_logic_vector(63 downto 0);\r
+ --LED_ADDON : out std_logic_vector(5 downto 0);\r
+ LED_ADDON_SFP_ORANGE : out std_logic_vector(1 downto 0);\r
+ LED_ADDON_SFP_GREEN : out std_logic_vector(1 downto 0);\r
+ LED_ADDON_RJ : out std_logic_vector(1 downto 0);\r
+ SFP_ADDON_TX_DIS : out std_logic_vector(1 downto 0);\r
+ SFP_ADDON_LOS : in std_logic_vector(1 downto 0);\r
+\r
+ RJ : inout std_logic_vector(3 downto 0);\r
+ H1 : inout std_logic_vector(4 downto 0);\r
+ H2 : inout std_logic_vector(4 downto 0);\r
+ H3 : inout std_logic_vector(4 downto 0);\r
+ H4 : inout std_logic_vector(4 downto 0);\r
+ H5 : inout std_logic_vector(3 downto 0);\r
+ H6 : inout std_logic_vector(4 downto 0);\r
+ H7 : inout std_logic_vector(4 downto 0);\r
+\r
+ PIN : out std_logic_vector(8 downto 1);\r
+\r
+ MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic;\r
+\r
+ --ADC\r
+ ADC_SCLK : out std_logic;\r
+ ADC_NCS : out std_logic;\r
+ ADC_MOSI : out std_logic;\r
+ ADC_MISO : in std_logic;\r
+ --Flash, Reload\r
+ FLASH_SCLK : out std_logic;\r
+ FLASH_NCS : out std_logic;\r
+ FLASH_MOSI : out std_logic;\r
+ FLASH_MISO : in std_logic;\r
+ FLASH_HOLD : out std_logic;\r
+ FLASH_WP : out std_logic;\r
+ PROGRAMN : out std_logic;\r
+ --I2C\r
+ I2C_SDA : inout std_logic;\r
+ I2C_SCL : inout std_logic;\r
+ TMP_ALERT : in std_logic;\r
+\r
+ --LED\r
+ LED : out std_logic_vector(8 downto 1);\r
+ LED_SFP_YELLOW : out std_logic;\r
+ LED_SFP_GREEN : out std_logic;\r
+ LED_SFP_RED : out std_logic;\r
+ LED_RJ_GREEN : out std_logic_vector(1 downto 0);\r
+ LED_RJ_RED : out std_logic_vector(1 downto 0);\r
+ LED_EXT_CLOCK : out std_logic;\r
+\r
+ --Other Connectors\r
+ TEST : inout std_logic_vector(14 downto 1); --on v1 only\r
+ --COMMON_SDA, COMMON_SCL : inout std_logic\r
+ HDR_IO : inout std_logic_vector(15 downto 0) --23..16 on v2 only\r
+ );\r
+\r
+\r
+ attribute syn_useioff : boolean;\r
+ attribute syn_useioff of FLASH_NCS : signal is true;\r
+ attribute syn_useioff of FLASH_SCLK : signal is true;\r
+ attribute syn_useioff of FLASH_MOSI : signal is true;\r
+ attribute syn_useioff of FLASH_MISO : signal is true;\r
+\r
+\r
+end entity;\r
+\r
+architecture arch of trb5sc_mimosis is\r
+ attribute syn_keep : boolean;\r
+ attribute syn_preserve : boolean;\r
+\r
+ signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320, clk_40 : std_logic;\r
+ signal GSR_N : std_logic;\r
+ signal reset_i : std_logic;\r
+ signal clear_i : std_logic;\r
+ signal trigger_in_i : std_logic;\r
+\r
+\r
+ attribute syn_keep of GSR_N : signal is true;\r
+ attribute syn_preserve of GSR_N : signal is true;\r
+\r
+ signal debug_clock_reset : std_logic_vector(31 downto 0);\r
+ signal external_clock_lock : std_logic := '0';\r
+ signal debug_tools : std_logic_vector(31 downto 0);\r
+\r
+ --Media Interface\r
+ signal med2int : med2int_array_t(0 to 0);\r
+ signal int2med : int2med_array_t(0 to 0);\r
+ signal med_stat_debug : std_logic_vector (1*64-1 downto 0);\r
+ signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic;\r
+\r
+\r
+ signal readout_rx : READOUT_RX;\r
+ signal readout_tx : readout_tx_array_t(0 to 0);\r
+\r
+ signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx, busgbeip_tx, busgbereg_tx, busfwd_tx : CTRLBUS_TX;\r
+ signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx, busgbeip_rx, busgbereg_rx, busfwd_rx : CTRLBUS_RX;\r
+\r
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');\r
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+\r
+ signal sed_error_i : std_logic;\r
+ signal clock_select : std_logic;\r
+ signal bus_master_active : std_logic;\r
+ signal flash_ncs_i : std_logic;\r
+\r
+ signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0);\r
+ signal header_io_i : std_logic_vector(10 downto 1);\r
+ signal timer : TIMERS;\r
+ signal add_reg : std_logic_vector(31 downto 0);\r
+ alias led_off : std_logic is add_reg(0);\r
+\r
+ signal out_data : std_logic_vector(15 downto 0);\r
+ signal out_i : std_logic_vector( 7 downto 0);\r
+ signal inp_i : std_logic_vector( 7 downto 0);\r
+ signal gbe_status : std_logic_vector(15 downto 0);\r
+\r
+\r
+ signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0);\r
+ signal i2c_reg_2 : std_logic_vector(31 downto 0);\r
+ signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0);\r
+ signal mimosis_scl_drv, mimosis_sda_drv : std_logic;\r
+ signal i2c_go_100, i2c_go : std_logic;\r
+ signal i2c_reg_5_40 : std_logic_vector(31 downto 0);\r
+ signal counter : unsigned(23 downto 0);\r
+ --signal fwd_dst_mac : std_logic_vector(47 downto 0);\r
+ --signal fwd_dst_ip : std_logic_vector(31 downto 0);\r
+ --signal fwd_dst_port : std_logic_vector(15 downto 0);\r
+ --signal fwd_data : std_logic_vector(7 downto 0);\r
+ --signal fwd_datavalid : std_logic;\r
+ --signal fwd_sop : std_logic;\r
+ --signal fwd_eop : std_logic;\r
+ --signal fwd_ready : std_logic;\r
+ --signal fwd_full : std_logic;\r
+ --signal fwd_length : std_logic_vector(15 downto 0);\r
+ --signal fwd_do_send : std_logic;\r
+\r
+begin\r
+\r
+\r
+trigger_in_i <= (TRIG_IN_BACKPL and IN_SELECT_EXT_CLOCK) or (TRIG_IN_RJ45 and not IN_SELECT_EXT_CLOCK);\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Clock & Reset Handling\r
+---------------------------------------------------------------------------\r
+ THE_CLOCK_RESET : entity work.clock_reset_handler\r
+ port map(\r
+ CLOCK_IN => CLK_200,\r
+ RESET_FROM_NET => med2int(0).stat_op(13),\r
+ SEND_RESET_IN => med2int(0).stat_op(15),\r
+\r
+ BUS_RX => bustc_rx,\r
+ BUS_TX => bustc_tx,\r
+\r
+ RESET_OUT => reset_i,\r
+ CLEAR_OUT => clear_i,\r
+ GSR_OUT => GSR_N,\r
+\r
+ REF_CLK_OUT => clk_full,\r
+ SYS_CLK_OUT => clk_sys,\r
+ RAW_CLK_OUT => clk_full_osc,\r
+\r
+ DEBUG_OUT => debug_clock_reset\r
+ );\r
+\r
+\r
+\r
+THE_160_PLL : entity work.pll_200_160\r
+ port map(\r
+ CLKI => clk_full_osc,\r
+ CLKOP => clk_160,\r
+ CLKOS => clk_320,\r
+ CLKOS2=> clk_40\r
+ );\r
+\r
+H5(3) <= clk_320;\r
+RJ(0) <= clk_40;\r
+\r
+---------------------------------------------------------------------------\r
+-- TrbNet Uplink\r
+---------------------------------------------------------------------------\r
+\r
+ THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync\r
+ generic map(\r
+ SERDES_NUM => SERDES_NUM,\r
+ USE_NEW_ECP5_RESET => 0,\r
+ IS_SYNC_SLAVE => c_YES\r
+ )\r
+ port map(\r
+ CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full,\r
+ CLK_INTERNAL_FULL => clk_full_osc,\r
+ SYSCLK => clk_sys,\r
+ RESET => reset_i,\r
+ CLEAR => clear_i,\r
+ --Internal Connection\r
+ MEDIA_MED2INT => med2int(0),\r
+ MEDIA_INT2MED => int2med(0),\r
+\r
+ --Sync operation\r
+ RX_DLM => open,\r
+ RX_DLM_WORD => open,\r
+ TX_DLM => open,\r
+ TX_DLM_WORD => open,\r
+\r
+ --SFP Connection\r
+ SD_PRSNT_N_IN => sfp_prsnt_i,\r
+ SD_LOS_IN => sfp_los_i,\r
+ SD_TXDIS_OUT => sfp_txdis_i,\r
+ --Control Interface\r
+ BUS_RX => bussci_rx,\r
+ BUS_TX => bussci_tx,\r
+ -- Status and control port\r
+ STAT_DEBUG => med_stat_debug(63 downto 0),\r
+ CTRL_DEBUG => open\r
+ );\r
+\r
+ gen_sfp_con : if SERDES_NUM = 1 generate\r
+ sfp_los_i <= SFP_LOS;\r
+ sfp_prsnt_i <= SFP_MOD_0;\r
+ SFP_TX_DIS <= sfp_txdis_i;\r
+ end generate;\r
+ gen_bpl_con : if SERDES_NUM = 0 generate\r
+ sfp_los_i <= BACK_GPIO(1);\r
+ sfp_prsnt_i <= BACK_GPIO(1);\r
+ BACK_GPIO(0) <= sfp_txdis_i;\r
+ end generate;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Endpoint\r
+---------------------------------------------------------------------------\r
+ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record\r
+ generic map (\r
+ ADDRESS_MASK => x"FFFF",\r
+ BROADCAST_BITMASK => BROADCAST_BITMASK,\r
+ REGIO_INIT_ENDPOINT_ID => x"0001",\r
+ REGIO_USE_1WIRE_INTERFACE => c_I2C,\r
+ TIMING_TRIGGER_RAW => c_YES,\r
+ --Configure data handler\r
+ DATA_INTERFACE_NUMBER => 1,\r
+ DATA_BUFFER_DEPTH => EVENT_BUFFER_SIZE,\r
+ DATA_BUFFER_WIDTH => 32,\r
+ DATA_BUFFER_FULL_THRESH => 2**EVENT_BUFFER_SIZE-EVENT_MAX_SIZE,\r
+ TRG_RELEASE_AFTER_DATA => c_YES,\r
+ HEADER_BUFFER_DEPTH => 9,\r
+ HEADER_BUFFER_FULL_THRESH => 2**9-16,\r
+ USE_GBE => USE_GBE\r
+ )\r
+\r
+ port map(\r
+ -- Misc\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+ CLK_125 => CLK_125,\r
+ CLEAR_N => GSR_N,\r
+\r
+ -- Media direction port\r
+ MEDIA_MED2INT => med2int(0),\r
+ MEDIA_INT2MED => int2med(0),\r
+\r
+ --Timing trigger in\r
+ TRG_TIMING_TRG_RECEIVED_IN => trigger_in_i,\r
+\r
+ READOUT_RX => readout_rx,\r
+ READOUT_TX => readout_tx,\r
+\r
+ --Slow Control Port\r
+ REGIO_COMMON_STAT_REG_IN => common_stat_reg, --0x00\r
+ REGIO_COMMON_CTRL_REG_OUT => common_ctrl_reg, --0x20\r
+ BUS_RX => ctrlbus_rx,\r
+ BUS_TX => ctrlbus_tx,\r
+ BUS_MASTER_IN => bus_master_in,\r
+ BUS_MASTER_OUT => bus_master_out,\r
+ BUS_MASTER_ACTIVE => bus_master_active,\r
+\r
+ ONEWIRE_INOUT => open,\r
+ I2C_SCL => I2C_SCL,\r
+ I2C_SDA => I2C_SDA,\r
+ --Timing registers\r
+ TIMERS_OUT => timer,\r
+ STATUS_GBE_OUT=> gbe_status\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Bus Handler\r
+---------------------------------------------------------------------------\r
+\r
+ THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record\r
+ generic map(\r
+ PORT_NUMBER => 5,\r
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", 5 => x"8100", 6 => x"8300", 7 => x"8400", others => x"0000"),\r
+ PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, 5 => 8, 6 => 8, 7 => 8, others => 0),\r
+ PORT_MASK_ENABLE => 1\r
+ )\r
+ port map(\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+\r
+ REGIO_RX => ctrlbus_rx,\r
+ REGIO_TX => ctrlbus_tx,\r
+\r
+ BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED\r
+ BUS_RX(1) => bussci_rx, --SCI Serdes\r
+ BUS_RX(2) => bustc_rx, --Clock switch\r
+ BUS_RX(3) => busmimosis_rx,\r
+ BUS_RX(4) => busi2c_rx,\r
+ --BUS_RX(5) => busgbeip_rx,\r
+ --BUS_RX(6) => busgbereg_rx,\r
+ --BUS_RX(7) => busfwd_rx,\r
+ BUS_TX(0) => bustools_tx,\r
+ BUS_TX(1) => bussci_tx,\r
+ BUS_TX(2) => bustc_tx,\r
+ BUS_TX(3) => busmimosis_tx,\r
+ BUS_TX(4) => busi2c_tx,\r
+ --BUS_TX(5) => busgbeip_tx,\r
+ --BUS_TX(6) => busgbereg_tx,\r
+ --BUS_TX(7) => busfwd_tx,\r
+ STAT_DEBUG => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- Control Tools\r
+---------------------------------------------------------------------------\r
+ THE_TOOLS : entity work.trb3sc_tools\r
+ generic map(\r
+ ADC_CMD_1 => x"2c3cb",\r
+ ADC_CMD_2 => x"1d5cb",\r
+ ADC_CMD_3 => x"1e3cb",\r
+ ADC_CMD_4 => x"2f5cb",\r
+ ADC_CMD_T => x"1F393"\r
+ )\r
+ port map(\r
+ CLK => clk_sys,\r
+ RESET => reset_i,\r
+\r
+ --Flash & Reload\r
+ FLASH_CS => flash_ncs_i,\r
+ FLASH_CLK => FLASH_SCLK,\r
+ FLASH_IN => FLASH_MISO,\r
+ FLASH_OUT => FLASH_MOSI,\r
+ PROGRAMN => PROGRAMN,\r
+ REBOOT_IN => common_ctrl_reg(15),\r
+ --SPI\r
+ SPI_CS_OUT => spi_cs,\r
+ SPI_MOSI_OUT => spi_mosi,\r
+ SPI_MISO_IN => spi_miso,\r
+ SPI_CLK_OUT => spi_clk,\r
+ --Header\r
+ --HEADER_IO => open,\r
+ HEADER_IO(7) => HDR_IO(6),\r
+ HEADER_IO(8) => HDR_IO(7),\r
+ ADDITIONAL_REG => add_reg,\r
+ --ADC\r
+ ADC_CS => ADC_NCS,\r
+ ADC_MOSI => ADC_MOSI,\r
+ ADC_MISO => ADC_MISO,\r
+ ADC_CLK => ADC_SCLK,\r
+ --Trigger & Monitor\r
+ MONITOR_INPUTS => (others => '0'),\r
+ TRIG_GEN_INPUTS => (others => '0'),\r
+ TRIG_GEN_OUTPUTS(1 downto 0) => BACK_GPIO(3 downto 2),\r
+ TRIG_GEN_OUTPUTS(3 downto 2) => SPARE(1 downto 0),\r
+ --SED\r
+ SED_ERROR_OUT => sed_error_i,\r
+ --Slowcontrol\r
+ BUS_RX => bustools_rx,\r
+ BUS_TX => bustools_tx,\r
+ --Control master for default settings\r
+ BUS_MASTER_IN => bus_master_in,\r
+ BUS_MASTER_OUT => bus_master_out,\r
+ BUS_MASTER_ACTIVE => bus_master_active,\r
+ DEBUG_OUT => debug_tools\r
+ );\r
+\r
+--counter <= counter + '1' when rising_edge(clk_sys);\r
+--HDR_IO <= std_logic_vector(counter(15 downto 0));\r
+--LED <= std_logic_vector(counter(23 downto 16));\r
+\r
+ --COMMON_SDA(6) <= '0' when (add_reg(31) = '1') else 'Z';\r
+ --COMMON_SCL(7) <= '0' when (add_reg(30) = '1') else 'Z';\r
+\r
+ FLASH_HOLD <= '1';\r
+ FLASH_WP <= '1';\r
+\r
+---------------------------------------------------------------------------\r
+-- I2C\r
+---------------------------------------------------------------------------\r
+THE_I2C : entity work.i2c_slim2\r
+ port map(\r
+ CLOCK => clk_40,\r
+ RESET => reset_i,\r
+ -- I2C command / setup\r
+ I2C_GO_IN => i2c_go,\r
+ ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read\r
+ WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word\r
+ DIRECT_IN => i2c_reg_1(4), -- don't send command\r
+ I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined)\r
+ I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored)\r
+ I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte)\r
+ I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command\r
+ I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command\r
+ STATUS_OUT => i2c_reg_4(23 downto 16),\r
+ VALID_OUT => i2c_reg_4(31),\r
+ I2C_BUSY_OUT => i2c_reg_4(30),\r
+ I2C_DONE_OUT => i2c_reg_4(29),\r
+ -- I2C connections\r
+ SDA_IN => PIN(4),\r
+ SDA_OUT => mimosis_sda_drv,\r
+ SCL_IN => PIN(3),\r
+ SCL_OUT => mimosis_scl_drv,\r
+ -- Debug\r
+ BSM_OUT => i2c_reg_4(27 downto 24)\r
+);\r
+\r
+-- I2C signal open collector driver\r
+-- PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
+-- PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
+\r
+PIN(4) <= MIMOSIS_SDA;\r
+PIN(3) <= MIMOSIS_SCL;\r
+MIMOSIS_SDA <= '0' when (mimosis_sda_drv = '0') else 'Z';\r
+MIMOSIS_SCL <= '0' when (mimosis_scl_drv = '0') else 'Z';\r
+\r
+H5(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC\r
+PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START\r
+PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET\r
+\r
+PROC_I2C_REGS : process begin\r
+ wait until rising_edge(CLK_SYS);\r
+ busi2c_tx.ack <= '0';\r
+ busi2c_tx.unknown <= '0';\r
+ busi2c_tx.nack <= '0';\r
+ busi2c_tx.data <= (others => '0');\r
+ i2c_go_100 <= '0';\r
+\r
+ if busi2c_rx.write = '1' then\r
+ busi2c_tx.ack <= '1';\r
+ if busi2c_rx.addr(3 downto 0) = x"0" then\r
+ i2c_reg_0 <= busi2c_rx.data;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"1" then\r
+ i2c_reg_1 <= busi2c_rx.data;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"2" then\r
+ i2c_reg_2 <= busi2c_rx.data;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"3" then\r
+ i2c_go_100 <= busi2c_rx.data(0);\r
+ elsif busi2c_rx.addr(3 downto 0) = x"5" then\r
+ i2c_reg_5 <= busi2c_rx.data;\r
+ else\r
+ busi2c_tx.ack <= '0';\r
+ busi2c_tx.unknown <= '1';\r
+ end if;\r
+ elsif busi2c_rx.read = '1' then\r
+ busi2c_tx.ack <= '1';\r
+ if busi2c_rx.addr(3 downto 0) = x"0" then\r
+ busi2c_tx.data <= i2c_reg_0;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"1" then\r
+ busi2c_tx.data <= i2c_reg_1;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"2" then\r
+ busi2c_tx.data <= i2c_reg_2;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"3" then\r
+ busi2c_tx.data <= (others => '0');\r
+ elsif busi2c_rx.addr(3 downto 0) = x"4" then\r
+ busi2c_tx.data <= i2c_reg_4;\r
+ elsif busi2c_rx.addr(3 downto 0) = x"5" then\r
+ busi2c_tx.data <= i2c_reg_5;\r
+ else\r
+ busi2c_tx.ack <= '0';\r
+ busi2c_tx.unknown <= '1';\r
+\r
+ end if;\r
+ end if;\r
+end process;\r
+\r
+ THE_I2C_GO_SYNC : pulse_sync\r
+ port map(\r
+ CLK_A_IN => clk_sys,\r
+ RESET_A_IN => reset_i,\r
+ PULSE_A_IN => i2c_go_100,\r
+ CLK_B_IN => clk_40,\r
+ RESET_B_IN => reset_i,\r
+ PULSE_B_OUT => i2c_go\r
+ );\r
+\r
+ THE_MIMOSIS_SIGNAL_SYNC : signal_sync\r
+ generic map(\r
+ WIDTH => 32,\r
+ DEPTH => 2\r
+ )\r
+ port map(\r
+ RESET => reset_i,\r
+ CLK0 => clk_sys,\r
+ CLK1 => clk_40,\r
+ D_IN => i2c_reg_5,\r
+ D_OUT => i2c_reg_5_40\r
+ );\r
+\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- LED\r
+---------------------------------------------------------------------------\r
+\r
+ LED_SFP_GREEN <= not med2int(0).stat_op(9);\r
+ LED_SFP_RED <= not (med2int(0).stat_op(10) or med2int(0).stat_op(11));\r
+ LED_SFP_YELLOW <= not med2int(0).stat_op(8);\r
+ LED <= x"FF";\r
+ LED_RJ_GREEN(1)<= not external_clock_lock or led_off; --on if external clock used\r
+ LED_RJ_GREEN(0)<= '1' when SERDES_NUM = 0 or led_off = '1' else '0'; --on if SFP is used (next to SFP)\r
+ LED_RJ_RED(1) <= external_clock_lock or led_off; --on if internal clock used\r
+ LED_RJ_RED(0) <= '1' when SERDES_NUM = 1 or led_off = '1' else '0'; --on if backplane is used (next to SFP)\r
+ LED_EXT_CLOCK <= IN_SELECT_EXT_CLOCK or led_off; --on if trigger/clock from RJ45 is used\r
+\r
+ TEST(13 downto 1) <= (others => '0');\r
+ TEST(14) <= flash_ncs_i; --for v1 boards\r
+\r
+ FLASH_NCS <= flash_ncs_i;\r
+\r
+ LED_ADDON_RJ <= "00";\r
+ LED_ADDON_SFP_GREEN(0) <= (gbe_status(0) and gbe_status(1) and gbe_status(2));\r
+ LED_ADDON_SFP_GREEN(1) <= '0';\r
+ LED_ADDON_SFP_ORANGE(0) <= (gbe_status(3) or gbe_status(4));\r
+ LED_ADDON_SFP_ORANGE(1) <= '0';\r
+\r
+-----------------------------------------------------------------------------\r
+---- GbE\r
+-----------------------------------------------------------------------------\r
+ --GBE : entity work.gbe_wrapper\r
+ --generic map(\r
+ --DO_SIMULATION => 0,\r
+ --INCLUDE_DEBUG => 0,\r
+ --USE_INTERNAL_TRBNET_DUMMY => 0,\r
+ --USE_EXTERNAL_TRBNET_DUMMY => 0,\r
+ --RX_PATH_ENABLE => 1,\r
+ --FIXED_SIZE_MODE => 1,\r
+ --INCREMENTAL_MODE => 1,\r
+ --FIXED_SIZE => 100,\r
+ --FIXED_DELAY_MODE => 1,\r
+ --UP_DOWN_MODE => 0,\r
+ --UP_DOWN_LIMIT => 100,\r
+ --FIXED_DELAY => 100,\r
+\r
+ --NUMBER_OF_GBE_LINKS => 1,\r
+ --LINKS_ACTIVE => "0001",\r
+\r
+ --LINK_HAS_READOUT => "0000",\r
+ --LINK_HAS_SLOWCTRL => "0000",\r
+ --LINK_HAS_DHCP => "0001",\r
+ --LINK_HAS_ARP => "0001",\r
+ --LINK_HAS_PING => "0001",\r
+ --LINK_HAS_FWD => "0001"\r
+ --)\r
+ --port map(\r
+ --CLK_SYS_IN => clk_sys,\r
+ --CLK_125_IN => CLK_125,\r
+ --RESET => reset_i,\r
+ --GSR_N => GSR_N,\r
+ ---- Trigger\r
+ --TRIGGER_IN => '0',\r
+ ---- SFP\r
+ --SD_PRSNT_N_IN(0) => SFP_MOD_0,\r
+ --SD_LOS_IN(0) => SFP_LOS,\r
+ --SD_TXDIS_OUT(0) => SFP_TX_DIS,\r
+ ---- trigger channel\r
+ ---- only for LINK_HAS_READOUT\r
+ --CTS_NUMBER_IN => (others => '0'),\r
+ --CTS_CODE_IN => (others => '0'),\r
+ --CTS_INFORMATION_IN => (others => '0'),\r
+ --CTS_READOUT_TYPE_IN => (others => '0'),\r
+ --CTS_START_READOUT_IN => '0',\r
+ --CTS_DATA_OUT => open,\r
+ --CTS_DATAREADY_OUT => open,\r
+ --CTS_READOUT_FINISHED_OUT => open,\r
+ --CTS_READ_IN => '1',\r
+ --CTS_LENGTH_OUT => open,\r
+ --CTS_ERROR_PATTERN_OUT => open,\r
+ ---- data channel\r
+ ---- only for LINK_HAS_READOUT\r
+ --FEE_DATA_IN => (others => '0'),\r
+ --FEE_DATAREADY_IN => '0',\r
+ --FEE_READ_OUT => open,\r
+ --FEE_STATUS_BITS_IN => (others => '0'),\r
+ --FEE_BUSY_IN => '0',\r
+ ---- unique adresses\r
+ --MC_UNIQUE_ID_IN => timer.uid,\r
+ --MY_TRBNET_ADDRESS_IN => timer.network_address,\r
+ --ISSUE_REBOOT_OUT => open, --BUG: needs to be connected\r
+ ---- slow control by GbE\r
+ --GSC_CLK_IN => open,\r
+ --GSC_INIT_DATAREADY_OUT => open,\r
+ --GSC_INIT_DATA_OUT => open,\r
+ --GSC_INIT_PACKET_NUM_OUT => open,\r
+ --GSC_INIT_READ_IN => '1',\r
+ --GSC_REPLY_DATAREADY_IN => '0',\r
+ --GSC_REPLY_DATA_IN => (others => '0'),\r
+ --GSC_REPLY_PACKET_NUM_IN => (others => '0'),\r
+ --GSC_REPLY_READ_OUT => open,\r
+ --GSC_BUSY_IN => '0',\r
+ ---- readout\r
+ --BUS_IP_RX => busgbeip_rx, -- registers inside GbE\r
+ --BUS_IP_TX => busgbeip_tx, -- registers inside GbE\r
+ --BUS_REG_RX => busgbereg_rx, -- registers inside GbE\r
+ --BUS_REG_TX => busgbereg_tx, -- registers inside GbE\r
+ ---- Forwarder\r
+ --FWD_DST_MAC_IN(47 downto 0) => fwd_dst_mac,\r
+ --FWD_DST_IP_IN(31 downto 0) => fwd_dst_ip,\r
+ --FWD_DST_UDP_IN(15 downto 0) => fwd_dst_port,\r
+ --FWD_DATA_IN(7 downto 0) => fwd_data,\r
+ --FWD_DATA_VALID_IN(0) => fwd_datavalid,\r
+ --FWD_SOP_IN(0) => fwd_sop,\r
+ --FWD_EOP_IN(0) => fwd_eop,\r
+ --FWD_READY_OUT(0) => fwd_ready,\r
+ --FWD_FULL_OUT(0) => fwd_full,\r
+ ---- reset\r
+ --MAKE_RESET_OUT => open, -- reset by GbE --BUG: needs to be connected\r
+ ---- debug and status\r
+ --STATUS_OUT => open,\r
+ --DEBUG_OUT => open\r
+ --);\r
+\r
+\r
+\r
+-----------------------------------------------------------------------------\r
+---- Test registers\r
+-----------------------------------------------------------------------------\r
+--THE_REGS : process begin\r
+ --wait until rising_edge(clk_sys);\r
+ --busfwd_tx.ack <= '0';\r
+ --busfwd_tx.nack <= '0';\r
+ --busfwd_tx.unknown <= '0';\r
+\r
+ --if busfwd_rx.write = '1' then\r
+ --busfwd_tx.ack <= '1';\r
+ --case busfwd_rx.addr(7 downto 0) is\r
+ --when x"00" => fwd_dst_ip <= busfwd_rx.data;\r
+ --when x"01" => fwd_dst_port <= busfwd_rx.data(15 downto 0);\r
+ --when x"02" => fwd_dst_mac(31 downto 0) <= busfwd_rx.data;\r
+ --when x"03" => fwd_dst_mac(47 downto 32) <= busfwd_rx.data(15 downto 0);\r
+ --when x"04" => fwd_length <= busfwd_rx.data(15 downto 0);\r
+ --when x"05" => fwd_do_send <= busfwd_rx.data(0);\r
+ --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1';\r
+ --end case;\r
+ --elsif busfwd_rx.read = '1' then\r
+ --busfwd_tx.ack <= '1';\r
+ --case busfwd_rx.addr(7 downto 0) is\r
+ --when x"00" => busfwd_tx.data <= fwd_dst_ip;\r
+ --when x"01" => busfwd_tx.data <= x"0000" & fwd_dst_port;\r
+ --when x"02" => busfwd_tx.data <= fwd_dst_mac(31 downto 0);\r
+ --when x"03" => busfwd_tx.data <= x"0000" & fwd_dst_mac(47 downto 32);\r
+ --when x"04" => busfwd_tx.data <= x"0000" & fwd_length;\r
+ --when x"05" => busfwd_tx.data <= x"0000000" & fwd_full & fwd_ready & "0" & fwd_do_send;\r
+ --when others => busfwd_tx.ack <= '0'; busfwd_tx.unknown <= '1';\r
+ --end case;\r
+ --end if;\r
+ --if reset_i = '1' then\r
+ --fwd_do_send <= '0';\r
+ --end if;\r
+--end process;\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Output stage\r
+---------------------------------------------------------------------------\r
+ THE_OUT : entity work.testout\r
+ port map(\r
+ clkout => open,\r
+ refclk => clk_160,\r
+ reset => reset_i,\r
+ data => out_data,\r
+ data_cflag => open,\r
+ data_direction => (others => '0'),\r
+ data_loadn => (others => '1'),\r
+ data_move => (others => '0'),\r
+ dout => out_i\r
+ );\r
+\r
+ PROC_OUT : process\r
+ variable cnt : integer range 0 to 7;\r
+ begin\r
+ wait until rising_edge(clk_160);\r
+ cnt := cnt + 1;\r
+ case cnt is\r
+ when 0 => out_data <= x"ffff";\r
+ when 1 => out_data <= x"ffff";\r
+ when 2 => out_data <= x"ffff";\r
+ when 3 => out_data <= x"0000";\r
+ when 4 => out_data <= x"5555";\r
+ when 5 => out_data <= x"5555";\r
+ when 6 => out_data <= x"5555";\r
+ when 7 => out_data <= x"5555";\r
+ end case;\r
+ end process;\r
+\r
+ H3(3 downto 0) <= out_i(3 downto 0);\r
+ H4(3 downto 0) <= out_i(7 downto 4);\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Input stage\r
+---------------------------------------------------------------------------\r
+ THE_MIMOSIS : entity work.MimosisInput\r
+ port map(\r
+ CLK => clk_160,\r
+ CLK_SYS => clk_sys,\r
+ RESET => reset_i,\r
+\r
+ INPUT => inp_i,\r
+\r
+ BUSRDO_RX => readout_rx,\r
+ BUSRDO_TX => readout_tx(0),\r
+\r
+ BUS_RX => busmimosis_rx,\r
+ BUS_TX => busmimosis_tx\r
+ );\r
+\r
+-- inp_i <= H2(3 downto 0) & H1(3 downto 0);\r
+ inp_i <= H2(3) & H1(3) & H2(2) & H1(2) & H2(1) & H1(1) & H2(0) & H1(0);\r
+-------------------------------------------------------------------------------\r
+-- No trigger/data endpoint included\r
+-------------------------------------------------------------------------------\r
+-- readout_tx(0).data_finished <= '1';\r
+-- readout_tx(0).data_write <= '0';\r
+-- readout_tx(0).busy_release <= '1';\r
+\r
+SFP_ADDON_TX_DIS <= (others => '0');\r
+end architecture;\r
+\r
+\r
+\r
jspc29 / trb5sc.git / commitdiff