CTS with 3ch TDC

diff --git a/backplanemaster/par.p2t b/backplanemaster/par.p2t
index 569fcb25f6b0cd55ea7638ee67ea6443b1e2884e..3a11e9f273303c8f056342db4d85542ed36831c7 100644 (file)
--- a/backplanemaster/par.p2t
+++ b/backplanemaster/par.p2t
@@ -1,7 +1,7 @@
 -w
 -l 5
 -s 12
--t 33 # seed setting here! 32
+-t 32 # seed setting here! 32
 -c 1
 -e 2
 -i 15

diff --git a/cts/config_simple.vhd b/cts/config_simple.vhd
index e258855be2c28e10cad2b9356bc55a21154674ed..27ea22579c6ba6ab75c957678571b79ac5d24f46 100644 (file)
--- a/cts/config_simple.vhd
+++ b/cts/config_simple.vhd
@@ -48,8 +48,8 @@ package config is
 
 -- TDC stuff    
   constant NUM_TDC_MODULES         : integer range 1 to 4  := 1;  -- number of tdc modules to implement
-  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 5; -- number of tdc channels per module
-  constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 4;  --the nearest power of two, for convenience reasons 
+  constant NUM_TDC_CHANNELS        : integer range 1 to 65 := 3; -- number of tdc channels per module
+  constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6  := 2;  --the nearest power of two, for convenience reasons 
   constant DOUBLE_EDGE_TYPE        : integer range 0 to 3  := 0;  --double edge type:  0, 1, 2,  3
   -- 0: single edge only,
   -- 1: same channel,

diff --git a/cts/par.p2t b/cts/par.p2t
index 51f613b617c921229b9e11754144d402c2a05ecf..32f03803d316a0de6782053357fa99e6f12e3b99 100644 (file)
--- a/cts/par.p2t
+++ b/cts/par.p2t
@@ -1,7 +1,7 @@
 -w
 -l 5
 -s 10
--t 3 # seed setting here! 3 4 13 17 37 51
+-t 13 # seed setting here! 3 4 13 17 37 51
 -c 0
 -e 0
 -i 6

diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd
index 104495433110c23f4c0036bec2e5c227c33cdf52..6019db43dafbd078ac08d4deab010fa590b6e87e 100644 (file)
--- a/cts/trb3sc_cts.vhd
+++ b/cts/trb3sc_cts.vhd
@@ -360,7 +360,7 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
     )
     port map(
       -- Clocks and reset
-      CLK_REF_FULL       => clk_full_osc, -- CLK_SUPPL_PCLK
+      CLK_REF_FULL       => clk_full_osc,
       SYSCLK             => clk_sys,
       RESET              => reset_i, -- check
       -- Media Interface TX/RX
@@ -392,7 +392,7 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate
       QUAD_RST_IN        => '0', -- check
       GLOBAL_RESET_OUT   => open,
       SLAVE_ACTIVE_OUT   => open,
-      SLAVE_ACTIVE_IN    => slave_active_fake, --'1',
+      SLAVE_ACTIVE_IN    => slave_active_fake,
       TX_PLL_LOL_IN      => tx_pll_lol_all_i,
       TX_PLL_LOL_OUT     => tx_pll_lol_qd_b_i,
       TX_CLK_AVAIL_OUT   => tx_clk_avail_i,
@@ -1082,7 +1082,10 @@ end generate;
 
   -- For single edge measurements
   gen_single : if DOUBLE_EDGE_TYPE = 0 or DOUBLE_EDGE_TYPE = 1 or DOUBLE_EDGE_TYPE = 3 generate
-    hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= INP(NUM_TDC_CHANNELS-2 downto 0);
+--    hit_in_i(NUM_TDC_CHANNELS-1 downto 1) <= INP(NUM_TDC_CHANNELS-2 downto 0);
+--    hit_in_i(NUM_TDC_CHANNELS-1 downto 3) <= INP(NUM_TDC_CHANNELS-2 downto 2);
+    hit_in_i(2)                           <= tx_dlm_i;
+    hit_in_i(1)                           <= rx_dlm_i;
   end generate;
   
 end architecture;