added switch for padiwa flavours

diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd
index 97c63dae9fa5ed08b442fa93b4cfd31749353e84..741d307fce965f2b36039c36b31eb1f50bbf0d8e 100644 (file)
--- a/base/trb3_components.vhd
+++ b/base/trb3_components.vhd
@@ -526,7 +526,7 @@ package trb3_components is
     generic(
       SERDES_NUM    : integer range 0 to 3 := 0;
 --     MASTER_CLOCK_SWITCH : integer := c_NO;   --just for debugging, should be NO
-      IS_SYNC_SLAVE : integer              := c_NO  --select slave mode
+      IS_SYNC_SLAVE : integer              := 0  --select slave mode
       );
     port(
       CLK                : in  std_logic;  -- _internal_ 200 MHz reference clock

diff --git a/wasa/panda_dirc_wasa.prj b/wasa/panda_dirc_wasa.prj
index c3c97dc2d0e0021b86bfa67c7bf565a6de05e2e4..d5444e6f3e0470f0f036e5b55758681e853d909f 100644 (file)
--- a/wasa/panda_dirc_wasa.prj
+++ b/wasa/panda_dirc_wasa.prj
@@ -6,8 +6,8 @@
 
 #project files
 add_file -vhdl -lib work "/d/jspc29/lattice/diamond/1.4.2.105/cae_library/synthesis/vhdl/machxo2.vhd"
-add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/base/trb3_components.vhd"
 add_file -vhdl -lib work "/d/jspc22/trb/cvs/trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/base/trb3_components.vhd"
 add_file -vhdl -lib work "/d/jspc22/trb/cvs/trbnet/trb_net_components.vhd"
 add_file -vhdl -lib work "/d/jspc22/trb/cvs/trb3/wasa/source/spi_slave.vhd"
 add_file -vhdl -lib work "/d/jspc22/trb/cvs/trbnet/trb_net_onewire.vhd"

diff --git a/wasa/panda_dirc_wasa.vhd b/wasa/panda_dirc_wasa.vhd
index 319ef8f93ce5d6aa1a9b5cdcf3c4635124cc2f92..a1a94f0cd3c7387a768f4c77e19629ca8e6c254a 100644 (file)
--- a/wasa/panda_dirc_wasa.vhd
+++ b/wasa/panda_dirc_wasa.vhd
@@ -14,7 +14,7 @@ use machxo2.all;
 \r
 entity panda_dirc_wasa is\r
   generic(\r
-    NORMAL_ORDER : integer := 0\r
+    PADIWA_FLAVOUR : integer := 2\r
     );\r
   port(\r
     CON        : out std_logic_vector(16 downto 1);\r
@@ -261,12 +261,13 @@ clk_source: OSCH
 ---------------------------------------------------------------------------\r
 -- Input re-ordering\r
 ---------------------------------------------------------------------------\r
-gen_outputs_1 : if NORMAL_ORDER = 1 generate\r
+gen_outputs_1 : if PADIWA_FLAVOUR = 2 generate\r
   INP_i <= INP;\r
   PWM <= pwm_i(15 downto 0);\r
 end generate;\r
 \r
-gen_outputs_2 : if NORMAL_ORDER = 0 generate\r
+\r
+gen_outputs_2 : if PADIWA_FLAVOUR = 1 generate\r
   INP_i <= INP(16) & INP(8) & INP(15) & INP(7) & INP(14) & INP(6) & INP(13) & INP(5) & \r
            INP(12) & INP(4) & INP(11) & INP(3) & INP(10) & INP(2) & INP(9)  & INP(1);\r
   PWM <= pwm_i(15) & pwm_i(7) & pwm_i(14) & pwm_i(6) & pwm_i(13) & pwm_i(5) & pwm_i(12) & pwm_i(4) & \r
@@ -506,7 +507,7 @@ THE_IO_REG_READ : process begin
     case spi_channel_i(3 downto 0) is\r
       when x"0" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16));\r
       when x"1" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16));\r
-      when x"2" => spi_reg20_i <= x"000" & "000" & std_logic_vector(to_unsigned(NORMAL_ORDER,1));\r
+      when x"2" => spi_reg20_i <= x"000" & std_logic_vector(to_unsigned(PADIWA_FLAVOUR,4));\r
       when others => null;\r
     end case;\r
   end if;\r