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+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsection{Memory Map}
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+The configuration memory of the GbE interface consists of two parts. Registers 0x8300 to 0x83FF are used to configure the behaviour the SubEventBuilder and the packing of data into UDP packets. The registers implemented are listed in table \ref{GbEConfigRegisters}.
+
+The second part is located at addresses 0x8200 to 0x82F0. Each block of 16 addresses describes the addresses and ports used to send data to one of the Eventbuilders (see table \ref{GbEEBSettings}. Which entry in the memory is used, is selected by the lower 4 bits of the IPU readout information as shown in table \ref{IPUInformationBits}.
+
+\begin{table}[hbtp]
+\begin{center}
+\begin{tabularx}{\textwidth}{|l|l|X|}
+\hline
+\textbf{Address} & \textbf{Name} & \textbf{Description} \\
+\hline\hline
+0x8300 & SubEventID & The ID is written in each SubEventHeader to identify the source of data \\
+0x8301 & SubEventDecoding & Information sent in the SubEventHeader \\
+0x8302 & QueueDecoding & Information sent in the HadesTuQueue \\
+0x8303 & MaxPacketSize & Maximum size of the UDP packet (default: 0xFDE8 = 65000) \\
+0x8304 & MaxFrameSize & Maximum size of a Ethernet packet (default: 0x578 = 1400) \\
+0x8305 & UseGbE & Enable sending data over GbE (default: 1) \\
+0x8306 & UseTrbNet & Forward data over TrbNet (default: 0) \\
+0x8307 & MultiEventQueue & Enable packing several events into one event queue (default: 0) \\
+0x8308 & TriggerCounter & The internal, 24bit trigger counter used for the SubEventHeader (default: 0) \\
+0x83FF & ResetDefault & When written to 0xFFFFFFFF: all values are reset to default \\
+\hline
+\end{tabularx}
+\caption{Memory map for GbE and SubEventBuilder configuration}
+\label{GbEConfigRegisters}
+\end{center}
+\end{table}
+
+\begin{table}[hbtp]
+\begin{center}
+\begin{tabularx}{\textwidth}{|l|l|X|}
+\hline
+\textbf{Address} & \textbf{Name} & \textbf{Description} \\
+\hline\hline
+0x82S0 & DestMacLsb & Lower 32 bits of the destination MAC address \\
+0x82S1 & DestMacMsb & Bit 15..0: Higher 16 bit of the destinatioon MAC, Bit 31..16: reserved\\
+0x82S2 & DestIP & Destination IP \\
+0x82S3 & DestUdpPort & Bit 15..0: Destination UDP port, Bit 31..16: reserved \\
+0x82S4 & SrcMacLsb & Lower 32 bits of the source MAC address \\
+0x82S5 & SrcMacMsb & Bit 15..0: Higher 16 bit of the source MAC, Bit 31..16: reserved \\
+0x82S6 & SrcIP & Source IP address \\
+0x82S7 & SrcUdpPort & Bit 15..0: Source UDP port, Bit 31..16: reserved \\
+0x82S8 & MtuSize & Bit 15..0: MTU size, Bit 31..16: reserved \\
+\hline
+\end{tabularx}
+\caption{Memory map for GbE Ethernet settings. The third digit is the EventBuilder number, allowing to stor 16 different settings that are selected by the IPU request information word.}
+\label{GbEEBSettings}
+\end{center}
+\end{table}
\item[0x8C - 0x8F: Waiting for ACK] One register for each TrbNet channel. Each bit gives the status of one port: 1 if data transmission on this port is stopped because the receiver did not acknowledge previous EOB words, 0 otherwise.
\item[0xA0 - 0xA3: Error-/Status-Bits $\dagger$] One register for each TrbNet channel. Each register is the last Error-/Status-Bits, combined from all ports.
\item[0xA4: Slow Control Error $\dagger$] One bit for each port. 1 if either one of the Errorbits 1,3,6 on the slow control channel have been set before. This register is cleared after being read.
+ \item[0xA5: Endpoint reached] One bit for each port. 1 if this port returned the ``Endpoint reached'' bit in the status word set in the last slow control access, 0 otherwise. This information can be used to track a single board in the network: First a read access using the network address of the selected board has to be done. Immediately afterward this register can be read. To secure this non-atomic operation, the register is only updated if the board also return the ``don't understand' bit, e.g. after a read memory access to register 0.
\item[0x4000 - 0x400F: IPU Packet counter] One register for each port. Each register is a 32 bit counter of the packets (with 64bit payload each) received on the IPU channel on this port. A write to 0x4000 resets all counters.
\item[0x4010 - 0x401F: Slow Control Packet counter] One register for each port. Each register is a 32 bit counter of the packets (with 64bit payload each) received on the slow control channel on this port. A write to 0x4010 resets all counters.
\item[0x4020 - 0x402F: Error Bits $\dagger$] One register for each port. Contents are part of the last Error-/Status-Bits received on this port:
\item Bit 16 - 23: Errorbits 0 - 7 on IPU channel
\item Bit 24 - 31: Errorbits 16 - 23 on IPU channel
\end{itemize}
+ \item[0x4030 - 0x403F] Inclusive busy counter. One register for each port counting the time the port is busy (waiting for the reply after a trigger has been sent). Writing to 0x4030 clears all counters.
+ \item[0x4040 - 0x404F] Exclusive busy counter. One register for each port counting the time this port and only this port is busy (waiting for the reply after a trigger has been sent). Writing to 0x4040 clears all counters.
+ \item[0x4050] Here, the global time also accessible in register 0x50 is readable. This allows to do a simultaneous readout with the busy counter registers to get exact time information.
\end{description}
$\dagger$: Register is not reset during network reset
\end{center}
\end{table}
-The full data inside the Subevent will consist of several parts. Due to the structure of the readout system, there will be one SubEvent from each sector. According to table \ref{subeventidtable}, the SubEventIds are 0x8400, 0x8410 ... 0x8450. Inside the SubEvent, there will be data from up to four different sources. From each source there is a DHDR sent, followed by some data. The first two sources are the two FPGA on the Shower AddOn board, containing the physics data. The third source is the hub located in the third FPGA which can send some debugging information. The fourth and last source is the SubEventBuilder which will add one data word containing the status and error bits for the event.
+The full data inside the Subevent will consist of several parts. Due to the structure of the readout system, there will be one SubEvent from each sector. According to table \ref{subeventidtable}, the SubEventIds are 0x3200, 0x3210 ... 0x3250. Inside the SubEvent, there will be data from up to four different sources. From each source there is a DHDR sent, followed by some data. The first two sources are the two FPGA on the Shower AddOn board, containing the physics data. The third source is the hub located in the third FPGA which can send some debugging information. The fourth and last source is the SubEventBuilder which will add one data word containing the status and error bits for the event.
The addresses of each of the sources are also defined in table \ref{networkaddresses}. They are 0x32S1 and 0x32S2 (where S is the sector, numbered from 0 to 5) for the two FPGA equipped with ADC, 0x32S0 for the hub in the third FPGA and 0x5555 for the SubEventBuilder. The overall structure containing SubEventHeader, event information, DHDR and data is shown in table \ref{IPUData:SubEventBuilder}.
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