RESET : in std_logic;
--Connection to Etrax
ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0);
- ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0);
- ETRAX_BUS_BUSY : out std_logic;
- ETRAX_IS_READY_TO_READ : out std_logic;
+ ETRAX_DATA_BUS_C : in std_logic_vector(17 downto 0);
+ ETRAX_BUS_BUSY : out std_logic;
--Connection to internal FPGA logic (all addresses above 0x100)
INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);
INTERNAL_DATA_IN : in std_logic_vector(31 downto 0);
FPGA_REGISTER_OUT : out std_logic_vector(CONTROL_REGISTERS*32-1 downto 0);
--Reset FPGA via Etrax
EXTERNAL_RESET : out std_logic;
- STAT : out std_logic_vector(7 downto 0)
+ STAT : out std_logic_vector(15 downto 0)
);
end etrax_interface;
architecture etrax_interface of etrax_interface is
);
end component;
- type ETRAX_RW_STATE_MACHINE is (IDLE, SAVE_DATA_1 ,SAVE_DATA_2 , SEND_DATA_1, SEND_ZERO, SEND_DATA_2, WAIT_FOR_DATA, SAVING_EXTERNAL_DATA, SEND_VALID, SEND_EXTERNAL_TRIGGER ); --SAVE_ADDRESS_1, SAVE_ADDRESS_2,
+ type ETRAX_RW_STATE_MACHINE is (IDLE, SAVE_DATA_1 ,SAVE_DATA_2 , SEND_DATA_1, SEND_DATA_2, WAIT_FOR_DATA, SEND_EXTERNAL_TRIGGER ); --SEND_VALID
signal ETRAX_RW_STATE_currentstate,ETRAX_RW_STATE_nextstate : ETRAX_RW_STATE_MACHINE;
signal etrax_trigger_pulse : std_logic;
--- signal saved_rw_mode : std_logic_vector(15 downto 0);
signal saved_address : std_logic_vector (15 downto 0);
signal saved_data : std_logic_vector(31 downto 0);
signal saved_data_fpga : std_logic_vector(31 downto 0);
signal internal_reset_i : std_logic;
signal communication_state : std_logic_vector(3 downto 0);
signal buf_FPGA_REGISTER_OUT : std_logic_vector(CONTROL_REGISTERS*32-1 downto 0);
- signal reg_BUSC, last_BUSC : std_logic_vector(1 downto 0);
+ signal last_BUSC : std_logic_vector(17 downto 16);
+ signal reg_BUSC : std_logic_vector(17 downto 0);
+
+ signal delayed_internal_reset_i : std_logic;
begin
STAT(3 downto 0) <= communication_state;
STAT(4) <= read_cycle;
STAT(5) <= write_cycle;
- STAT(7 downto 6) <= "00";
+ STAT(6) <= reg_BUSC(16);
+ STAT(7) <= etrax_trigger_pulse;
+ STAT(8) <= reg_BUSC(17);
MAKE_RESET: process (CLK)
begin
if rising_edge(CLK) then
if (ETRAX_DATA_BUS_C(16)='1' and ETRAX_DATA_BUS_C(17)='1') then
internal_reset_i <= '1';
- elsif ETRAX_DATA_BUS_C(16)='0' and ETRAX_DATA_BUS_C(17)='0' then
- internal_reset_i <= '0';
else
internal_reset_i <= '0';
end if;
end process MAKE_RESET;
BUSC_SYNC : signal_sync
+ generic map(
+ WIDTH => 18,
+ DEPTH => 1
+ )
port map(
RESET => RESET,
CLK0 => CLK,
CLK1 => CLK,
- D_IN => ETRAX_DATA_BUS_C(17 downto 16),
+ D_IN => ETRAX_DATA_BUS_C,
D_OUT => reg_BUSC
);
+ THE_RESET_DELAY : signal_sync
+ generic map(
+ WIDTH => 1,
+ DEPTH => 4
+ )
+ port map(
+ RESET => RESET,
+ CLK0 => CLK,
+ CLK1 => CLK,
+ D_IN(0) => internal_reset_i,
+ D_OUT(0) => delayed_internal_reset_i
+ );
+
process(CLK)
begin
if rising_edge(CLK) then
- last_BUSC <= reg_BUSC;
- etrax_trigger_pulse <= '0';
- etrax_is_ready_to_read_i <= '0';
- if (not last_BUSC(0) and reg_BUSC(0)) = '1' then
- etrax_trigger_pulse <= '1';
- end if;
- if (not last_BUSC(1) and reg_BUSC(1)) = '1' then
- etrax_is_ready_to_read_i <= '1';
- end if;
+ last_BUSC <= reg_BUSC(17 downto 16);
end if;
end process;
+ etrax_trigger_pulse <= (last_BUSC(16) xor reg_BUSC(16)) and not delayed_internal_reset_i;
EXTERNAL_RESET <= internal_reset_i;
ETRAX_BUS_BUSY <= '0' when ETRAX_RW_STATE_currentstate = IDLE else '1';
- ETRAX_IS_READY_TO_READ <= etrax_is_ready_to_read_i;
--- read_cycle <= saved_rw_mode(15);
--- write_cycle <= not saved_rw_mode(15);
read_cycle <= saved_address(15);
write_cycle <= not saved_address(15);
when IDLE =>
communication_state <= x"1";
if etrax_trigger_pulse = '1' then
--- ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_1;
--- end if;
---
--- when SAVE_ADDRESS_1 =>
--- communication_state <= x"2";
--- if etrax_trigger_pulse = '1' then
--- ETRAX_RW_STATE_nextstate <= SAVE_ADDRESS_2;
--- end if;
---
--- when SAVE_ADDRESS_2 =>
--- communication_state <= x"3";
--- if etrax_trigger_pulse = '1' then
--- if read_cycle = '1' then
--- ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER;
--- else
- ETRAX_RW_STATE_nextstate <= SAVE_DATA_1;
- end if;
--- end if;
+ ETRAX_RW_STATE_nextstate <= SAVE_DATA_1;
+ end if;
when SAVE_DATA_1 =>
- communication_state <= x"4";
---new start
+ communication_state <= x"2";
if read_cycle = '1' then
ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER;
- end if;
---new end
- if etrax_trigger_pulse = '1' then
+ elsif etrax_trigger_pulse = '1' then
ETRAX_RW_STATE_nextstate <= SAVE_DATA_2;
end if;
when SAVE_DATA_2 =>
- communication_state <= x"5";
+ communication_state <= x"3";
if etrax_trigger_pulse = '1' then
ETRAX_RW_STATE_nextstate <= SEND_EXTERNAL_TRIGGER;
end if;
when SEND_EXTERNAL_TRIGGER =>
- ETRAX_RW_STATE_nextstate <= WAIT_FOR_DATA;
-
- when WAIT_FOR_DATA =>
- communication_state <= x"6";
- if write_cycle = '1' then
- ETRAX_RW_STATE_nextstate <= SEND_VALID;
- elsif INTERNAL_DATAREADY_IN = '1' or saved_address(14 downto 8) = 0 then --(15 downto 8)
- ETRAX_RW_STATE_nextstate <= SAVING_EXTERNAL_DATA;
+ communication_state <= x"4";
+ if read_cycle = '1' and (INTERNAL_DATAREADY_IN = '1' or saved_address(14 downto 5) = 0) then
+ ETRAX_RW_STATE_nextstate <= SEND_DATA_1;
+ elsif write_cycle = '1' then
+ ETRAX_RW_STATE_nextstate <= IDLE;
+ else
+ ETRAX_RW_STATE_nextstate <= WAIT_FOR_DATA;
end if;
- when SEND_VALID =>
- communication_state <= x"7";
- if etrax_trigger_pulse = '1' then
- ETRAX_RW_STATE_nextstate <= IDLE;
+ when WAIT_FOR_DATA =>
+ communication_state <= x"5";
+ if INTERNAL_DATAREADY_IN = '1' then
+ ETRAX_RW_STATE_nextstate <= SEND_DATA_1;
end if;
- when SAVING_EXTERNAL_DATA =>
- ETRAX_RW_STATE_nextstate <= SEND_DATA_1;
-
when SEND_DATA_1 =>
- communication_state <= x"8";
- if etrax_trigger_pulse = '1' then
- ETRAX_RW_STATE_nextstate <= SEND_ZERO;
- end if;
-
- when SEND_ZERO =>
- communication_state <= x"a";
+ communication_state <= x"6";
if etrax_trigger_pulse = '1' then
ETRAX_RW_STATE_nextstate <= SEND_DATA_2;
end if;
- when SEND_DATA_2 =>
- communication_state <= x"9";
+ when SEND_DATA_2 =>
+ communication_state <= x"7";
if etrax_trigger_pulse = '1' then
ETRAX_RW_STATE_nextstate <= IDLE;
end if;
begin
if rising_edge(CLK) then
if internal_reset_i = '1' then
--- saved_rw_mode <= (others => '0');
saved_address <= (others => '0');
saved_data <= (others => '0');
--- elsif ETRAX_RW_STATE_currentstate = IDLE and etrax_trigger_pulse = '1' then
--- saved_rw_mode <= ETRAX_DATA_BUS_C(15 downto 0);
--- elsif ETRAX_RW_STATE_currentstate = SAVE_ADDRESS_2 and etrax_trigger_pulse = '1' then
--- saved_address(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0);
---new start
elsif ETRAX_RW_STATE_currentstate = IDLE and etrax_trigger_pulse = '1' then
- saved_address(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0);
---new end
+ saved_address(15 downto 0) <= reg_BUSC(15 downto 0);
elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_1 and etrax_trigger_pulse = '1' then
- saved_data(31 downto 16) <= ETRAX_DATA_BUS_C(15 downto 0);
+ saved_data(31 downto 16) <= reg_BUSC(15 downto 0);
elsif ETRAX_RW_STATE_currentstate = SAVE_DATA_2 and etrax_trigger_pulse = '1' then
- saved_data(15 downto 0) <= ETRAX_DATA_BUS_C(15 downto 0);
+ saved_data(15 downto 0) <= reg_BUSC(15 downto 0);
end if;
end if;
end process REGISTER_ETRAX_BUS;
INTERNAL_ADDRESS_OUT <= '0' & saved_address(14 downto 0);
INTERNAL_DATA_OUT <= saved_data;
- INTERNAL_WRITE_OUT <= '1' when write_cycle = '1' and saved_address(14 downto 8) /= 0 and ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER else '0'; --(15 downto 8)
- INTERNAL_READ_OUT <= '1' when read_cycle = '1' and saved_address(14 downto 8) /= 0 and ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER else '0'; --(15 downto 8)
+ INTERNAL_WRITE_OUT <= '1' when write_cycle = '1' and saved_address(14 downto 5) /= 0
+ and ETRAX_RW_STATE_currentstate = SEND_EXTERNAL_TRIGGER
+ else '0';
+ INTERNAL_READ_OUT <= '1' when read_cycle = '1' and saved_address(14 downto 5) /= 0
+ and ETRAX_RW_STATE_currentstate = SAVE_DATA_1
+ else '0';
FPGA_REGISTER_OUT <= buf_FPGA_REGISTER_OUT;
begin
if rising_edge(CLK) then
if internal_reset_i = '1' then
- ETRAX_DATA_BUS_B(16 downto 0) <= "0"& x"0000";--(others => 'Z');
+ ETRAX_DATA_BUS_B(16 downto 0) <= "0"& x"0000";
elsif ETRAX_RW_STATE_currentstate = SEND_DATA_1 then
- ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(31 downto 16);--fpga_register_07_i(15 downto 0);--
+ ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(31 downto 16);
ETRAX_DATA_BUS_B(16) <= '1';
- elsif ETRAX_RW_STATE_currentstate = SEND_DATA_2 or ETRAX_RW_STATE_currentstate = SEND_VALID then
- ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(15 downto 0);--fpga_register_07_i(15 downto 0);--
+ elsif ETRAX_RW_STATE_currentstate = SEND_DATA_2 then
+ ETRAX_DATA_BUS_B(15 downto 0) <= saved_data_fpga(15 downto 0);
ETRAX_DATA_BUS_B(16) <= '1';
else
ETRAX_DATA_BUS_B(16 downto 0) <= "0"& x"0000";
end process ETRAX_DATA_BUS_CHOOSE;
ETRAX_DATA_BUS_B(17) <= '1';
- ETRAX_DATA_BUS_C <= (others => 'Z');
DATA_SOURCE_SELECT : process (CLK)
variable stat_num : integer range 0 to STATUS_REGISTERS-1;
if rising_edge(CLK) then
stat_num := conv_integer(saved_address(3 downto 0));
ctrl_num := conv_integer(saved_address(3 downto 0));
--- case saved_rw_mode(14 downto 0) is
--- when "000000000000000" =>
- if read_cycle = '1' then
- if saved_address(14 downto 8) = 0 then
- if saved_address(7 downto 4) = 0 then --status regs
- saved_data_fpga <= FPGA_REGISTER_IN((stat_num)*32+31 downto stat_num*32);
- elsif saved_address(4) = '1' then
- saved_data_fpga <= buf_FPGA_REGISTER_OUT((ctrl_num)*32+31 downto (ctrl_num)*32);
- else
- saved_data_fpga <= (others => '0');
- end if;
- elsif INTERNAL_DATAREADY_IN = '1' then
- saved_data_fpga <= INTERNAL_DATA_IN;
- end if;
- elsif write_cycle = '1' and ETRAX_RW_STATE_currentstate = WAIT_FOR_DATA then
- if saved_address(15 downto 4) = x"001" then
- buf_FPGA_REGISTER_OUT((ctrl_num+1)*32-1 downto (ctrl_num)*32) <= saved_data;
- end if;
+ if read_cycle = '1' then
+ if saved_address(14 downto 5) = 0 then
+ if saved_address(4) = '0' then --status regs
+ saved_data_fpga <= FPGA_REGISTER_IN((stat_num)*32+31 downto stat_num*32);
+ elsif saved_address(4) = '1' then
+ saved_data_fpga <= buf_FPGA_REGISTER_OUT((ctrl_num)*32+31 downto (ctrl_num)*32);
+ else
+ saved_data_fpga <= (others => '0');
end if;
--- when others =>
--- saved_data_fpga <= x"deadface";
--- end case;
+ elsif INTERNAL_DATAREADY_IN = '1' then
+ saved_data_fpga <= INTERNAL_DATA_IN;
+ end if;
+ elsif write_cycle = '1' and ETRAX_RW_STATE_currentstate = WAIT_FOR_DATA then
+ if saved_address(4) = '1' then
+ buf_FPGA_REGISTER_OUT((ctrl_num+1)*32-1 downto (ctrl_num)*32) <= saved_data;
+ end if;
+ end if;
+
end if;
end process DATA_SOURCE_SELECT;
end architecture;
library work;
use work.trb_net_std.all;
+use work.trb_net_components.all;
architecture trb2_control_arch of trb2_control is
- component trb_net16_med_tlk is
- port (
- RESET : in std_logic;
- CLK : in std_logic;
- TLK_CLK : in std_logic;
- TLK_ENABLE : out std_logic;
- TLK_LCKREFN : out std_logic;
- TLK_LOOPEN : out std_logic;
- TLK_PRBSEN : out std_logic;
- TLK_RXD : in std_logic_vector(15 downto 0);
- TLK_RX_CLK : in std_logic;
- TLK_RX_DV : in std_logic;
- TLK_RX_ER : in std_logic;
- TLK_TXD : out std_logic_vector(15 downto 0);
- TLK_TX_EN : out std_logic;
- TLK_TX_ER : out std_logic;
- SFP_LOS : in std_logic;
- SFP_TX_DIS : out std_logic;
- MED_DATAREADY_IN : in std_logic;
- MED_READ_IN : in std_logic;
- MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_OUT : out std_logic;
- MED_READ_OUT : out std_logic;
- MED_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- STAT : out std_logic_vector (63 downto 0);
- STAT_MONITOR : out std_logic_vector ( 100 downto 0);
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0)
- --connect STAT(0) to LED
- );
- end component;
component trb_net_bridge_etrax_endpoint is
generic(
USE_CHANNELS : channel_config_t := (c_YES,c_YES,c_NO,c_YES);
);
end component;
- component etrax_interface is
- generic(
- STATUS_REGISTERS : integer := 4;
- CONTROL_REGISTERS : integer := 4
- );
- port (
- CLK : in std_logic;
- RESET : in std_logic;
- --Connection to Etrax
- ETRAX_DATA_BUS_B : out std_logic_vector(17 downto 0);
- ETRAX_DATA_BUS_C : inout std_logic_vector(17 downto 0);
- ETRAX_BUS_BUSY : out std_logic;
- ETRAX_IS_READY_TO_READ : out std_logic;
- --Connection to internal FPGA logic (all addresses above 0x100)
- INTERNAL_DATA_OUT : out std_logic_vector(31 downto 0);
- INTERNAL_DATA_IN : in std_logic_vector(31 downto 0);
- INTERNAL_READ_OUT : out std_logic;
- INTERNAL_WRITE_OUT : out std_logic;
- INTERNAL_DATAREADY_IN : in std_logic;
- INTERNAL_ADDRESS_OUT : out std_logic_vector(15 downto 0);
- --Easy-to-use status and control registers (Addresses 0-15 (stat) and 16-31 (ctrl)
- FPGA_REGISTER_IN : in std_logic_vector(STATUS_REGISTERS*32-1 downto 0);
- FPGA_REGISTER_OUT : out std_logic_vector(CONTROL_REGISTERS*32-1 downto 0);
- --Reset FPGA via Etrax
- EXTERNAL_RESET : out std_logic;
- STAT : out std_logic_vector(7 downto 0)
- );
- end component;
-
- component trb_net_onewire is
- generic(
- USE_TEMPERATURE_READOUT : integer range 0 to 1 := 1;
- CLK_PERIOD : integer := 10 --clk period in ns
- );
- port(
- CLK : in std_logic;
- RESET : in std_logic;
- --connection to 1-wire interface
- ONEWIRE : inout std_logic;
- --connection to id ram, according to memory map in TrbNetRegIO
- DATA_OUT : out std_logic_vector(15 downto 0);
- ADDR_OUT : out std_logic_vector(2 downto 0);
- WRITE_OUT: out std_logic;
- TEMP_OUT : out std_logic_vector(11 downto 0);
- STAT : out std_logic_vector(31 downto 0)
- );
- end component;
signal CLK : std_logic;
signal RESET : std_logic;
signal STAT_API1 : std_logic_vector(31 downto 0);
signal MED_STAT_OP : std_logic_vector(15 downto 0);
signal MED_CTRL_OP : std_logic_vector(15 downto 0);
- signal EI_STAT : std_logic_vector(7 downto 0);
+ signal EI_STAT : std_logic_vector(15 downto 0);
signal last_CTRL_REGS : std_logic_vector(15 downto 14);
signal send_reset_counter : std_logic_vector(11 downto 0) := x"FFF";
ETRAX_DATA_BUS_B => FS_PB,
ETRAX_DATA_BUS_C => FS_PC,
ETRAX_BUS_BUSY => etrax_state(0),
- ETRAX_IS_READY_TO_READ => etrax_state(1),
INTERNAL_DATA_OUT => etrax_data_in,
INTERNAL_DATA_IN => etrax_data_out,
INTERNAL_READ_OUT => etrax_read,
---------------------------------------------------------------------
STAT_REGS(63 downto 0) <= APL_STAT & STAT_ENDP;
- buf_ADO_TTL(14 downto 0) <= STAT_API1(14 downto 0); --TLK_STAT(15 downto 14) & "0" & TLK_STAT(27 downto 16);
+ buf_ADO_TTL(14 downto 0) <= EI_STAT(14 downto 0);
+ --STAT_API1(14 downto 0); --TLK_STAT(15 downto 14) & "0" & TLK_STAT(27 downto 16);
-- buf_ADO_TTL(0) <= etrax_read;
-- buf_ADO_TTL(6 downto 1) <= EI_STAT(5 downto 0);
-- buf_ADO_TTL(14 downto 7) <= (others => 'Z');
jspc29 / trbnet.git / commitdiff