Typo correction and feature bit addition

diff --git a/trb3/IncludedFeaturesTable.tex b/trb3/IncludedFeaturesTable.tex
index eb2b9c2ce5656c08a30b7ff600cad7f004dea8bd..f40704a86970f0f60cf2b95422ad3ed655224c8c 100644 (file)
--- a/trb3/IncludedFeaturesTable.tex
+++ b/trb3/IncludedFeaturesTable.tex
@@ -37,6 +37,8 @@ channel with stretcher \\
 words, 3:108 words \\
  & 15       & TDC         & Contains a TDC \\
  & 17 -- 16 & ReadoutModule & Number of readout modules \\
+ & 41       & ReferenceTime & Reference Time Path 0: RJ-45 (default) 1: 
+Through Clock Manager (cbmtof only)\\
  & 42       & Spi         & Contains SPI on all relevant I/Os depending on AddOn board design\\
  & 43       & Uart        & Contains an Uart\\
  & 47 -- 44 & InpMonitor  & See table 1. Pinout should match the one of the TDC\\

diff --git a/trb3/TriggerModule.tex b/trb3/TriggerModule.tex
index e19572b88297048f850c4bfa59ad90a7e7d12a93..69bb6497316877c2b000025c49537a66daf33b60 100644 (file)
--- a/trb3/TriggerModule.tex
+++ b/trb3/TriggerModule.tex
@@ -31,8 +31,8 @@ An additional module is used to have counters for each of up to 32 input channel
 be stored in a Fifo at an adjustable rate. The Fifos for all channels are controlled by a common
 logic and store their data synchronously. Filling of the Fifos has to be triggered and stops after
 1024 samples have been acquired.
-To save ressources, it is also possible to use only one monitoring fifo combined with a multiplexer
-to select one of the inputs as source.
+To save resources, it is also possible to use only one monitoring Fifo combined 
+with a multiplexer to select one of the inputs as source.
 
 \begin{description*}
  \item[cf00, cf02 .. cf1e] Input enable mask. Up to 16 times, according to number of outputs.
@@ -48,8 +48,9 @@ to select one of the inputs as source.
  \item[cf8e] Status of all input signals
  \item[cf8f] Bit 0: Trigger recording of data. Fifo are cleared, then 1024 samples are acquired\\
              Bit 1: Reset counters\\
-             Bit 20-16: Input select (if only a single fifo is used)
- \item[cfa0 .. cfbf] One fifo for each input. Up to 1024 values of 18 Bit are stored. The uppermost
+             Bit 20-16: Input select (if only a single Fifo is used)
+ \item[cfa0 .. cfbf] One Fifo for each input. Up to 1024 values of 18 Bit are 
+stored. The uppermost
 bit is the Fifo empty signal (data invalid)
  \item[cfc0 .. cfdf] One counter for each input. The width is 24 Bit.
 \end{description*}