architecture trb_net16_hub_base_arch of trb_net16_hub_base is
-
+16
constant total_point_num : integer := MII_NUMBER*2**(c_MUX_WIDTH-1) + INT_NUMBER + 1;
signal m_DATAREADY_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0);
signal m_DATA_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0);
buf_HC_STAT_REGS(16*32-1 downto 12*32) <= HC_STAT_ack_waiting;
buf_HC_STAT_REGS(32*32-1 downto 16*32) <= HUB_ERROR_BITS(16*32-1 downto 0);
buf_HC_STAT_REGS(36*32-1 downto 32*32) <= HUB_STAT_ERRORBITS;
+ buf_HC_STAT_REGS(64*32-1 downto 36*32) <= (others => '0');
loop_links : for i in 0 to 16 generate
buf_HC_STAT_REGS(5*32+i) <= '1' when (i < MII_NUMBER or (i = MII_NUMBER and INT_NUMBER > 0)) and MII_IS_UPLINK(i) = 1 else '0';
if rising_edge(CLK) then
HC_STAT_REGS(8*32-1 downto 0) <= buf_HC_STAT_REGS(8*32-1 downto 0);
HC_STAT_REGS(31*32-1 downto 12*32) <= buf_HC_STAT_REGS(31*32-1 downto 12*32);
- HC_STAT_REGS(36*32-1 downto 32*32) <= buf_HC_STAT_REGS(36*32-1 downto 32*32);
+ HC_STAT_REGS(64*32-1 downto 32*32) <= buf_HC_STAT_REGS(64*32-1 downto 32*32);
end if;
end process;
---------------------------------------------------------------------
--debug Status and Control ports
- buf_STAT_DEBUG(5 downto 0) <= HUB_INIT_DATAREADY_IN(14 downto 9);
- buf_STAT_DEBUG(11 downto 6) <= HUB_REPLY_DATAREADY_IN(14 downto 9);
- buf_STAT_DEBUG(17 downto 12) <= HUB_REPLY_READ_OUT(14 downto 9);
- buf_STAT_DEBUG(23 downto 18) <= HUB_INIT_READ_IN(14 downto 9);
+ buf_STAT_DEBUG(5 downto 0) <= HUB_INIT_DATAREADY_IN(16 downto 11);
+ buf_STAT_DEBUG(11 downto 6) <= HUB_REPLY_DATAREADY_IN(16 downto 11);
+ buf_STAT_DEBUG(17 downto 12) <= HUB_REPLY_READ_OUT(16 downto 11);
+ buf_STAT_DEBUG(23 downto 18) <= HUB_INIT_READ_OUT(16 downto 11);
buf_STAT_DEBUG(30 downto 24) <= HUB_CTRL_final_activepoints(3*32+6 downto 3*32);
buf_STAT_DEBUG(31) <= CLK;