-- use sc.components.all;
entity hub is
generic (
- HOW_MANY_CHANNELS : integer range 2 to c_MAX_MII_PER_HUB := 16
+ HOW_MANY_CHANNELS : integer range 2 to c_MAX_MII_PER_HUB := 4
);
port (
LVDS_CLK_200P : in std_logic;
clkos : out std_logic;
lock : out std_logic);
end component;
- component trb_net16_hub_base
+ component trb_net16_hub_base is
generic (
- --general settings
- MUX_SECURE_MODE : integer range 0 to 1 := c_NO;
- --hub control
- HUB_CTRL_CHANNELNUM : integer range 0 to 3 := 0;--c_SLOW_CTRL_CHANNEL;
- HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_SMALL;
- HUB_CTRL_REG_ADDR_WIDTH : integer range 1 to 7 := 4;
- HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES);
- IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
- INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F00A";
- INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
- COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
- COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
- HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
- --media interfaces
- MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := HOW_MANY_CHANNELS;
- MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
- -- settings for apis
- API_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0;
- API_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3);
- API_TYPE : hub_api_config_t := (0,0,0,0,0,0,0,0);
- API_FIFO_TO_INT_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1);
- API_FIFO_TO_APL_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1);
- --trigger reading interfaces
- TRG_NUMBER : integer range 0 to c_MAX_TRG_PER_HUB := 0;
- TRG_SECURE_MODE : integer range 0 to 1 := c_NO;
- TRG_CHANNELS : hub_api_config_t := (0,1,0,0,0,0,0,0)
- );
+ --hub control
+ HUB_CTRL_CHANNELNUM : integer range 0 to 3 := 3;--c_SLOW_CTRL_CHANNEL;
+ HUB_CTRL_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;
+ HUB_USED_CHANNELS : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+ USE_CHECKSUM : hub_channel_config_t := (c_YES,c_YES,c_YES,c_YES);
+ IBUF_SECURE_MODE : integer range 0 to 1 := c_NO;
+ INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004";
+ INIT_UNIQUE_ID : std_logic_vector(95 downto 0) := (others => '0');
+ COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000";
+ COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001";
+ HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678";
+ --media interfaces
+ MII_NUMBER : integer range 2 to c_MAX_MII_PER_HUB := 4;
+ MII_IBUF_DEPTH : hub_iobuf_config_t := std_HUB_IBUF_DEPTH;
+ -- settings for apis
+ API_NUMBER : integer range 0 to c_MAX_API_PER_HUB := 0;
+ API_CHANNELS : hub_api_config_t := (3,3,3,3,3,3,3,3);
+ API_TYPE : hub_api_config_t := (0,0,0,0,0,0,0,0);
+ API_FIFO_TO_INT_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1);
+ API_FIFO_TO_APL_DEPTH : hub_api_config_t := (1,1,1,1,1,1,1,1);
+ --trigger reading interfaces
+ TRG_NUMBER : integer range 0 to c_MAX_TRG_PER_HUB := 0;
+ TRG_SECURE_MODE : integer range 0 to 1 := c_NO;
+ TRG_CHANNELS : hub_api_config_t := (0,1,0,0,0,0,0,0)
+ );
port (
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
- MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_OUT : out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
- MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
- MED_ERROR_IN : in std_logic_vector (MII_NUMBER*3-1 downto 0);
- MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
- MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
- APL_DATA_IN : in std_logic_vector (API_NUMBER*c_DATA_WIDTH downto 0);
- APL_PACKET_NUM_IN : in std_logic_vector (API_NUMBER*c_NUM_WIDTH downto 0);
- APL_DATAREADY_IN : in std_logic_vector (API_NUMBER downto 0);
- APL_READ_OUT : out std_logic_vector (API_NUMBER downto 0);
- APL_SHORT_TRANSFER_IN : in std_logic_vector (API_NUMBER downto 0);
- APL_DTYPE_IN : in std_logic_vector (API_NUMBER*4 downto 0);
- APL_ERROR_PATTERN_IN : in std_logic_vector (API_NUMBER*32 downto 0);
- APL_SEND_IN : in std_logic_vector (API_NUMBER downto 0);
- APL_TARGET_ADDRESS_IN : in std_logic_vector (API_NUMBER*16 downto 0);
- APL_DATA_OUT : out std_logic_vector (API_NUMBER*16 downto 0);
- APL_PACKET_NUM_OUT : out std_logic_vector (API_NUMBER*c_NUM_WIDTH downto 0);
- APL_TYP_OUT : out std_logic_vector (API_NUMBER*3 downto 0);
- APL_DATAREADY_OUT : out std_logic_vector (API_NUMBER downto 0);
- APL_READ_IN : in std_logic_vector (API_NUMBER downto 0);
- APL_RUN_OUT : out std_logic_vector (API_NUMBER downto 0);
- APL_MY_ADDRESS_IN : in std_logic_vector (API_NUMBER*16 downto 0);
- APL_SEQNR_OUT : out std_logic_vector (API_NUMBER*8 downto 0);
- TRG_GOT_TRIGGER_OUT : out std_logic_vector (TRG_NUMBER downto 0);
- TRG_ERROR_PATTERN_OUT : out std_logic_vector (TRG_NUMBER*32 downto 0);
- TRG_DTYPE_OUT : out std_logic_vector (TRG_NUMBER*4 downto 0);
- TRG_SEQNR_OUT : out std_logic_vector (TRG_NUMBER*8 downto 0);
- TRG_ERROR_PATTERN_IN : in std_logic_vector (TRG_NUMBER*32 downto 0);
- TRG_RELEASE_IN : in std_logic_vector (TRG_NUMBER downto 0);
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ --Media interfacces
+ MED_DATAREADY_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATA_OUT : out std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_OUT: out std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+ MED_READ_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATAREADY_IN : in std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_DATA_IN : in std_logic_vector (MII_NUMBER*c_DATA_WIDTH-1 downto 0);
+ MED_PACKET_NUM_IN : in std_logic_vector (MII_NUMBER*c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT : out std_logic_vector (MII_NUMBER-1 downto 0);
+ MED_ERROR_IN : in std_logic_vector (MII_NUMBER*3-1 downto 0);
+ MED_STAT_OP : in std_logic_vector (MII_NUMBER*16-1 downto 0);
+ MED_CTRL_OP : out std_logic_vector (MII_NUMBER*16-1 downto 0);
+ --API: interfaces
+ APL_DATA_IN : in std_logic_vector (VAL(API_NUMBER*c_DATA_WIDTH) downto 0);
+ APL_PACKET_NUM_IN : in std_logic_vector (VAL(API_NUMBER*c_NUM_WIDTH) downto 0);
+ APL_DATAREADY_IN : in std_logic_vector (VAL(API_NUMBER) downto 0);
+ APL_READ_OUT : out std_logic_vector (VAL(API_NUMBER) downto 0);
+ APL_SHORT_TRANSFER_IN : in std_logic_vector (VAL(API_NUMBER) downto 0);
+ APL_DTYPE_IN : in std_logic_vector (VAL(API_NUMBER*4) downto 0);
+ APL_ERROR_PATTERN_IN : in std_logic_vector (VAL(API_NUMBER*32) downto 0);
+ APL_SEND_IN : in std_logic_vector (VAL(API_NUMBER) downto 0);
+ APL_TARGET_ADDRESS_IN : in std_logic_vector (VAL(API_NUMBER*16) downto 0);
+ APL_DATA_OUT : out std_logic_vector (VAL(API_NUMBER*c_DATA_WIDTH) downto 0);
+ APL_PACKET_NUM_OUT : out std_logic_vector (VAL(API_NUMBER*c_NUM_WIDTH) downto 0);
+ APL_TYP_OUT : out std_logic_vector (VAL(API_NUMBER*3) downto 0);
+ APL_DATAREADY_OUT : out std_logic_vector (VAL(API_NUMBER) downto 0);
+ APL_READ_IN : in std_logic_vector (VAL(API_NUMBER) downto 0);
+ APL_RUN_OUT : out std_logic_vector (VAL(API_NUMBER) downto 0);
+ APL_MY_ADDRESS_IN : in std_logic_vector (VAL(API_NUMBER*16) downto 0);
+ APL_SEQNR_OUT : out std_logic_vector (VAL(API_NUMBER*8) downto 0);
+ --TRG interfaces
+ TRG_GOT_TRIGGER_OUT : out std_logic_vector (VAL(TRG_NUMBER) downto 0);
+ TRG_ERROR_PATTERN_OUT : out std_logic_vector (VAL(TRG_NUMBER*32) downto 0);
+ TRG_DTYPE_OUT : out std_logic_vector (VAL(TRG_NUMBER*4) downto 0);
+ TRG_SEQNR_OUT : out std_logic_vector (VAL(TRG_NUMBER*8) downto 0);
+ TRG_ERROR_PATTERN_IN : in std_logic_vector (VAL(TRG_NUMBER*32) downto 0);
+ TRG_RELEASE_IN : in std_logic_vector (VAL(TRG_NUMBER) downto 0);
ONEWIRE : inout std_logic;
+ --Fixed status and control ports
HUB_STAT_CHANNEL : out std_logic_vector (2**(c_MUX_WIDTH-1)*16-1 downto 0);
HUB_STAT_GEN : out std_logic_vector (31 downto 0);
MPLEX_CTRL : in std_logic_vector (MII_NUMBER*32-1 downto 0);
MPLEX_STAT : out std_logic_vector (MII_NUMBER*32-1 downto 0);
- ETRAX_CTRL : in std_logic_vector (15 downto 0)
+ STAT_COMMON_STAT_REGS : out std_logic_vector (std_COMSTATREG*32-1 downto 0); --Status of common STAT regs
+ STAT_COMMON_CTRL_REGS : out std_logic_vector (std_COMCTRLREG*32-1 downto 0); --Status of common STAT regs
+ STAT_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom STAT regs
+ STAT_CTRL_REGS : out std_logic_vector (8*32-1 downto 0); --Status of custom CTRL regs
+ --Additional access to registers
+ REGIO_EXT_REG_DATA_IN : in std_logic_vector(31 downto 0);
+ REGIO_EXT_REG_DATA_OUT: out std_logic_vector(31 downto 0);
+ REGIO_EXT_REG_WRITE_IN: in std_logic;
+ REGIO_EXT_REG_ADDR_IN : in std_logic_vector(7 downto 0);
+
+ --Debugging registers
+ STAT_DEBUG : out std_logic_vector (31 downto 0); --free status regs for debugging
+ CTRL_DEBUG : in std_logic_vector (31 downto 0) --free control regs for debugging
);
end component;
component simpleupcounter_16bit
signal med_ctrl_op_i : std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0);
signal hub_stat_channel_i : std_logic_vector(2**(c_MUX_WIDTH-1)*16-1 downto 0);
signal hub_stat_gen_i : std_logic_vector(31 downto 0);
+ signal HUB_STAT_DEBUG, HUB_CTRL_DEBUG : std_logic_vector(31 downto 0);
-----------------------------------------------------------------------------
-- other
MED_STAT_OP => med_stat_op_i,
MED_CTRL_OP => med_ctrl_op_i
);
--- ADO_TTL(34 downto 19) <= med_read_in_i(0) & flexi_pcs_synch_status_i(2 downto 1) & med_packet_num_out_i(1 downto 0) & rx_k_i(1 downto 0) & rxd_i(3 downto 0) & med_dataready_out_i(0) & med_data_out_i(3 downto 0);
+ ADO_TTL(34 downto 19) <= med_read_in_i(0) & flexi_pcs_synch_status_i(2 downto 1) & med_packet_num_out_i(1 downto 0) & rx_k_i(1 downto 0) & rxd_i(3 downto 0) & med_dataready_out_i(0) & med_data_out_i(3 downto 0);
-- ADO_TTL(34 downto 19) <= med_dataready_out_i(0)& med_data_out_i(14 downto 0);
--- ADO_TTL(15 downto 0) <= med_read_out_i(0) & flexi_pcs_synch_status_i(7 downto 6) & med_packet_num_in_i(1 downto 0) & tx_k_i(1 downto 0) & txd_synch_i(3 downto 0) & med_dataready_in_i(0) & med_data_in_i(3 downto 0);
+ ADO_TTL(15 downto 0) <= med_read_out_i(0) & flexi_pcs_synch_status_i(7 downto 6) & med_packet_num_in_i(1 downto 0) & tx_k_i(1 downto 0) & txd_synch_i(3 downto 0) & med_dataready_in_i(0) & med_data_in_i(3 downto 0);
-- ADO_TTL(15 downto 0) <= rx_k_i(1 downto 0) & rxd_i(13 downto 0);
-- med_data_in_i(15 downto 0) <= hub_register_0e_and_0d;
-- med_read_in_i <= (others => '1'); --test
HUB_STAT_GEN => hub_stat_gen_i,
MPLEX_CTRL => mplex_ctrl_i,
MPLEX_STAT => open,
- ETRAX_CTRL => hub_register_0e_and_0d
+ REGIO_EXT_REG_DATA_IN => (others => '0'),
+ REGIO_EXT_REG_DATA_OUT=> open,
+ REGIO_EXT_REG_WRITE_IN=> '0',
+ REGIO_EXT_REG_ADDR_IN => (others => '0'),
+ STAT_DEBUG => HUB_STAT_DEBUG,
+ CTRL_DEBUG => HUB_CTRL_DEBUG
);
TRB_HUB_INT : trb_hub_interface
port map (
CLK => LVDS_CLK_200P,
- RESET => ADO_TTL(0),
- STROBE => ADO_TTL(9),
- internal_data_in => ADO_TTL(18 downto 11),
- internal_data_out => ADO_TTL(42 downto 35),
- internal_address => ADO_TTL(34 downto 19),
- internal_mode => ADO_TTL(10),
- VALID_DATA_SENT => ADO_TTL(8),
+ RESET => open, --ADO_TTL(0),
+ STROBE => open, --ADO_TTL(9),
+ internal_data_in => open, --ADO_TTL(18 downto 11),
+ internal_data_out => open, --ADO_TTL(42 downto 35),
+ internal_address => open, --ADO_TTL(34 downto 19),
+ internal_mode => open, --ADO_TTL(10),
+ VALID_DATA_SENT => open, --ADO_TTL(8),
HUB_REGISTER_00 => hub_register_00_i,
HUB_REGISTER_01 => hub_register_01_i,
HUB_REGISTER_02 => hub_register_02_i,
-- hub_register_00_i(7 downto 0) <= flexi_pcs_synch_status_i(7 downto 0);
-- hub_register_01_i(7 downto 0) <= hub_stat_gen_i(15 downto 8);
- hub_register_02_i(7 downto 0) <= saved_lvl1_ready(7 downto 0);--rxd_i(7 downto 0); --; --rxd_1_a(15 downto 8);
- hub_register_03_i(7 downto 0) <= saved_lvl1_ready(15 downto 8);--rxd_i(15 downto 8); --cv_counter_ch1;
- hub_register_04_i(7 downto 0) <= saved_lvl2_ready(7 downto 0);--hub_stat_gen_i(7 downto 0);
+ hub_register_02_i(7 downto 0) <= (others => '0');--saved_lvl1_ready(7 downto 0);--rxd_i(7 downto 0); --; --rxd_1_a(15 downto 8);
+ hub_register_03_i(7 downto 0) <= (others => '0');--saved_lvl1_ready(15 downto 8);--rxd_i(15 downto 8); --cv_counter_ch1;
+ hub_register_04_i(7 downto 0) <= (others => '0');--saved_lvl2_ready(7 downto 0);--hub_stat_gen_i(7 downto 0);
-- hub_register_04_i<= rxd_synch_i(39 downto 32);
- hub_register_05_i(7 downto 0) <= saved_lvl2_ready(15 downto 8);--rxd_i(31 downto 24);
+ hub_register_05_i(7 downto 0) <= (others => '0');--saved_lvl2_ready(15 downto 8);--rxd_i(31 downto 24);
hub_register_10_i(7 downto 0) <= med_data_out_i(31 downto 24);--rxd_i(7+8*16 downto 0+8*16); --; --rxd_1_a(15 downto 8);
-- hub_register_11_i <= rxd_i(23+8*16 downto 16+8*16); --cv_counter_ch1;
-- hub_register_12_i <= rxd_i(39+8*16 downto 32+8*16);
entity trb_net16_dummy_apl is
generic (
TARGET_ADDRESS : std_logic_vector (15 downto 0) := x"F001";
- PREFILL_LENGTH : integer := 2;
- TRANSFER_LENGTH : integer := 2 -- length of dummy data
+ PREFILL_LENGTH : integer := 1;
+ TRANSFER_LENGTH : integer := 1 -- length of dummy data
-- might not work with transfer_length > api_fifo
-- because of incorrect handling of fifo_full_in!
);
port(
-- Misc
- CLK : in std_logic;
- RESET : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
CLK_EN : in std_logic;
-- APL Transmitter port
APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "application to network"
architecture trb_net16_dummy_apl_arch of trb_net16_dummy_apl is
- type SENDER_STATE is (IDLE, WRITING, RUNNING, WAITING, MY_ERROR);
+ type SENDER_STATE is (IDLE, WRITING, WAITING);
signal current_state, next_state : SENDER_STATE;
signal next_counter, reg_counter : std_logic_vector(15 downto 0);
signal buf_APL_DATA_OUT, next_APL_DATA_OUT : std_logic_vector(15 downto 0);
-- address <= x"0008";
-- reghigh <= x"DEAD";
-- reglow <= x"AFFE";
- address <= READ_ID; --x"0001";
- reghigh <= x"0000";
- reglow <= x"0000";
- APL_DTYPE_OUT <= x"8";
+ address <= x"1001"; --x"0001";
+ reghigh <= x"0022";
+ reglow <= xor_all(APL_DATA_IN) & "000000000000011";
+ APL_DTYPE_OUT <= x"A";
APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS;
-
+
process(current_state)
begin
case current_state is
when IDLE => state_bits <= "000";
when WRITING => state_bits <= "001";
- when RUNNING => state_bits <= "010";
when WAITING => state_bits <= "011";
- when MY_ERROR => state_bits <= "100";
when others => state_bits <= "111";
end case;
end process;
APL_ERROR_PATTERN_OUT <= x"12345678";
--APL_DATA_OUT <= reg_counter;
- CHECK_1:if TRANSFER_LENGTH >0 generate
+ CHECK_1:if TRANSFER_LENGTH >0 generate
APL_SHORT_TRANSFER_OUT <= '0';
APL_SEND_OUT <= buf_APL_SEND_OUT;
end generate;
- CHECK_2:if TRANSFER_LENGTH =0 generate
+ CHECK_2:if TRANSFER_LENGTH =0 generate
APL_SHORT_TRANSFER_OUT <= '1';
APL_SEND_OUT <= '1' when APL_RUN_IN = '0' else '0';
end generate;
-
+
SENDER_CTRL: process (current_state, APL_READ_IN, reg_counter, APL_RUN_IN, RESET, packet_counter, buf_APL_SEND_OUT)
begin -- process
next_APL_SEND_OUT <= buf_APL_SEND_OUT;
- next_state <= MY_ERROR;
+ next_state <= IDLE;
next_counter <= reg_counter;
next_APL_PACKET_NUM_OUT <= packet_counter;
next_APL_WRITE_OUT <= '0';
elsif APL_READ_IN = '0' then
next_state <= IDLE;
else
- next_APL_SEND_OUT <= buf_APL_SEND_OUT;
next_state <= WRITING;
next_APL_DATA_OUT <= address;
next_APL_WRITE_OUT <= '1';
next_packet_counter <= "01";
+ next_APL_SEND_OUT <= '1';
end if;
-------------------------------------------------------------------------
-- WRITING
next_counter <= reg_counter +1;
end if;
-----------------------------------------------------------------------
--- RUNNING
------------------------------------------------------------------------
- elsif current_state = RUNNING then
- next_APL_SEND_OUT <= '0';
- if reg_counter = TRANSFER_LENGTH then
- next_state <= WAITING;
- else
- next_state <= RUNNING;
- if APL_READ_IN = '1' then
- next_counter <= reg_counter +1;
- end if;
- end if;
------------------------------------------------------------------------
-- WAITING
-----------------------------------------------------------------------
elsif current_state = WAITING then
end if;
end if;
end process;
-
+
end architecture;
);
port(
-- Misc
- CLK : in std_logic;
- RESET : in std_logic;
+ CLK : in std_logic;
+ RESET : in std_logic;
CLK_EN : in std_logic;
-- APL Transmitter port
APL_DATA_OUT: out std_logic_vector (15 downto 0); -- Data word "application to network"
APL_READ_OUT: out std_logic; -- Read data word
-- APL Control port
APL_RUN_IN: in std_logic; -- Data transfer is running
--- APL_MY_ADDRESS_OUT: in std_logic_vector (15 downto 0); -- My own address (temporary solution!!!)
APL_SEQNR_IN: in std_logic_vector (7 downto 0);
STAT : out std_logic_vector(31 downto 0)
);
APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS;
--APL_DATA_OUT <= reg_counter;
- CHECK_1:if TRANSFER_LENGTH >0 generate
+ CHECK_1:if TRANSFER_LENGTH >0 generate
APL_SHORT_TRANSFER_OUT <= '0';
end generate;
- CHECK_2:if TRANSFER_LENGTH =0 generate
+ CHECK_2:if TRANSFER_LENGTH =0 generate
APL_SHORT_TRANSFER_OUT <= '1';
end generate;
-
+
process(current_state)
begin
case current_state is
--create comb. real packet type
current_TYPE_IN <= APL_TYP_IN when (APL_PACKET_NUM_IN = "00" and RESET = '0')
else saved_PACKET_TYPE_IN;
-
+
SENDER_CTRL: process (current_state, APL_READ_IN, reg_counter, APL_RUN_IN, RESET, APL_TYP_IN,
packet_counter, buf_APL_SEND_OUT, current_TYPE_IN, APL_DATAREADY_IN, APL_PACKET_NUM_IN)
begin -- process
next_packet_counter <= "10";
elsif packet_counter = "10" then
next_APL_WRITE_OUT <= '1';
- next_APL_DATA_OUT <= reg_counter;
+ next_APL_DATA_OUT <= xor_all(APL_DATA_IN) & reg_counter(14 downto 0);
next_packet_counter <= "11";
elsif packet_counter <= "11" then
next_state <= IDLE;
end if;
end if;
end process;
-
+
end architecture;
end process;
end trb_net_dummy_apl_arch;
+
MED_CTRL_OP : out std_logic_vector (15 downto 0);
--Trigger Output
- LVL1_ERROR_PATTERN_OUT : out std_logic_vector(31 downto 0);
- LVL1_GOT_TRIGGER_OUT : out std_logic;
- LVL1_DTYPE_OUT : out std_logic_vector(3 downto 0);
- LVL1_SEQNR_OUT : out std_logic_vector(7 downto 0);
- LVL1_ERROR_PATTERN_IN : in std_logic_vector(31 downto 0);
- LVL1_RELEASE_IN : in std_logic;
+ TRG_TYPE_OUT : out std_logic_vector (3 downto 0);
+ TRG_NUMBER_OUT : out std_logic_vector (15 downto 0);
+ TRG_CODE_OUT : out std_logic_vector (7 downto 0);
+ TRG_INFORMATION_OUT : out std_logic_vector (15 downto 0);
+ TRG_RECEIVED_OUT : out std_logic;
+ TRG_RELEASE_IN : in std_logic;
+ TRG_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0);
-- Status and control port => just coming from the iobuf for debugging
STAT_GEN: out std_logic_vector (31 downto 0);
STAT: out STD_LOGIC_VECTOR (31 downto 0)
);
end component;
-component trb_net16_term is
+component trb_net16_trigger is
generic (
- USE_APL_PORT : integer range 0 to 1 := c_YES;
- --even when 0, ERROR_PACKET_IN is used for automatic replys
+ USE_TRG_PORT : integer range 0 to 1 := c_YES;
+ --even when NO, ERROR_PACKET_IN is used for automatic replys
SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE
--if secure_mode is not used, apl must provide error pattern and dtype until
- --next trigger comes in. In secure mode these need to be available while relase_trg is high
+ --next trigger comes in. In secure mode these need to be available while relase_trg is high only
);
port(
-- Misc
CLK_EN : in std_logic;
INT_DATAREADY_OUT: out std_logic;
- INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
+ INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0);
INT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
INT_READ_IN: in std_logic;
INT_DATAREADY_IN: in std_logic;
- INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
+ INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0);
INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
INT_READ_OUT: out std_logic;
- -- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT: out std_logic_vector (3 downto 0); -- see NewTriggerBusNetworkDescr
- APL_ERROR_PATTERN_OUT: out std_logic_vector (31 downto 0); -- see NewTriggerBusNetworkDescr
- APL_SEQNR_OUT: out std_logic_vector (7 downto 0);
- APL_GOT_TRM: out std_logic;
- APL_RELEASE_TRM: in std_logic;
- APL_ERROR_PATTERN_IN: in std_logic_vector (31 downto 0) -- see NewTriggerBusNetworkDescr
- -- Status and control port
- );
-end component;
-component trb_net16_term_buf is
- port(
- -- Misc
- CLK : in std_logic;
- RESET : in std_logic;
- CLK_EN : in std_logic;
-
- MED_INIT_DATAREADY_OUT: out std_logic;
- MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_INIT_READ_IN: in std_logic;
-
- MED_REPLY_DATAREADY_OUT: out std_logic;
- MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_REPLY_READ_IN: in std_logic;
-
- MED_DATAREADY_IN: in std_logic;
- MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
- MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
- MED_READ_OUT: out std_logic
+ -- Trigger information output
+ TRG_TYPE_OUT : out std_logic_vector (3 downto 0);
+ TRG_NUMBER_OUT : out std_logic_vector (15 downto 0);
+ TRG_CODE_OUT : out std_logic_vector (7 downto 0);
+ TRG_INFORMATION_OUT : out std_logic_vector (15 downto 0);
+ TRG_RECEIVED_OUT : out std_logic;
+ TRG_RELEASE_IN : in std_logic;
+ TRG_ERROR_PATTERN_IN : in std_logic_vector (31 downto 0)
);
-end component;
+ end component;
+ component trb_net16_term_buf is
+ port(
+ -- Misc
+ CLK : in std_logic;
+ RESET : in std_logic;
+ CLK_EN : in std_logic;
+
+ MED_INIT_DATAREADY_OUT: out std_logic;
+ MED_INIT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
+ MED_INIT_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_INIT_READ_IN: in std_logic;
+
+ MED_REPLY_DATAREADY_OUT: out std_logic;
+ MED_REPLY_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
+ MED_REPLY_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_REPLY_READ_IN: in std_logic;
+
+ MED_DATAREADY_IN: in std_logic;
+ MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word
+ MED_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ MED_READ_OUT: out std_logic
+ );
+ end component;
signal apl_to_buf_INIT_DATAREADY: std_logic;
signal apl_to_buf_INIT_DATA : std_logic_vector (15 downto 0);
signal MED_REPLY_PACKET_NUM_OUT : std_logic_vector (1 downto 0);
signal MED_REPLY_READ_IN : std_logic;
-signal m_DATAREADY_OUT : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
-signal m_DATA_OUT : std_logic_vector (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
-signal m_PACKET_NUM_OUT: std_logic_vector (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
-signal m_READ_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+ signal m_DATAREADY_OUT : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
+ signal m_DATA_OUT : std_logic_vector (c_DATA_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
+ signal m_PACKET_NUM_OUT: std_logic_vector (c_NUM_WIDTH*(2**c_MUX_WIDTH)-1 downto 0);
+ signal m_READ_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
-signal m_DATAREADY_IN : std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);
-signal m_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
-signal m_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
-signal m_READ_OUT : std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);
+ signal m_DATAREADY_IN : std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);
+ signal m_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
+ signal m_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ signal m_READ_OUT : std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);
begin
-------------------------------------------------
CTRL => MPLEX_CTRL
);
- trglvl1 : trb_net16_term
+ trglvl1 : trb_net16_trigger
generic map(
USE_APL_PORT => c_YES,
SECURE_MODE => std_TERM_SECURE_MODE
INT_READ_OUT => buf_to_apl_INIT_READ,
-- "mini" APL, just to see the triggers coming in
- APL_DTYPE_OUT => LVL1_DTYPE_OUT,
- APL_ERROR_PATTERN_OUT => LVL1_ERROR_PATTERN_OUT,
- APL_SEQNR_OUT => LVL1_SEQNR_OUT,
- APL_GOT_TRM => LVL1_GOT_TRIGGER_OUT,
- APL_RELEASE_TRM => LVL1_RELEASE_IN,
- APL_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN
+ TRG_TYPE_OUT => TRG_TYPE_OUT,
+ TRG_ERROR_PATTERN_OUT => TRG_ERROR_PATTERN_OUT,
+ TRG_NUMBER_OUT => TRG_NUMBER_OUT,
+ TRG_CODE_OUT => TRG_CODE_OUT,
+ TRG_INFORMATION_OUT => TRG_INFORMATION_OUT,
+ TRG_RECEIVED_OUT => TRG_RECEIVED_OUT,
+ TRG_RELEASE_IN => TRG_RELEASE_IN,
+ TRG_ERROR_PATTERN_IN => TRG_ERROR_PATTERN_IN
);
apl_to_buf_INIT_DATAREADY <= '0';
entity trb_net16_io_multiplexer is
-
port(
-- Misc
CLK : in std_logic;
end if;
end if;
end process;
-
+
g2: if USE_TRG_PORT = 1 generate
CLK_REG: process(CLK)
begin
---This entity provides data transfer (64bit) via a smaller (16bit) Bus
---with three bits for debugging (13bit data + 3bit control)
---first 56bit via Bus are for dataword, transmitted Bits 64 downto 56 Bits
---are for debugging
-
-
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.std_logic_ARITH.ALL;
RESET : in std_logic;
CLK_EN : in std_logic;
-- Internal direction port (MII)
- -- do not change this interface!!!
-- 1st part: from the medium to the internal logic (trbnet)
INT_DATAREADY_OUT: out STD_LOGIC; --Data word is reconstructed from media
--and ready to be read out (the IOBUF MUST read)
INT_PACKET_NUM_IN: in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0);
INT_READ_OUT: out STD_LOGIC; -- offered word is read
INT_ERROR_IN: in STD_LOGIC_VECTOR (2 downto 0); -- Status bits
- -- (end do not change this interface!!!)
-- Media direction port
signal packets_out_counter, next_packets_out_counter: std_logic_vector(3 downto 0);
signal last_MED_TRANSMISSION_CLK_IN : std_logic;
+ signal last_MED_FIRST_PACKET_IN : std_logic;
signal reg_MED_DATA_IN : std_logic_vector(7 downto 0);
signal reg_MED_TRANSMISSION_CLK_IN, reg_MED_CARRIER_IN : std_logic;
signal reg_MED_PARITY_IN : std_logic;
signal recv_counter : std_logic_vector(2 downto 0);
signal transmission_running, next_transmission_running : std_logic;
signal buf_MED_DATA_IN, next_buf_MED_DATA_IN : std_logic_vector(7 downto 0);
+
+
begin
INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT;
INT_DATA_OUT <= buf_INT_DATA_OUT;
-- MED_DATA_OUT(8) <= buf_INT_DATAREADY_OUT;
-- MED_DATA_OUT(9) <= INT_READ_IN;
-- MED_DATA_OUT(10)<= buf_INT_PACKET_NUM_OUT(0);
- MED_DATA_OUT(10 downto 8) <= buf_INT_DATA_OUT(2 downto 0);
+ MED_DATA_OUT(10 downto 8) <= buf_MED_DATA_IN(2 downto 0);
MED_DATA_OUT(11) <= not reset;
recv_counter <= "111";
elsif reg_MED_CARRIER_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_TRANSMISSION_CLK_IN = '1' then
recv_counter <= recv_counter + 1;
+ last_MED_FIRST_PACKET_IN <= reg_MED_FIRST_PACKET_IN;
+ if reg_MED_FIRST_PACKET_IN = '1' and last_MED_FIRST_PACKET_IN = '0' then
+ recv_counter <= "000";
+ end if;
end if;
end if;
end process;
buf_INT_PACKET_NUM_OUT)
begin
next_INT_DATA_OUT <= buf_INT_DATA_OUT;
- next_INT_DATAREADY_OUT <= buf_INT_DATAREADY_OUT;
+ next_INT_DATAREADY_OUT <= '0'; --buf_INT_DATAREADY_OUT;
next_buf_MED_DATA_IN <= buf_MED_DATA_IN;
next_INT_PACKET_NUM_OUT <= buf_INT_PACKET_NUM_OUT;
+-- if buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then
+-- next_INT_DATAREADY_OUT <= '0';
+-- end if;
+
if reg_MED_CARRIER_IN = '1' and last_MED_TRANSMISSION_CLK_IN = '0' and reg_MED_TRANSMISSION_CLK_IN = '1' then
- if recv_counter(0) = '1' then
+ if recv_counter(0) = '1' or (reg_MED_FIRST_PACKET_IN = '1' and last_MED_FIRST_PACKET_IN = '0') then
next_buf_MED_DATA_IN <= reg_MED_DATA_IN;
else
next_INT_DATA_OUT(7 downto 0) <= reg_MED_DATA_IN;
next_INT_DATAREADY_OUT <= '1';
end if;
end if;
- if buf_INT_DATAREADY_OUT = '1' and INT_READ_IN = '1' then
- next_INT_DATAREADY_OUT <= '0';
- end if;
-
end process;
if rising_edge(CLK) then
if RESET='1' then
buf_INT_DATAREADY_OUT <= '0';
- buf_INT_DATA_OUT <= (others => '0');
last_MED_TRANSMISSION_CLK_IN <= '1';
- buf_MED_DATA_IN <= (others => '0');
- buf_INT_PACKET_NUM_OUT <= "00";
else
buf_INT_DATA_OUT <= next_INT_DATA_OUT;
buf_INT_DATAREADY_OUT <= next_INT_DATAREADY_OUT;
LVDS_IN_reg: process(CLK)
begin
if rising_edge(CLK) then
- if RESET='1' then
- reg_MED_TRANSMISSION_CLK_IN <= '0';
- reg_MED_CARRIER_IN <= '0';
- reg_MED_PARITY_IN <= '0';
- reg_MED_DATA_IN <= (others => '0');
- reg_MED_FIRST_PACKET_IN <= '0';
- else
- reg_MED_TRANSMISSION_CLK_IN <= MED_DATA_IN(13);
- reg_MED_CARRIER_IN <= MED_DATA_IN(14);
- reg_MED_PARITY_IN <= MED_DATA_IN(15);
- reg_MED_DATA_IN <= MED_DATA_IN(7 downto 0);
- reg_MED_FIRST_PACKET_IN <= MED_DATA_IN(12);
- end if;
+ reg_MED_TRANSMISSION_CLK_IN <= MED_DATA_IN(13);
+ reg_MED_CARRIER_IN <= MED_DATA_IN(14);
+ reg_MED_PARITY_IN <= MED_DATA_IN(15);
+ reg_MED_DATA_IN <= MED_DATA_IN(7 downto 0);
+ reg_MED_FIRST_PACKET_IN <= MED_DATA_IN(12);
end if;
end process;
jspc29 / trbnet.git / commitdiff