added configuration register for trigger and clock fan-out

diff --git a/trb3/HardwareProject.tex b/trb3/HardwareProject.tex
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index 7afb333db38ca6c0f0c594d2d362ed9ecdbf1a77..ba0514a0d0842e1cd3d43a08a283911d5de7fb13 100644 (file)
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -196,6 +196,18 @@ The data stream contains SubEvent-IDs and SubSubEvent-IDs to identify the sender
 \item[C] Unpack as CTS data
 \item[5] The only SubSubEvent-ID starting with 5 is 5555 at the end of each SubEvent, marking the beginning of the status information word for this SubEvent.
 \end{description*}
+The data format is shown in later sections.
+
+
+\subsection{Trigger \& Clock Input}
+Both trigger and clock input (RJ-45 connectors) are equipped with a configurable fan-out chip. Its control signals can be set in slow-control register 0xd300 (currently in CTS only, but should also be present in other central FPGA).
+\begin{description*}
+ \item[Bit 0] Trigger select (local signal: 1, external signal: 0
+ \item[Bit 8] Clock select (Input 0 or 1)
+ \item[Bit 19 -- 16] 4 User signals on trigger fan-out
+ \item[Bit 27 -- 24] 4 User signals on clock fan-out
+\end{description*}
+
 
 
 %%% Local Variables: 

diff --git a/trb3/Trb3Hardware.tex b/trb3/Trb3Hardware.tex
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/trb3/main.tex b/trb3/main.tex
index 6757662521afa04eb41f57ea40c155f350ac5a24..dc46671ee768d68a7e199a31a9da91fdc02dfdf4 100644 (file)
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -141,7 +141,6 @@
     \input{Trb3GeneralRemarks}
 \cleardoublepage
 \part{Hardware}
-  \input{Trb3Hardware}
   \section{Measurements}
     \subsection{FPGA I/O Performance}
     \clearpage