-- Status
PCS_AN_READY_OUT : out std_logic; -- for internal SCTRL
LINK_ACTIVE_OUT : out std_logic; -- for internal SCTRL
+ TICK_MS_IN : in std_logic;
-- Debug
STATUS_OUT : out std_logic_vector(7 downto 0);
DEBUG_OUT : out std_logic_vector(63 downto 0)
signal delay_q : std_logic_vector(7 downto 0);
signal pulse : std_logic;
- signal led_timer : unsigned(19 downto 0);
- signal led_timer_done_x : std_logic;
- signal led_timer_done : std_logic;
signal led_activity_x : std_logic;
signal led_activity : std_logic_vector(1 downto 0);
hcs_n => tsm_hcs_n,
hwrite_n => tsm_hwrite_n,
hread_n => tsm_hread_n,
- ---------------- Input signals to the Tx MAC FIFO I/F ---------------
+ -------------gbe_trb/base/fwd_test_random.vhd--- Input signals to the Tx MAC FIFO I/F ---------------
tx_fifodata => mac_tx_data,
tx_fifoavail => mac_fifoavail,
tx_fifoeof => mac_fifoeof,
STATUS_OUT(2) <= an_complete; -- GbE Autonegotiation completed
STATUS_OUT(1) <= link_rx_ready; -- SerDes Rx channel operational
STATUS_OUT(0) <= link_tx_ready; -- SerDes TX channel operational
-
- THE_LED_TIMER_PROC: process( CLK_125 )
- begin
- if( rising_edge(CLK_125) ) then
- led_timer_done <= led_timer_done_x;
- led_timer <= led_timer + 1;
- end if;
- end process THE_LED_TIMER_PROC;
-
- led_timer_done_x <= '1' when (std_logic_vector(led_timer) = x"fffff") else '0';
led_activity_x <= pcs_rx_en or pcs_tx_en;
if( led_activity_x = '1' ) then
led_activity(0) <= '1';
end if;
- if( led_timer_done = '1' ) then
+ if( TICK_MS_IN = '1' ) then
led_activity <= led_activity(0) & '0';
end if;
end if;