newest version

diff --git a/cts_cal_screset_gen.vhd b/cts_cal_screset_gen.vhd
index ecf57b2dfdd3336883838ea8724b6a54de464e83..e0a28e9ba8e4714ab8a9e689f31e0cbade4d7c51 100644 (file)
--- a/cts_cal_screset_gen.vhd
+++ b/cts_cal_screset_gen.vhd
@@ -76,7 +76,7 @@ architecture cts_cal_screset_gen of cts_cal_screset_gen is
   --lvl1 self trigger
   signal lvl1_self_trigger : std_logic;
   signal self_trigg_cntr : std_logic_vector(27 downto 0):=x"0000000";
-
+  signal lvl1_cal_shw_pulse, lvl1_cal_shw_trigger : std_logic := '0';
 
 begin
 
@@ -99,10 +99,16 @@ begin
     if rising_edge(CLK) then  
       if RESET = '1' or GEN_FREQ_IN = 0 then
         lvl1_self_trigger <= '0';
+        lvl1_cal_shw_trigger <= '0';
       elsif self_trigg_cntr = GEN_FREQ_IN then
         lvl1_self_trigger <= '1';
+        lvl1_cal_shw_trigger <= '0';
+      elsif self_trigg_cntr = GEN_FREQ_IN - 10 then
+        lvl1_self_trigger <= '0';
+        lvl1_cal_shw_trigger <= '1';
       else
         lvl1_self_trigger <= '0';
+        lvl1_cal_shw_trigger <= '0';
       end if;
     end if;
   end process SET_LVL1_SELF_TRIGGER;
@@ -113,7 +119,14 @@ begin
       en_clk    => '1',
       signal_in => lvl1_self_trigger,
       pulse     => GEN_OUT);
-  
+
+  GEN_SHW_CAL_PULSE: edge_to_pulse
+    port map (
+      clock     => CLK,
+      en_clk    => '1',
+      signal_in => lvl1_cal_shw_trigger,
+      pulse     => lvl1_cal_shw_pulse);
+
 --  GEN_OUT <= lvl1_self_trigger;
   
   
@@ -220,7 +233,7 @@ one_second_cntr_reset <= RESET or one_second_reset;
     if rising_edge(CLK) then
       if SEND_CAL_CURRENT = SEND_CAL_SHOWER or reset = '1' then
         shower_cal_mark <= '0';
-      elsif SHOWER_CAL_ENABLE_IN = '1' then
+      elsif SHOWER_CAL_ENABLE_IN = '1' and lvl1_cal_shw_pulse = '1' then
         shower_cal_mark <= '1';
       end if;
     end if;

diff --git a/cts_fpga1.lpf b/cts_fpga1.lpf
index ff3201d6440dbf8eb569e3358c3d2f1a8714a623..3632bc013fb98327467ab916475ee7c0dcee2080 100644 (file)
--- a/cts_fpga1.lpf
+++ b/cts_fpga1.lpf
@@ -8,6 +8,12 @@ BLOCK ASYNCPATHS ;
 
 IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ;
 
+#################################################################
+# SPI CLK
+#################################################################
+
+SYSCONFIG MCCLK_FREQ = 20;
+
 #################################################################
 # Clock I/O
 #################################################################

diff --git a/cts_fpga1.vhd b/cts_fpga1.vhd
index 92fb615ed5dbe5964ce116d7c4c4ef04964ca4dc..464f16a4883f651a3892811c9902b4b2bb194b07 100644 (file)
--- a/cts_fpga1.vhd
+++ b/cts_fpga1.vhd
@@ -7,11 +7,11 @@ library work;
 --use work.trb_net_std.all;
 --use work.trb_net_components.all;
 -- use work.trb_net16_hub_func.all;
-use work.version.all;
+use work.version.all;                   --no_sim--
 use work.cts_components.all;
 library SC;
 use SC.COMPONENTS.all;
-use ieee.std_logic_arith.all;
+use ieee.std_logic_arith.all; 
 
 entity cts_fpga1 is
   generic(

diff --git a/cts_fpga1_compile.pl b/cts_fpga1_compile.pl
index 7c101516a7c18bd92908be9e26ca17921ddfb2bd..97c417b8f58881058210df12c5900a2787fa10db 100755 (executable)
--- a/cts_fpga1_compile.pl
+++ b/cts_fpga1_compile.pl
@@ -14,8 +14,8 @@ use warnings;
 use strict;
 
 #my $lattice_path = '/opt/lattice/ispLEVER8.0/isptools/';
-#my $lattice_path = '/opt/lattice/ispLEVER8.0/isptools/';
-my $lattice_path = '/opt/lattice/diamond/1.3/';
+my $lattice_path = '/opt/lattice/ispLEVER8.0/isptools/';
+#my $lattice_path = '/opt/lattice/diamond/1.3/';
 #my $lattice_path = '/opt/lattice/diamond/1.3/';
 #my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/';
 #my $synplify_path = '/opt/synplicity/D-2009.12/bin/';

diff --git a/cts_fpga1_test.vhd b/cts_fpga1_test.vhd
index e02f8b9d430544f0dd6f7dc09edfd7e84d58c1da..4a4af1b8ba2732f78b401dfa908d02bcdf0265ad 100644 (file)
--- a/cts_fpga1_test.vhd
+++ b/cts_fpga1_test.vhd
@@ -6,6 +6,7 @@ use ieee.numeric_std.all;
 use ieee.std_logic_arith.all;
 
 
+
 entity cts_fpga1_test is
   generic(
     RW_REGISTERS_NUMBER  : integer range 0 to 26  := 26;
@@ -27,7 +28,7 @@ entity cts_fpga1_test is
 --    LED_ORANGE          : out std_logic;
 --    LED_RED             : out std_logic;
 --    LED_YELLOW          : out std_logic;
---    TRB2_OK_LED         : out std_logic;
+--    TRB2_OK_LED          : out std_logic;
 --    TRB2_RX_LED         : out std_logic;
 --    TRB2_TX_LED         : out std_logic;
 --    TRB3_OK_LED         : out std_logic;
@@ -38,6 +39,7 @@ entity cts_fpga1_test is
 --    TEST_LINE           : out std_logic_vector(31 downto 0)
     );
 
+  
     attribute syn_useioff : boolean;
 --    attribute syn_useioff of ADO_TTL              : signal is true;
     attribute syn_useioff of TRIG_OUT              : signal is true;

diff --git a/cts_fpga1_to_fpga2.vhd b/cts_fpga1_to_fpga2.vhd
index 060b88b93de9a77ae0344c5d225c12be86089fba..6cdadc1d1d2be3e674e6e0689c17f47f4730e7b4 100644 (file)
--- a/cts_fpga1_to_fpga2.vhd
+++ b/cts_fpga1_to_fpga2.vhd
@@ -158,9 +158,16 @@ begin
       if RESET = '1' then
         lvl1_info_data <= (others => '0');
       elsif LVL1_TRIGGER_IN = '1' then
-        lvl1_info_data <= x"00" & LVL1_INFO_IN & LVL1_RND_CODE_IN &
-                          x"0000000" & LVL1_CODE_IN &
-                          x"0000" & LVL1_TRIGGER_TAG_IN;
+        --changed 2014 apr start
+       --was lvl1_info_data <= x"00" & LVL1_INFO_IN & LVL1_RND_CODE_IN &
+       --was                   x"0000000" & LVL1_CODE_IN &
+       --was                   x"0000" & LVL1_TRIGGER_TAG_IN;
+       --
+         lvl1_info_data <= 
+                           x"00000000" &
+                           x"0000" & LVL1_TRIGGER_TAG_IN &
+                           x"0" & LVL1_CODE_IN & LVL1_INFO_IN & LVL1_RND_CODE_IN;
+         --changed 2014 apr end
       end if;
     end if;
   end process SAVE_LVL1_INFO;

diff --git a/cts_fpga1_trb_no_fpga.xcf b/cts_fpga1_trb_no_fpga.xcf
index 94795dc3a4c327b12cfe584128b4e44cf9ee5085..306601ba1e434c831b6ed08089e5743d137d94d4 100644 (file)
--- a/cts_fpga1_trb_no_fpga.xcf
+++ b/cts_fpga1_trb_no_fpga.xcf
@@ -19,8 +19,8 @@
                                <BScanLen>1</BScanLen>
                                <BScanVal>0</BScanVal>
                        </Bypass>
-                       <File>/home/marek/ctsaddon/workdir/cts_fpga1.bit</File>
-                       <FileTime>10/5/2010 11:15:23</FileTime>
+                       <File>/home/marek/ctsaddon/workdir/cts_fpga1_22042014.bit</File>
+                       <FileTime>4/22/2014 14:12:40</FileTime>
                        <Operation>Fast Program</Operation>
                        <Option>
                                <SVFVendor>JTAG STANDARD</SVFVendor>
@@ -48,7 +48,9 @@
                                <BScanLen>1</BScanLen>
                                <BScanVal>0</BScanVal>
                        </Bypass>
+                       <File>/home/marek/ctsaddon/workdir/cts_fpga2.bit</File>
                        <MaskFile>/home/marek/.isplever_lin/ispvmsystem/Database/xpga/ecp2/ecp2m-100.msk</MaskFile>
+                       <FileTime>4/12/2014 14:21:11</FileTime>
                        <Operation>Bypass</Operation>
                        <Option>
                                <SVFVendor>JTAG STANDARD</SVFVendor>
@@ -58,6 +60,7 @@
                                <OverideUES value="TRUE"/>
                                <TCKFrequency>1.000000 MHz</TCKFrequency>
                                <SVFProcessor>SVF Processor</SVFProcessor>
+                               <Usercode>0x00000000</Usercode>
                                <AccessMode>JTAG</AccessMode>
                        </Option>
                </Device>

diff --git a/cts_fpga2.lpf b/cts_fpga2.lpf
index d3da9cb3761717ed5f334e5100597ce653ba3912..ed1eda0e27398dce98f3688aef74b4a150b3c006 100644 (file)
--- a/cts_fpga2.lpf
+++ b/cts_fpga2.lpf
@@ -6,6 +6,11 @@ BLOCK RESETPATHS ;
 BLOCK ASYNCPATHS ;
 IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ;
 
+#################################################################
+# SPI CLK
+#################################################################
+
+SYSCONFIG MCCLK_FREQ = 20;
 
 #################################################################
 # Clock

diff --git a/cts_fpga2_compile.pl b/cts_fpga2_compile.pl
index 986a987d52a3edeec4c0fa6b6dafc99e156b0cb3..68b0c30a268e3145f96b5db76887a3417aebc704 100755 (executable)
--- a/cts_fpga2_compile.pl
+++ b/cts_fpga2_compile.pl
@@ -12,8 +12,8 @@ use Data::Dumper;
 
 use warnings;
 use strict;
-my $lattice_path = '/opt/lattice/diamond/1.3/';
-#my $lattice_path = '/opt/lattice/ispLEVER8.0/isptools/';
+#my $lattice_path = '/opt/lattice/diamond/1.3/';
+my $lattice_path = '/opt/lattice/ispLEVER8.0/isptools/';
 #my $synplify_path = '/d/sugar/lattice/synplify/syn96L3/synplify_linux/';
 #my $synplify_path = '/opt/synplicity/D-2009.12/bin/';
 #my $synplify_path = '/opt/synplicity/D-2010.03-SP1-1/bin/';

diff --git a/cts_fpga2_to_fpga1.vhd b/cts_fpga2_to_fpga1.vhd
index f8d39b7eaf61dc637f489e91c1b54b039667b3b4..fd86a44ef1d0f3a894bce1d087f6b7f23f888026 100644 (file)
--- a/cts_fpga2_to_fpga1.vhd
+++ b/cts_fpga2_to_fpga1.vhd
@@ -86,12 +86,13 @@ architecture cts_fpga2_to_fpga1 of cts_fpga2_to_fpga1 is
       SIGNAL_VECTOR_OUT : out std_logic_vector(VECTOR_WIDTH - 1 downto 0));
   end component;
   
-  type LVL1 is (IDLE, LVL1_TAKE_INFO_A, LVL1_TAKE_INFO_B, LVL1_TAKE_INFO_C, LVL1_SEND_DATA_A, LVL1_SEND_DATA_B);
+  type LVL1 is (IDLE, LVL1_TAKE_INFO_A, LVL1_TAKE_INFO_B, LVL1_TAKE_INFO_C, LVL1_SEND_DATA_A, LVL1_SEND_DATA_B, WAIT_FOR_FIFO_READOUT_A, WAIT_FOR_FIFO_READOUT_B);
   signal LVL1_CURRENT, LVL1_NEXT : LVL1;
   signal lvl1_rcnt_out_i : std_logic_vector(9 downto 0);
   signal lvl1_rd_en_in_i, lvl1_rd_en_in_fsm: std_logic;
   signal lvl1_rd_en_in_pulse : std_logic_vector(3 downto 0);
-  signal lvl1_data_valid_out_fsm : std_logic;
+  signal lvl1_data_valid_out_fsm, save_info_fsm, save_info, save_info_a, save_info_b, trigg_tag_cntr_up : std_logic;
+  signal trigg_tag_cntr : std_logic_vector(15 downto 0);
   signal lvl1_data_valid_out_i, lvl1_data_valid_out_align : std_logic_vector(0 downto 0);
   
   signal lvl1_delay_in, lvl1_delay_out_align : std_logic_vector(1 downto 0);
@@ -163,7 +164,7 @@ begin
       SIGNAL_VECTOR_OUT => lvl1_delay_out_align);
 
   
-  LVL1_TRIGGER_OUT <= lvl1_trigger_out_delayed(0);
+  --was 2014 apr LVL1_TRIGGER_OUT <= lvl1_trigger_out_delayed(0);
   LVL1_DATA_VALID_OUT <= lvl1_delay_out_align(0);
   LVL1_TRIGGER_RELEASE_OUT <= lvl1_trigger_release_out_i;
   LVL1_DATA_FINISHED_OUT <= lvl1_delay_out_align(1);
@@ -178,13 +179,22 @@ begin
         lvl1_trigger_out_i(0) <= '0';
         lvl1_trigger_release_out_i <= '0';
         lvl1_data_finished_out_i <= '0';
+        save_info <= '0';
+        trigg_tag_cntr_up <= '0';
+        LVL1_TRIGGER_OUT <= '0';
       else
         LVL1_CURRENT   <= LVL1_NEXT;
         lvl1_rd_en_in_i   <= lvl1_rd_en_in_fsm;
         lvl1_delay_in(0) <= lvl1_data_valid_out_fsm;
-        lvl1_trigger_out_i(0) <= lvl1_trigger_out_fsm;
+        --was 2014 apr lvl1_trigger_out_i(0) <= lvl1_trigger_out_fsm;
         lvl1_trigger_release_out_i <= lvl1_trigger_release_out_fsm;
         lvl1_delay_in(1) <= lvl1_data_finished_out_fsm;
+        save_info <= save_info_fsm;
+        save_info_a <= save_info;
+        save_info_b <= save_info_a;
+        LVL1_TRIGGER_OUT <= save_info_b;
+        trigg_tag_cntr_up <= lvl1_data_finished_out_fsm;
+        
       end if;
     end if;
   end process LVL1_CLK;
@@ -196,19 +206,28 @@ begin
     lvl1_trigger_out_fsm <= '0';
     lvl1_trigger_release_out_fsm <= '0';
     lvl1_data_finished_out_fsm <= '0';
-    
+    save_info_fsm <= '0';
     case (LVL1_CURRENT) is
       
       when IDLE      =>
-        if lvl1_rcnt_out_i = 4 then
+       --2014 apr was if lvl1_rcnt_out_i = 4 then
+        if lvl1_rcnt_out_i = 1 then
+          lvl1_rd_en_in_fsm <= '1';
+          save_info_fsm <= '1';
           LVL1_NEXT <= LVL1_TAKE_INFO_A;
         else
+          lvl1_rd_en_in_fsm <= '0';
+          save_info_fsm <= '0';
           LVL1_NEXT <= IDLE;
         end if;
         
       when LVL1_TAKE_INFO_A =>
-        lvl1_rd_en_in_fsm <= '1';
-        LVL1_NEXT <= LVL1_TAKE_INFO_B;
+        
+        if lvl1_rcnt_out_i = 3 then
+          LVL1_NEXT <= LVL1_TAKE_INFO_B;
+        else
+          LVL1_NEXT <= LVL1_TAKE_INFO_A;
+        end if;
         
       when LVL1_TAKE_INFO_B =>
         lvl1_rd_en_in_fsm <= '1';
@@ -230,12 +249,17 @@ begin
       when LVL1_SEND_DATA_B =>
         if lvl1_rcnt_out_i = 2 then
           lvl1_data_finished_out_fsm <= '1';
-          LVL1_NEXT <= IDLE;
+          LVL1_NEXT <= WAIT_FOR_FIFO_READOUT_A;
         else
           lvl1_rd_en_in_fsm <= '1';
           lvl1_data_valid_out_fsm <= '1';
           LVL1_NEXT <= LVL1_SEND_DATA_B;
         end if;
+      when WAIT_FOR_FIFO_READOUT_A =>
+        LVL1_NEXT <= WAIT_FOR_FIFO_READOUT_B;
+      when WAIT_FOR_FIFO_READOUT_B =>
+        LVL1_NEXT <= IDLE;
+        
         
       when others    =>
         LVL1_NEXT <= IDLE;
@@ -290,25 +314,53 @@ begin
       end if;
     end if;
   end process  LVL1_PULSES_FOR_SAVING_INFO;
+  
+--was 2014 apr
+--  THE_LVL1_SAVE_INFO: for i in 0 to 2 generate
+--    LVL1_SAVE_INFO : process (CLK, RESET)
+--    begin
+--      if rising_edge(CLK) then
+--        if RESET = '1' then
+--          lvl1_info(i) <= (others => '0');
+--        elsif lvl1_rd_en_in_pulse(i) = '1'  then
+--          lvl1_info(i) <= lvl1_data_out_sync;
+--        end if;
+--      end if;
+--    end process LVL1_SAVE_INFO;
+--  end generate THE_LVL1_SAVE_INFO;
 
-  THE_LVL1_SAVE_INFO: for i in 0 to 2 generate
-    LVL1_SAVE_INFO : process (CLK, RESET)
-    begin
-      if rising_edge(CLK) then
-        if RESET = '1' then
-          lvl1_info(i) <= (others => '0');
-        elsif lvl1_rd_en_in_pulse(i) = '1'  then
-          lvl1_info(i) <= lvl1_data_out_sync;
-        end if;
+  SAVE_INFO_PROC : process (CLK, RESET)
+  begin
+    if rising_edge(CLK) then
+      if RESET = '1' then
+        lvl1_info(0) <= (others => '0');
+      elsif save_info_b = '1' then
+        lvl1_info(0) <= lvl1_data_out_i;
+      else
+        lvl1_info(0) <= lvl1_info(0);
+      end if;
+    end if;
+  end process SAVE_INFO_PROC;
+  --changed apr 2014 start
+  TRIGG_TAG_CNTR_PROC : process (CLK, RESET)
+  begin
+    if rising_edge(CLK) then
+      if RESET = '1' then
+        trigg_tag_cntr <= (others => '0');
+      elsif trigg_tag_cntr_up = '1' then
+        trigg_tag_cntr <= trigg_tag_cntr + 1;
+      else
+        trigg_tag_cntr <= trigg_tag_cntr;
       end if;
-    end process LVL1_SAVE_INFO;
-  end generate THE_LVL1_SAVE_INFO;
+    end if;
+  end process TRIGG_TAG_CNTR_PROC;
   
-  LVL1_INFO_OUT <= lvl1_info(2)(23 downto 8);
-  LVL1_RND_CODE_OUT  <= lvl1_info(2)(7 downto 0);
-  LVL1_CODE_OUT  <= lvl1_info(1)(3 downto 0);
-  LVL1_TRIGGER_TAG_OUT <= lvl1_info(0)(15 downto 0);
-
+  LVL1_INFO_OUT <= lvl1_info(0)(23 downto 8);
+  LVL1_RND_CODE_OUT  <= lvl1_info(0)(7 downto 0);
+  LVL1_CODE_OUT  <= lvl1_info(0)(27 downto 24);
+  --was LVL1_TRIGGER_TAG_OUT <= lvl1_info(1)(15 downto 0);
+  LVL1_TRIGGER_TAG_OUT <= trigg_tag_cntr;
+  --changed apr 2014 end
 -------------------------------------------------------------------------------
 -- lvl2
 -------------------------------------------------------------------------------

diff --git a/cts_fpga2_trb_fpga_on.xcf b/cts_fpga2_trb_fpga_on.xcf
index 3b4db582596162b1fd94b5e2e82821628dc6d154..2c1a295c89b0489055b0deb1f3a60f1b67961b80 100644 (file)
--- a/cts_fpga2_trb_fpga_on.xcf
+++ b/cts_fpga2_trb_fpga_on.xcf
@@ -70,7 +70,7 @@
                        </Bypass>
                        <File>/home/marek/ctsaddon/workdir/cts_fpga2.bit</File>
                        <MaskFile>/home/marek/.isplever_lin/ispvmsystem/Database/xpga/ecp2/ecp2m-100.msk</MaskFile>
-                       <FileTime>8/13/2010 0:0:41</FileTime>
+                       <FileTime>4/12/2014 14:21:11</FileTime>
                        <Operation>Fast Program</Operation>
                        <Option>
                                <SVFVendor>JTAG STANDARD</SVFVendor>

diff --git a/cts_fpga2_trb_no_fpga.xcf b/cts_fpga2_trb_no_fpga.xcf
index 33098913886b136bf3c43b6b8d2af4e635aaf7e5..403b23642d42e3770b2f3479ea2d59b774cf4505 100644 (file)
--- a/cts_fpga2_trb_no_fpga.xcf
+++ b/cts_fpga2_trb_no_fpga.xcf
@@ -48,7 +48,7 @@
                        </Bypass>
                        <File>/home/marek/ctsaddon/workdir/cts_fpga2.bit</File>
                        <MaskFile>/home/marek/.isplever_lin/ispvmsystem/Database/xpga/ecp2/ecp2m-100.msk</MaskFile>
-                       <FileTime>1/4/2012 15:5:51</FileTime>
+                       <FileTime>4/12/2014 14:21:11</FileTime>
                        <Operation>Fast Program</Operation>
                        <Option>
                                <SVFVendor>JTAG STANDARD</SVFVendor>

diff --git a/cts_simulation_tb.mpf b/cts_simulation_tb.mpf
index 2c673a2be01457c843380b31729f3a20b835ce63..f97bab91e0541658dae32d3316b2ce16b7c2d240 100644 (file)
--- a/cts_simulation_tb.mpf
+++ b/cts_simulation_tb.mpf
@@ -37,11 +37,11 @@ mc2_lib = $MODEL_TECH/../mc2_lib
 ;mvc_lib = $MODEL_TECH/../mvc_lib
 
 work = work
-sc = /opt/lattice/diamond/1.3/ispfpga/vhdl/data/orca5/mti/work
-scm = /opt/lattice/diamond/1.3/ispfpga/vhdl/data/orca5/mti/work
-pcsc_work = /opt/lattice/diamond/1.3/ispfpga/vhdl/data/orca5/mti/work
 ecp2 = /opt/lattice/diamond/1.3/ispfpga/vhdl/data/ecp2/mti/work
 ecp2m = /opt/lattice/diamond/1.3/ispfpga/vhdl/data/ecp2/mti/work
+pcsc_work = /opt/lattice/ispLEVER8.1/isptools/ispfpga/vhdl/data/orca5/mti/work
+scm = /opt/lattice/ispLEVER8.1/isptools/ispfpga/vhdl/data/orca5/mti/work
+sc = /opt/lattice/ispLEVER8.1/isptools/ispfpga/vhdl/data/orca5/mti/work
 [vcom]
 ; VHDL93 variable selects language version as the default. 
 ; Default is VHDL-2002.
@@ -1565,9 +1565,9 @@ Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 v
 Project_File_7 = /home/marek/trbnet/special/spi_master.vhd
 Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1286546951 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 112 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_8 = /home/marek/trbnet/trb_net_priority_arbiter.vhd
-Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232546052 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 94 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 94 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_9 = /home/marek/ctsaddon/simulation/cts_cal_screset_gen.vhd
-Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1398167587 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_10 = /home/marek/ctsaddon/simulation/ram_register.vhd
 Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_11 = /home/marek/trbnet/lattice/ecp2m/trb_net_clock_generator.vhd
@@ -1575,31 +1575,31 @@ Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
 Project_File_12 = /home/marek/trbnet/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd
 Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249570868 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 67 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_13 = /home/marek/ctsaddon/fifo12bit_synch.vhd
-Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329309772 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 141 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329309772 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 139 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_14 = /home/marek/trbnet/trb_net_sbuf6.vhd
-Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 97 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 97 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_15 = /home/marek/ctsaddon/simulation/cts_fpga2_reg_interface.vhd
-Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332007582 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 35 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1397105384 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 35 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_16 = /home/marek/ctsaddon/simulation/delay.vhd
-Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331907215 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 138 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1331907215 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 136 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_17 = /home/marek/trbnet/special/handler_trigger_and_data.vhd
 Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1296638933 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 110 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_18 = /home/marek/trbnet/trb_net16_term.vhd
-Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1237891031 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 54 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 54 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_19 = /home/marek/trbnet/trb_net_dummy_fifo.vhd
-Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600670 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 92 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 92 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_20 = /home/marek/trbnet/trb_net_sbuf.vhd
-Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 96 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 96 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_21 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x512_oreg.vhd
 Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 88 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_22 = /home/marek/trbnet/lattice/ecp2m/dll_in100_out100.vhd
 Project_File_P_22 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292267 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 66 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_23 = /home/marek/ctsaddon/simulation/cts_fpga1_to_fpga2.vhd
-Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 32 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_23 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1397105384 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 32 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_24 = /home/marek/ctsaddon/fifo52bit_synch.vhd
-Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329503624 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 142 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_24 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329503624 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 140 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_25 = /home/marek/trbnet/trb_net16_endpoint_hades_full_handler.vhd
-Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 100 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_25 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365763 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 100 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_26 = /home/marek/ctsaddon/simulation/pll_in200_out40.vhd
 Project_File_P_26 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 16 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_27 = /home/marek/ctsaddon/simulation/ddr2_16inputs.vhd
@@ -1607,55 +1607,55 @@ Project_File_P_27 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
 Project_File_28 = /home/marek/ctsaddon/simulation/cts_width_rom.vhd
 Project_File_P_28 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_29 = /home/marek/trbnet/special/handler_lvl1.vhd
-Project_File_P_29 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014417 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 109 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_29 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1314708131 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 109 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_30 = /home/marek/trbnet/trb_net16_sbuf.vhd
-Project_File_P_30 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1295625509 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 107 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_30 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 107 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_31 = /home/marek/trbv2/f_divider.vhd
 Project_File_P_31 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1259846036 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 115 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_32 = /home/marek/ctsaddon/simulation/scm_fifo_16bit_to_32bit.vhd
 Project_File_P_32 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 23 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_33 = /home/marek/trbnet/trb_net16_obuf_nodata.vhd
-Project_File_P_33 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1248956644 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 53 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_33 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 53 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_34 = /home/marek/ctsaddon/simulation/cts_fpga2_to_fpga1.vhd
-Project_File_P_34 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 36 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_34 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1398167513 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 36 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_35 = /home/marek/ctsaddon/simulation/cts_fpga2.vhd
-Project_File_P_35 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 123 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_35 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1398167587 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 143 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_36 = /home/marek/ctsaddon/simulation/cts_eb_ip_switch.vhd
 Project_File_P_36 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 31 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_37 = /home/marek/ctsaddon/simulation/cts_witdh_rom_simulation.vhd
-Project_File_P_37 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321880898 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 131 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_37 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321880898 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 129 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_38 = /home/marek/trbnet/special/spi_databus_memory.vhd
 Project_File_P_38 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1268245488 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 111 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_39 = /home/marek/trbnet/special/spi_slim.vhd
-Project_File_P_39 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321875807 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 129 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_39 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1397106421 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 142 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_40 = /home/marek/trbnet/trb_net16_term_buf.vhd
-Project_File_P_40 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292102 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 55 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_40 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 55 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_41 = /home/marek/trbnet/basics/pulse_stretch.vhd
-Project_File_P_41 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1277977616 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 127 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_41 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1277977616 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 126 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_42 = /home/marek/trbnet/trb_net16_iobuf.vhd
-Project_File_P_42 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1285861828 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 103 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_42 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365763 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 103 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_43 = /home/marek/trbnet/trb_net16_regIO.vhd
-Project_File_P_43 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1295344067 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 105 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_43 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 105 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_44 = /home/marek/trbnet/trb_net16_ibuf.vhd
-Project_File_P_44 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 101 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_44 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365763 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 101 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_45 = /home/marek/ctsaddon/simulation/trb_net16_med_ecp_sfp_gbe.vhd
-Project_File_P_45 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 117 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_45 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1398167587 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 117 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_46 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x256_oreg.vhd
 Project_File_P_46 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 78 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_47 = /home/marek/ctsaddon/simulation/cts_beam_structure.vhd
-Project_File_P_47 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325766507 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 134 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_47 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1397105384 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 132 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_48 = /home/marek/trbnet/trb_net16_ipudata.vhd
-Project_File_P_48 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760358 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 52 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_48 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365763 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 52 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_49 = /home/marek/ctsaddon/simulation/cts_fpga2_trig_gen.vhd
 Project_File_P_49 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454097 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 37 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_50 = /home/marek/trbnet/trb_net_CRC.vhd
-Project_File_P_50 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1235046634 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 91 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_50 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 91 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_51 = /home/marek/ctsaddon/simulation/ddr2_busses.vhd
-Project_File_P_51 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 133 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_51 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1398167587 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 131 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_52 = /home/marek/trbnet/trb_net16_io_multiplexer.vhd
-Project_File_P_52 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1285861828 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 102 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_52 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365763 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 102 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_53 = /home/marek/trbnet/lattice/ecp2m/spi_dpram_32_to_8.vhd
-Project_File_P_53 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 71 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_53 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1316008498 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 71 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_54 = /home/marek/ctsaddon/simulation/delay_fifo.vhd
 Project_File_P_54 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_55 = /home/marek/ctsaddon/simulation/ddr2_3out_clkdiv.vhd
@@ -1667,7 +1667,7 @@ Project_File_P_57 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
 Project_File_58 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x16_media_interface.vhd
 Project_File_P_58 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1275387240 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 77 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_59 = /home/marek/trbnet/trb_net16_api_base.vhd
-Project_File_P_59 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 98 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_59 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365763 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 98 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_60 = /home/marek/ctsaddon/simulation/pll_in200_out400.vhd
 Project_File_P_60 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329672874 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_61 = /home/marek/ctsaddon/simulation/cts_fpga2_reg_mem.vhd
@@ -1675,25 +1675,25 @@ Project_File_P_61 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
 Project_File_62 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x1k_oreg.vhd
 Project_File_P_62 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 75 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_63 = /home/marek/trbnet/trb_net16_endpoint_hades_cts.vhd
-Project_File_P_63 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321875836 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 130 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_63 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365763 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 128 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_64 = /home/marek/ctsaddon/simulation/cts_readout.vhd
 Project_File_P_64 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332007582 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_65 = /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_all.vhd
 Project_File_P_65 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1248958666 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 122 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_66 = /home/marek/trbnet/trb_net16_dummy_fifo.vhd
-Project_File_P_66 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600670 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 51 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_66 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365763 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 51 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_67 = /home/marek/trbnet/trb_net_onewire_listener.vhd
-Project_File_P_67 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872784 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 126 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_67 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 125 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_68 = /home/marek/ctsaddon/simulation/cts_set_width_large.vhd
-Project_File_P_68 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 27 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_68 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1397105384 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 27 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_69 = /home/marek/trbnet/trb_net_pattern_gen.vhd
-Project_File_P_69 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1214858855 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 93 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_69 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 93 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_70 = /home/marek/ctsaddon/simulation/ecp2m_lvl2_trigger_buffer_fifo_1kW.vhd
 Project_File_P_70 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 41 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_71 = /home/marek/ctsaddon/simulation/dll_in400_out200.vhd
 Project_File_P_71 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329672874 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_72 = /home/marek/ctsaddon/simulation/cts_components.vhd
-Project_File_P_72 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329672874 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_72 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1397105384 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 1 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_73 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x4k_oreg.vhd
 Project_File_P_73 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760376 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 83 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_74 = /home/marek/trbnet/special/trb_net_reset_handler.vhd
@@ -1707,7 +1707,7 @@ Project_File_P_77 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
 Project_File_78 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_18x1k.vhd
 Project_File_P_78 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1242817604 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 70 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_79 = /home/marek/trbnet/trb_net_onewire.vhd
-Project_File_P_79 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872769 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 125 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_79 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 124 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_80 = /home/marek/ctsaddon/simulation/fifo_2bit_to_32bit.vhd
 Project_File_P_80 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 43 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_81 = /home/marek/trbv2/etrax_write_read_tb.vhd
@@ -1717,9 +1717,9 @@ Project_File_P_82 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
 Project_File_83 = /home/marek/ctsaddon/simulation/scm_fifo_1bit_to_32bit.vhd
 Project_File_P_83 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_84 = /home/marek/ctsaddon/cts_fpga1_test.vhd
-Project_File_P_84 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329672862 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 136 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_84 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1398167648 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 134 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_85 = /home/marek/trbnet/trb_net16_regio_bus_handler.vhd
-Project_File_P_85 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 106 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_85 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 106 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_86 = /home/marek/ctsaddon/simulation/scm_fifo_2bit_to_32bit.vhd
 Project_File_P_86 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 20 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_87 = /home/marek/ctsaddon/simulation/fifo_4bit_to_32bit.vhd
@@ -1731,9 +1731,9 @@ Project_File_P_89 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
 Project_File_90 = /home/marek/trbnet/media_interfaces/ecp2m_sfp/serdes_gbe_0.vhd
 Project_File_P_90 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1249891632 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 121 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_91 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo.vhd
-Project_File_P_91 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1282206842 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 68 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_91 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1334944108 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 68 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_92 = /home/marek/trbnet/trb_net_sbuf5.vhd
-Project_File_P_92 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 48 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_92 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 48 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_93 = /home/marek/ctsaddon/simulation/scm_fifo_4bit_to_32bit.vhd
 Project_File_P_93 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_94 = /home/marek/trbnet/media_interfaces/trb_net16_med_ecp_sfp_4_gbe.vhd
@@ -1743,21 +1743,21 @@ Project_File_P_95 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
 Project_File_96 = /home/marek/trbnet/special/handler_ipu.vhd
 Project_File_P_96 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1304089906 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 108 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_97 = /home/marek/ctsaddon/simulation/version.vhd
-Project_File_P_97 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332007582 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_97 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1398167513 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_98 = /home/marek/ctsaddon/simulation/fifo16bit_synch.vhd
 Project_File_P_98 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_99 = /home/marek/ctsaddon/ddr2_13out_clkdiv.vhd
-Project_File_P_99 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329503926 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 140 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_99 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1329503926 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 138 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_100 = /home/marek/ctsaddon/simulation/fifo_8bit_to_32bit.vhd
 Project_File_P_100 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 45 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_101 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_8b_16b_dualport.vhd
 Project_File_P_101 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1278661530 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 69 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_102 = /home/marek/ctsaddon/simulation/cts_fpga1_test_set_width.vhd
-Project_File_P_102 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689053 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 124 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_102 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689053 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 123 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_103 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x32k_oreg.vhd
 Project_File_P_103 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760373 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 86 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_104 = /home/marek/trbnet/trb_net_priority_encoder.vhd
-Project_File_P_104 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1203091968 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 95 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_104 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 95 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_105 = /home/marek/ctsaddon/simulation/scm_fifo_8bit_to_32bit.vhd
 Project_File_P_105 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 22 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_106 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_lvl2_fifo.vhd
@@ -1765,15 +1765,15 @@ Project_File_P_106 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
 Project_File_107 = /home/marek/ctsaddon/simulation/cts_downscale.vhd
 Project_File_P_107 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 30 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_108 = /home/marek/trbnet/trb_net16_obuf.vhd
-Project_File_P_108 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1302529528 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 104 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_108 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 104 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_109 = /home/marek/trbnet/trb_net16_term_ibuf.vhd
-Project_File_P_109 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 56 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_109 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 56 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_110 = /home/marek/ctsaddon/simulation/cts_align_signals.vhd
 Project_File_P_110 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453841 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 29 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_111 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x1k_oreg.vhd
 Project_File_P_111 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 81 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_112 = /home/marek/ctsaddon/simulation/cts_fpga1_tb.vhd
-Project_File_P_112 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1325689502 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 135 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_112 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1398158691 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 133 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_113 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x2k_oreg.vhd
 Project_File_P_113 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 76 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_114 = /home/marek/trbnet/basics/ram_16x16_dp.vhd
@@ -1783,33 +1783,33 @@ Project_File_P_115 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
 Project_File_116 = /home/marek/ctsaddon/simulation/cts_fpga2_lvl1_data_downscale.vhd
 Project_File_P_116 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321454039 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 33 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_117 = /home/marek/ctsaddon/simulation/trb_net16_lsm_sfp.vhd
-Project_File_P_117 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 89 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_117 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1398167587 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 89 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_118 = /home/marek/ctsaddon/simulation/dll_edge.vhd
 Project_File_P_118 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 13 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_119 = /home/marek/ctsaddon/simulation/cts_fpga1.vhd
-Project_File_P_119 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 137 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_119 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1398167587 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 135 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_120 = /home/marek/trbnet/basics/signal_sync.vhd
 Project_File_P_120 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1253527273 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 64 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_121 = /home/marek/ctsaddon/simulation/multiplicity.vhd
-Project_File_P_121 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 143 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_121 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 141 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_122 = /home/marek/trbnet/basics/ram_dp_rw.vhd
 Project_File_P_122 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1232546052 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 62 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_123 = /home/marek/ctsaddon/simulation/ddr2_12out_clkdiv.vhd
 Project_File_P_123 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321452786 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_124 = /home/marek/ctsaddon/simulation/cts_trigger_logic.vhd
-Project_File_P_124 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008208 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_124 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1398157164 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_125 = /home/marek/trbnet/lattice/ecp2m/trb_net16_fifo_arch.vhd
-Project_File_P_125 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321872640 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 72 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_125 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321284744 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 72 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_126 = /home/marek/trbnet/trb_net16_trigger.vhd
-Project_File_P_126 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1279810103 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 57 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_126 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 57 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_127 = /home/marek/ctsaddon/simulation/trb_net_components.vhd
-Project_File_P_127 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 90 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_127 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1398167587 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 90 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_128 = /home/marek/trbnet/lattice/ecp2m/lattice_ecp2m_fifo_16bit_dualport.vhd
 Project_File_P_128 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1224600671 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 120 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_129 = /home/marek/trbnet/lattice/ecp2m/pll_in100_out100.vhd
 Project_File_P_129 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1263292102 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 119 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_130 = /home/marek/trbnet/trb_net16_endpoint_hades_full.vhd
-Project_File_P_130 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 99 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_130 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365763 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 99 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_131 = /home/marek/ctsaddon/simulation/cts_one_clock.vhd
 Project_File_P_131 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453424 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 26 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_132 = /home/marek/ctsaddon/simulation/cts_delay.vhd
@@ -1819,19 +1819,19 @@ Project_File_P_133 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0
 Project_File_134 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_18x512_oreg.vhd
 Project_File_P_134 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270052331 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 79 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_135 = /home/marek/trbnet/special/handler_data.vhd
-Project_File_P_135 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1304328663 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 128 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_135 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1304093814 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 127 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_136 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x16k_oreg.vhd
 Project_File_P_136 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1280760366 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 85 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_137 = /home/marek/trbnet/basics/rom_16x8.vhd
 Project_File_P_137 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1226080893 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 63 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_138 = /home/marek/trbnet/trb_net_std.vhd
-Project_File_P_138 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1319014411 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 49 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_138 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365764 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 49 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_139 = /home/marek/ctsaddon/simulation/cts_set_width.vhd
-Project_File_P_139 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1332008494 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 132 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_139 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1398167587 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 130 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_140 = /home/marek/trbnet/trb_net16_addresses.vhd
-Project_File_P_140 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1266500256 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 50 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_140 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1349365763 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 50 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_141 = /home/marek/ctsaddon/cts_polarity_check.vhd
-Project_File_P_141 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453598 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 139 cover_nosub 0 dont_compile 0 vhdl_use93 2002
+Project_File_P_141 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1321453598 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 137 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_142 = /home/marek/trbnet/lattice/ecp2m/fifo/fifo_36x2k_oreg.vhd
 Project_File_P_142 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1270028476 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 82 cover_nosub 0 dont_compile 0 vhdl_use93 2002
 Project_File_143 = /home/marek/ctsaddon/simulation/fifo_16bit_to_32bit.vhd

diff --git a/cts_trigger_logic.vhd b/cts_trigger_logic.vhd
index 3ca5b63e3e020212386fcc7b37c6a8eecba0ab24..d796d984d46034bbf9c519ee8707cdddbf57e4e6 100755 (executable)
--- a/cts_trigger_logic.vhd
+++ b/cts_trigger_logic.vhd
@@ -485,7 +485,7 @@ architecture cts_trigger_logic of cts_trigger_logic is
   signal event_data : event_data_type;
 
   signal reset_scalers, reset_scalers_sync : std_logic;
-  type   LVL1_TEST is (IDLE, LVL1_A, LVL1_B, LVL1_C, LVL1_D, LVL1_E, LVL1_F);
+  type   LVL1_TEST is (IDLE, LVL1_A, LVL1_B, LVL1_C, LVL1_S1, LVL1_S2, LVL1_S3,  LVL1_D, LVL1_E, LVL1_F);
   signal LVL1_CURRENT, LVL1_NEXT : LVL1_TEST;
   signal lvl1_trigger_code : std_logic_vector(3 downto 0);
   signal lvl1_trigger_fsm : std_logic;
@@ -575,7 +575,7 @@ architecture cts_trigger_logic of cts_trigger_logic is
   --special scalers
   signal trigg_relative_time, trigg_relative_time_saved : std_logic_vector(31 downto 0);
   signal trigg_last_time, trigg_last_time_saved : std_logic_vector(31 downto 0);
-  signal trigg_anticoinc_time, trigg_anticoinc_time_saved : std_logic_vector(31 downto 0);
+  signal trigg_anticoinc_time, trigg_anticoinc_time_saved, trigg_anticoinc_time_saved_prev : std_logic_vector(31 downto 0);
   signal trigg_anticoinc : std_logic;
   signal reset_special_scalers : std_logic;
   
@@ -1760,7 +1760,7 @@ begin
   end process SAVE_LAST_TIME;
   scalers(TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER-2+2) <= trigg_last_time_saved;
   
---time since the last anticoincidence signal
+--time since the previous anticoincidence signal
   ANTICOINC_SIGNAL : process (CLK, RESET)
   begin
     if rising_edge(CLK) then
@@ -1777,26 +1777,30 @@ begin
   COUNT_SAVE_ANTICOINC_TIME : process (CLK, RESET)
   begin
     if rising_edge(CLK) then
-      if RESET = '1' or trigg_anticoinc = '1' or reset_special_scalers = '1' then
+      if RESET = '1' or trigg_anticoinc = '1' then
         trigg_anticoinc_time <= (others => '0');
+        trigg_anticoinc_time_saved <= trigg_anticoinc_time;
+        trigg_anticoinc_time_saved_prev <= trigg_anticoinc_time_saved;
       else
         trigg_anticoinc_time <= trigg_anticoinc_time + 1;
+        trigg_anticoinc_time_saved <= trigg_anticoinc_time_saved;
+        trigg_anticoinc_time_saved_prev <= trigg_anticoinc_time_saved_prev;
       end if;
     end if;
   end process COUNT_SAVE_ANTICOINC_TIME;
   
-  SAVE_ANTICOINC_TIME : process (CLK, RESET)
-  begin
-    if rising_edge(CLK) then
-      if RESET = '1' then
-        trigg_anticoinc_time_saved <= (others => '0');
-      elsif lvl1_trigger_pulse = '1' then
-        trigg_anticoinc_time_saved <= trigg_anticoinc_time;
-      else
-        trigg_anticoinc_time_saved <= trigg_anticoinc_time_saved;
-      end if;
-    end if;
-  end process SAVE_ANTICOINC_TIME;
+--  SAVE_ANTICOINC_TIME : process (CLK, RESET)
+--  begin
+--    if rising_edge(CLK) then
+--      if RESET = '1' then
+--        trigg_anticoinc_time_saved <= (others => '0');
+--      elsif lvl1_trigger_pulse = '1' then
+
+--      else
+        
+--      end if;
+--    end if;
+--  end process SAVE_ANTICOINC_TIME;
   scalers(TRIGGER_INPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER+TRIGGER_OUTPUTS_NUMBER-2+3) <= trigg_anticoinc_time_saved;
   
   
@@ -2081,16 +2085,24 @@ begin
       signal_in => lvl1_end,
       pulse  => lvl1_end_pulse);
   
-  SAVE_DATA_TO_SEND_TO_TRB : process (CLK, reset)  --only latch info - the rest
+  SAVE_DATA_TO_SEND_TO_TRB : process (CLK, reset)  --only latch and beam
+                                                   --scalers info - the rest
                                                    --is in the top entity
   begin
     if rising_edge(CLK) then
       if reset = '1' then
         data_to_send(0) <= (others => '0');
         data_to_send(1) <= (others => '0');
+        data_to_send(2) <= (others => '0');
+        data_to_send(3) <= (others => '0');
+        data_to_send(4) <= (others => '0');
       else
         data_to_send(0) <= pti_and_gts_out_saved(31 downto 0);
         data_to_send(1) <= (others => '0');
+        data_to_send(2) <= trigg_relative_time_saved;
+        data_to_send(3) <= trigg_last_time_saved;
+        data_to_send(4) <= trigg_anticoinc_time_saved;--_prev;
+
       end if;
     end if;
   end process SAVE_DATA_TO_SEND_TO_TRB;
@@ -2191,6 +2203,24 @@ begin
         lvl1_trigger_debug_fsm <= x"5";
         data_valid_fsm   <= '1';
         data_out_i_fsm <= data_to_send(1);
+--2014_apr start
+        LVL1_NEXT <= LVL1_S1;
+      when LVL1_S1 => 
+        lvl1_trigger_debug_fsm <= x"5";
+        data_valid_fsm   <= '1';
+        data_out_i_fsm <= data_to_send(2);
+        LVL1_NEXT <= LVL1_S2;
+      when LVL1_S2 => 
+        lvl1_trigger_debug_fsm <= x"5";
+        data_valid_fsm   <= '1';
+        data_out_i_fsm <= data_to_send(3);
+        LVL1_NEXT <= LVL1_S3;
+      when LVL1_S3 => 
+        lvl1_trigger_debug_fsm <= x"5";
+        data_valid_fsm   <= '1';
+        data_out_i_fsm <= data_to_send(4);
+--2014_apr end
+       
 --        if scaler_marker = '0' then
         if lvl1_trigger_code = x"E" then
           LVL1_NEXT <= LVL1_D;

diff --git a/ddr2_busses.vhd b/ddr2_busses.vhd
index a4be9b9056266382128072d1ec0d769c4779b398..361953bda271f87982a516358b057f66a1f8fe5e 100644 (file)
--- a/ddr2_busses.vhd
+++ b/ddr2_busses.vhd
@@ -274,7 +274,8 @@ begin
  --start in 16 out 3 x 8 (beam shifting by 4 due to the start detector damage) for triggering
 
   
-
+--there are two versions one mixed second one-to-one - just uncomment this what
+--you want
 --start cable is mixed: 1 2 3 4 5 6  7  8  9   10 11 12 13 14 15 16
 --                      1 3 5 7 9 11 13 15 16  14 12 10  8  6  4  2
 
@@ -284,45 +285,45 @@ begin
     if rising_edge(CLK) then
       case TRIG_CNTRL_IN(7 downto 6) is
         when  b"00" =>  
---          TRIG_OUT(8*4-1 downto 0) <=  output_from_fifo_sunch_a(8*4-1 downto 0);
-          TRIG_OUT(8*4-1 downto 0) <=   output_from_fifo_sunch_a(13*4-1 downto 12*4) &
-                                output_from_fifo_sunch_a(4*4-1 downto 3*4) &
-                                output_from_fifo_sunch_a(14*4-1 downto 13*4) &
-                                output_from_fifo_sunch_a(3*4-1 downto 2*4) &
-                                output_from_fifo_sunch_a(15*4-1 downto 14*4) &
-                                output_from_fifo_sunch_a(2*4-1 downto 1*4) &
-                                output_from_fifo_sunch_a(16*4-1 downto 15*4) &
-                                output_from_fifo_sunch_a(1*4-1 downto 0);
+          TRIG_OUT(8*4-1 downto 0) <=  output_from_fifo_sunch_a(8*4-1 downto 0);
+--          TRIG_OUT(8*4-1 downto 0) <=   output_from_fifo_sunch_a(13*4-1 downto 12*4) &
+--                                output_from_fifo_sunch_a(4*4-1 downto 3*4) &
+--                                output_from_fifo_sunch_a(14*4-1 downto 13*4) &
+--                                output_from_fifo_sunch_a(3*4-1 downto 2*4) &
+--                                output_from_fifo_sunch_a(15*4-1 downto 14*4) &
+--                                output_from_fifo_sunch_a(2*4-1 downto 1*4) &
+--                                output_from_fifo_sunch_a(16*4-1 downto 15*4) &
+--                                output_from_fifo_sunch_a(1*4-1 downto 0);
         when  b"01" => 
---          TRIG_OUT(8*4-1 downto 0) <=  output_from_fifo_sunch_a(12*4-1 downto 4*4);
-          TRIG_OUT(8*4-1 downto 0) <=   output_from_fifo_sunch_a(11*4-1 downto 10*4) &
-                                output_from_fifo_sunch_a(6*4-1 downto 5*4) &
-                                output_from_fifo_sunch_a(12*4-1 downto 11*4) &
-                                output_from_fifo_sunch_a(5*4-1 downto 4*4) &
-                                output_from_fifo_sunch_a(13*4-1 downto 12*4) &
-                                output_from_fifo_sunch_a(4*4-1 downto 3*4) &
-                                output_from_fifo_sunch_a(14*4-1 downto 13*4) &
-                                output_from_fifo_sunch_a(3*4-1 downto 2*4);
+          TRIG_OUT(8*4-1 downto 0) <=  output_from_fifo_sunch_a(12*4-1 downto 4*4);
+--          TRIG_OUT(8*4-1 downto 0) <=   output_from_fifo_sunch_a(11*4-1 downto 10*4) &
+--                                output_from_fifo_sunch_a(6*4-1 downto 5*4) &
+--                                output_from_fifo_sunch_a(12*4-1 downto 11*4) &
+--                                output_from_fifo_sunch_a(5*4-1 downto 4*4) &
+--                                output_from_fifo_sunch_a(13*4-1 downto 12*4) &
+--                                output_from_fifo_sunch_a(4*4-1 downto 3*4) &
+--                                output_from_fifo_sunch_a(14*4-1 downto 13*4) &
+--                                output_from_fifo_sunch_a(3*4-1 downto 2*4);
         when  b"10" => 
---          TRIG_OUT(8*4-1 downto 0) <=  output_from_fifo_sunch_a(16*4-1 downto 8*4);
-         TRIG_OUT(8*4-1 downto 0) <=   output_from_fifo_sunch_a(9*4-1 downto 8*4) &
-                                output_from_fifo_sunch_a(8*4-1 downto 7*4) &
-                                output_from_fifo_sunch_a(10*4-1 downto 9*4) &
-                                output_from_fifo_sunch_a(7*4-1 downto 6*4) &
-                                output_from_fifo_sunch_a(11*4-1 downto 10*4) &
-                                output_from_fifo_sunch_a(6*4-1 downto 5*4) &
-                                output_from_fifo_sunch_a(12*4-1 downto 11*4) &
-                                output_from_fifo_sunch_a(5*4-1 downto 4*4);
+         TRIG_OUT(8*4-1 downto 0) <=  output_from_fifo_sunch_a(16*4-1 downto 8*4);
+--         TRIG_OUT(8*4-1 downto 0) <=   output_from_fifo_sunch_a(9*4-1 downto 8*4) &
+--                                output_from_fifo_sunch_a(8*4-1 downto 7*4) &
+--                                output_from_fifo_sunch_a(10*4-1 downto 9*4) &
+--                                output_from_fifo_sunch_a(7*4-1 downto 6*4) &
+--                                output_from_fifo_sunch_a(11*4-1 downto 10*4) &
+--                                output_from_fifo_sunch_a(6*4-1 downto 5*4) &
+--                                output_from_fifo_sunch_a(12*4-1 downto 11*4) &
+--                                output_from_fifo_sunch_a(5*4-1 downto 4*4);
         when others =>
---          TRIG_OUT(8*4-1 downto 0) <=  output_from_fifo_sunch_a(8*4-1 downto 0);
-        TRIG_OUT(8*4-1 downto 0) <=   output_from_fifo_sunch_a(13*4-1 downto 12*4) &
-                                output_from_fifo_sunch_a(4*4-1 downto 3*4) &
-                                output_from_fifo_sunch_a(14*4-1 downto 13*4) &
-                                output_from_fifo_sunch_a(3*4-1 downto 2*4) &
-                                output_from_fifo_sunch_a(15*4-1 downto 14*4) &
-                                output_from_fifo_sunch_a(2*4-1 downto 1*4) &
-                                output_from_fifo_sunch_a(16*4-1 downto 15*4) &
-                                output_from_fifo_sunch_a(1*4-1 downto 0);
+        TRIG_OUT(8*4-1 downto 0) <=  output_from_fifo_sunch_a(8*4-1 downto 0);
+--        TRIG_OUT(8*4-1 downto 0) <=   output_from_fifo_sunch_a(13*4-1 downto 12*4) &
+--                                output_from_fifo_sunch_a(4*4-1 downto 3*4) &
+--                                output_from_fifo_sunch_a(14*4-1 downto 13*4) &
+--                                output_from_fifo_sunch_a(3*4-1 downto 2*4) &
+--                                output_from_fifo_sunch_a(15*4-1 downto 14*4) &
+--                                output_from_fifo_sunch_a(2*4-1 downto 1*4) &
+--                                output_from_fifo_sunch_a(16*4-1 downto 15*4) &
+--                                output_from_fifo_sunch_a(1*4-1 downto 0);
       end case;
     end if;
   end process SELECT_START_SIGNALS_FOR_TRIGGER;
@@ -332,42 +333,46 @@ begin
   begin
     if rising_edge(CLK) then
       case TRIG_CNTRL_IN(9 downto 8) is
-        when  b"00" =>  
-          TRIG_OUT(44*4-1 downto 36*4) <=   output_from_fifo_sunch_a((13+16)*4-1 downto (12+16)*4) &
-                                            output_from_fifo_sunch_a((4+16)*4-1 downto (3+16)*4) &
-                                            output_from_fifo_sunch_a((14+16)*4-1 downto (13+16)*4) &
-                                            output_from_fifo_sunch_a((3+16)*4-1 downto (2+16)*4) &
-                                            output_from_fifo_sunch_a((15+16)*4-1 downto (14+16)*4) &
-                                            output_from_fifo_sunch_a((2+16)*4-1 downto (1+16)*4) &
-                                            output_from_fifo_sunch_a((16+16)*4-1 downto (15+16)*4) &
-                                            output_from_fifo_sunch_a((1+16)*4-1 downto 16*4);
-        when  b"01" =>  
-          TRIG_OUT(44*4-1 downto 36*4) <=   output_from_fifo_sunch_a((11+16)*4-1 downto (10+16)*4) &
-                                            output_from_fifo_sunch_a((6+16)*4-1 downto (5+16)*4) &
-                                            output_from_fifo_sunch_a((12+16)*4-1 downto (11+16)*4) &
-                                            output_from_fifo_sunch_a((5+16)*4-1 downto (4+16)*4) &
-                                            output_from_fifo_sunch_a((13+16)*4-1 downto (12+16)*4) &
-                                            output_from_fifo_sunch_a((4+16)*4-1 downto (3+16)*4) &
-                                            output_from_fifo_sunch_a((14+16)*4-1 downto (13+16)*4) &
-                                            output_from_fifo_sunch_a((3+16)*4-1 downto (2+16)*4);
-         when  b"10" =>  
-          TRIG_OUT(44*4-1 downto 36*4) <=   output_from_fifo_sunch_a((9+16)*4-1 downto (8+16)*4) &
-                                            output_from_fifo_sunch_a((8+16)*4-1 downto (7+16)*4) &
-                                            output_from_fifo_sunch_a((10+16)*4-1 downto (9+16)*4) &
-                                            output_from_fifo_sunch_a((7+16)*4-1 downto (6+16)*4) &
-                                            output_from_fifo_sunch_a((11+16)*4-1 downto (10+16)*4) &
-                                            output_from_fifo_sunch_a((6+16)*4-1 downto (5+16)*4) &
-                                            output_from_fifo_sunch_a((12+16)*4-1 downto (11+16)*4) &
-                                            output_from_fifo_sunch_a((5+16)*4-1 downto (4+16)*4);
+        when  b"00" =>
+          TRIG_OUT(44*4-1 downto 36*4) <=  output_from_fifo_sunch_a((8+16)*4-1 downto (0+16)*4);
+--          TRIG_OUT(44*4-1 downto 36*4) <=   output_from_fifo_sunch_a((13+16)*4-1 downto (12+16)*4) &
+--                                            output_from_fifo_sunch_a((4+16)*4-1 downto (3+16)*4) &
+--                                            output_from_fifo_sunch_a((14+16)*4-1 downto (13+16)*4) &
+--                                            output_from_fifo_sunch_a((3+16)*4-1 downto (2+16)*4) &
+--                                            output_from_fifo_sunch_a((15+16)*4-1 downto (14+16)*4) &
+--                                            output_from_fifo_sunch_a((2+16)*4-1 downto (1+16)*4) &
+--                                            output_from_fifo_sunch_a((16+16)*4-1 downto (15+16)*4) &
+--                                            output_from_fifo_sunch_a((1+16)*4-1 downto 16*4);
+        when  b"01" =>
+          TRIG_OUT(44*4-1 downto 36*4) <=  output_from_fifo_sunch_a((12+16)*4-1 downto (4+16)*4);
+--          TRIG_OUT(44*4-1 downto 36*4) <=   output_from_fifo_sunch_a((11+16)*4-1 downto (10+16)*4) &
+--                                            output_from_fifo_sunch_a((6+16)*4-1 downto (5+16)*4) &
+--                                            output_from_fifo_sunch_a((12+16)*4-1 downto (11+16)*4) &
+--                                            output_from_fifo_sunch_a((5+16)*4-1 downto (4+16)*4) &
+--                                            output_from_fifo_sunch_a((13+16)*4-1 downto (12+16)*4) &
+--                                            output_from_fifo_sunch_a((4+16)*4-1 downto (3+16)*4) &
+--                                            output_from_fifo_sunch_a((14+16)*4-1 downto (13+16)*4) &
+--                                            output_from_fifo_sunch_a((3+16)*4-1 downto (2+16)*4);
+         when  b"10" =>
+          TRIG_OUT(44*4-1 downto 36*4) <=  output_from_fifo_sunch_a((16+16)*4-1 downto (8+16)*4);
+--          TRIG_OUT(44*4-1 downto 36*4) <=   output_from_fifo_sunch_a((9+16)*4-1 downto (8+16)*4) &
+--                                            output_from_fifo_sunch_a((8+16)*4-1 downto (7+16)*4) &
+--                                            output_from_fifo_sunch_a((10+16)*4-1 downto (9+16)*4) &
+--                                            output_from_fifo_sunch_a((7+16)*4-1 downto (6+16)*4) &
+--                                            output_from_fifo_sunch_a((11+16)*4-1 downto (10+16)*4) &
+--                                            output_from_fifo_sunch_a((6+16)*4-1 downto (5+16)*4) &
+--                                            output_from_fifo_sunch_a((12+16)*4-1 downto (11+16)*4) &
+--                                            output_from_fifo_sunch_a((5+16)*4-1 downto (4+16)*4);
         when others =>
-          TRIG_OUT(44*4-1 downto 36*4) <=   output_from_fifo_sunch_a((13+16)*4-1 downto (12+16)*4) &
-                                            output_from_fifo_sunch_a((4+16)*4-1 downto (3+16)*4) &
-                                            output_from_fifo_sunch_a((14+16)*4-1 downto (13+16)*4) &
-                                            output_from_fifo_sunch_a((3+16)*4-1 downto (2+16)*4) &
-                                            output_from_fifo_sunch_a((15+16)*4-1 downto (14+16)*4) &
-                                            output_from_fifo_sunch_a((2+16)*4-1 downto (1+16)*4) &
-                                            output_from_fifo_sunch_a((16+16)*4-1 downto (15+16)*4) &
-                                            output_from_fifo_sunch_a((1+16)*4-1 downto 16*4);
+          TRIG_OUT(44*4-1 downto 36*4) <=  output_from_fifo_sunch_a((8+16)*4-1 downto (0+16)*4);
+--          TRIG_OUT(44*4-1 downto 36*4) <=   output_from_fifo_sunch_a((13+16)*4-1 downto (12+16)*4) &
+--                                            output_from_fifo_sunch_a((4+16)*4-1 downto (3+16)*4) &
+--                                            output_from_fifo_sunch_a((14+16)*4-1 downto (13+16)*4) &
+--                                            output_from_fifo_sunch_a((3+16)*4-1 downto (2+16)*4) &
+--                                            output_from_fifo_sunch_a((15+16)*4-1 downto (14+16)*4) &
+--                                            output_from_fifo_sunch_a((2+16)*4-1 downto (1+16)*4) &
+--                                            output_from_fifo_sunch_a((16+16)*4-1 downto (15+16)*4) &
+--                                            output_from_fifo_sunch_a((1+16)*4-1 downto 16*4);
       end case;
     end if;
   end process SELECT_START_SIGNALS_FOR_TRIGGER_Y;

diff --git a/version.vhd b/version.vhd
index cc9cb313abf49f0da5403cad75cbd3eea8d1431a..f9e4388c67d27b00d8a9e1f72746c36db2fe8548 100644 (file)
--- a/version.vhd
+++ b/version.vhd
@@ -8,6 +8,6 @@ use ieee.numeric_std.all;
 
 package version is
 
-    constant VERSION_NUMBER_TIME  : integer   := 1334087142;
+    constant VERSION_NUMBER_TIME  : integer   := 1403204414;
 
 end package version;