*** empty log message ***

diff --git a/gbe_ecp2m/trb_net16_gbe_buf.vhd b/gbe_ecp2m/trb_net16_gbe_buf.vhd
index 863c81bd6b478b3bc1df0917ff7ae57602f38fbf..c1f6637dc5078d57e05753044a43bd1b164bfea1 100755 (executable)
--- a/gbe_ecp2m/trb_net16_gbe_buf.vhd
+++ b/gbe_ecp2m/trb_net16_gbe_buf.vhd
@@ -668,11 +668,33 @@ port map(
        DEBUG_OUT(63 downto 32)         => dbg_pc2
 );
 
-monitor_fifos_q(3 downto 0) <= monitor_fifos(3 downto 0);
-monitor_fifos_q(7 downto 4) <= b"1111" when ((dbg_pc1(28) = '1') or (dbg_pc1(31) = '1'))
-                               else b"0000";
-monitor_fifos_q(11 downto 8) <= b"1111" when (dbg_fc1(28) = '1') else b"0000";
-monitor_fifos_q(15 downto 12) <= b"1111" when (pcs_an_complete = '0') else b"0000";
+-- gk 04.08.10
+MON_PROC : process(CLK)
+begin
+       if rising_edge(CLK) then
+               monitor_fifos_q(3 downto 0) <= monitor_fifos(3 downto 0);
+               if (dbg_pc1(28) = '1') then
+                       monitor_fifos_q(5 downto 4) <= b"11";
+               else 
+                       monitor_fifos_q(5 downto 4) <= b"00";
+               end if;
+               if (dbg_pc1(30) = '1') then
+                       monitor_fifos_q(7 downto 6) <= b"11";
+               else 
+                       monitor_fifos_q(7 downto 6) <= b"00";
+               end if;
+               if (dbg_fc1(28) = '1') then
+                       monitor_fifos_q(11 downto 8) <= b"1111";
+               else
+                       monitor_fifos_q(11 downto 8) <= b"0000";
+               end if;
+               if (pcs_an_complete = '0') then
+                       monitor_fifos_q(15 downto 12) <= b"1111";
+               else
+                       monitor_fifos_q(15 downto 12) <= b"0000";
+               end if;
+       end if;
+end process MON_PROC;
 
 -- Third stage: Frame Constructor
 FRAME_CONSTRUCTOR: trb_net16_gbe_frame_constr

diff --git a/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd b/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd
index 4e5f0e8b7e648fc428442974206ad9800d89ff91..9112acddd7a65f98617d9592c698fb2b66659f83 100755 (executable)
--- a/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd
+++ b/gbe_ecp2m/trb_net16_gbe_frame_constr.vhd
@@ -55,7 +55,7 @@ architecture trb_net16_gbe_frame_constr of trb_net16_gbe_frame_constr is
 -- -- Placer Directives\r
 -- attribute HGROUP : string;\r
 -- -- for whole architecture\r
--- attribute HGROUP of trb_net16_gbe_frame_constr : architecture  is "GBE_frame_constr_group";\r
+-- attribute HGROUP of trb_net16_gbe_frame_constr : architecture  is "GBE_frame_group";\r
 \r
 component fifo_4096x9 is\r
 port( \r

diff --git a/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd b/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd
index b1cc4f11ec9ba900debc619638999236c27ff110..fd808c754942170d9dde6e54d1d963d43f9358de 100755 (executable)
--- a/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd
+++ b/gbe_ecp2m/trb_net16_gbe_frame_trans.vhd
@@ -47,7 +47,7 @@ architecture trb_net16_gbe_frame_trans of trb_net16_gbe_frame_trans is
 -- -- Placer Directives\r
 -- attribute HGROUP : string;\r
 -- -- for whole architecture\r
--- attribute HGROUP of trb_net16_gbe_frame_trans : architecture  is "GBE_frame_trans_group";\r
+-- attribute HGROUP of trb_net16_gbe_frame_trans : architecture  is "GBE_frame_group";\r
 \r
 component mac_init_mem is\r
 port (\r

diff --git a/gbe_ecp2m/trb_net16_ipu2gbe.vhd b/gbe_ecp2m/trb_net16_ipu2gbe.vhd
index cb010066ecef27bfd69b95207bb5f286512782c3..71ed59dc9fcdf3455ea81fb1ba325d4522f4fd2c 100755 (executable)
--- a/gbe_ecp2m/trb_net16_ipu2gbe.vhd
+++ b/gbe_ecp2m/trb_net16_ipu2gbe.vhd
@@ -241,6 +241,12 @@ signal inc_trg_ctr_comb     : std_logic;
 signal invalid_hsize_ctr    : std_logic_vector(15 downto 0);
 signal invalid_hsize_lock   : std_logic;
 
+signal load_eod_q           : std_logic;
+signal read_size_q          : std_logic_vector(17 downto 0);
+
+-- gk 06.08.10 write to fifo only if gbe is enabled but keep the saving logic unblocked
+signal sf_real_wr_en        : std_logic;
+
 begin
 
 -- Fake signals
@@ -310,11 +316,11 @@ begin
 end process SF_DATA_PROC;
 
 -- combinatorial read signal for the FEE data interface, DO NOT USE DIRECTLY
-fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled
+fee_read_comb <= '1' when ( (sf_afull = '0') and (data_req = '1') ) --and (DATA_GBE_ENABLE_IN = '1') ) -- GbE enabled
                                         else '0';
 
 -- combinatorial write signal for the split FIFO, DO NOT USE DIRECTLY
-sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') and (DATA_GBE_ENABLE_IN = '1') ) or -- GbE enabled
+sf_wr_en_comb <= '1' when ( (fee_read = '1') and (FEE_DATAREADY_IN = '1') ) or -- and (DATA_GBE_ENABLE_IN = '1') ) or -- GbE enabled
                                        (save_addr = '1') or
                                        (add_sub_state = '1')  -- gk 29.03.10 save the subsubevent
                                         else '0';
@@ -577,7 +583,7 @@ port map(
        Data(17)          => save_eod,
        WrClock         => CLK,
        RdClock         => CLK,
-       WrEn            => sf_wr_en,
+       WrEn            => sf_real_wr_en, -- gk 06.08.10 --sf_wr_en,
        RdEn            => sf_rd_en,
        Reset           => RESET,
        RPReset         => RESET,
@@ -592,6 +598,8 @@ port map(
        Full            => sf_full,
        AlmostFull      => sf_afull
 );
+-- gk 06.08.10
+sf_real_wr_en <= '1' when ((sf_wr_en = '1') and (DATA_GBE_ENABLE_IN = '1')) else '0';
 
 ------------------------------------------------------------------------------------------
 ------------------------------------------------------------------------------------------
@@ -714,7 +722,7 @@ begin
                when LIDLE =>
                        state2 <= x"0";
                        -- gk 23.07.10
-                       if( (sf_aempty = '0') and (PC_READY_IN = '1') and (event_waiting = '1') ) then
+                       if( (sf_aempty = '0') and (PC_READY_IN = '1') and (event_waiting = '1') and (DATA_GBE_ENABLE_IN = '1') ) then  -- gk 06.08.10
                                loadNextState <= INIT;
                                rst_rem_ctr_comb <= '1';
                                rst_regs_comb <= '1';
@@ -879,13 +887,22 @@ begin
                elsif (drop_headers = '1') then
                        headers_invalid_ctr   <= headers_invalid_ctr + x"1";
                        dropped_ctr <= dropped_ctr + x"1";
-               elsif (load_eod = '1') and (read_size /= x"3fffe") and (invalid_hsize_lock = '0') then
+               elsif (load_eod_q = '1') and (read_size_q /= x"3fffe") and (invalid_hsize_lock = '0') then -- ??
                        invalid_hsize_ctr <= invalid_hsize_ctr + x"1";
                        invalid_hsize_lock <= '1';
                end if;
        end if;
 end process INVALID_STATS_PROC;
 
+-- gk 05.08.10
+INVALID_H_PROC : process(CLK)
+begin
+       if rising_edge(CLK) then
+               load_eod_q  <= load_eod;
+               read_size_q <= read_size;
+       end if;
+end process INVALID_H_PROC;
+
 -- gk 26.04.10
 READOUT_CTR_PROC : process(CLK)
 begin
@@ -1258,7 +1275,8 @@ MONITOR_OUT(63 downto 32)   <= dropped_ctr;
 MONITOR_OUT(95 downto 64)   <= headers_invalid_ctr;
 MONITOR_OUT(127 downto 96)  <= dropped_sm_events_ctr;
 MONITOR_OUT(159 downto 128) <= dropped_lr_events_ctr;
-MONITOR_OUT(191 downto 160) <= (others => '0');
+MONITOR_OUT(163 downto 160) <= b"1111" when (sf_afull = '1') else b"0000";
+MONITOR_OUT(191 downto 164) <= (others => '0');
 
 -- Outputs
 FEE_READ_OUT             <= fee_read;