one lpf file for each Dirich version because current Diamond doesnt like double assig...

diff --git a/dirich/config_compile_frankfurt.pl b/dirich/config_compile_frankfurt.pl
index 19df01d5cd78847a24643fd1b9f48075d505bac6..b440f7fe8bf2250dde32064f5a31a29a7aedfdc3 100644 (file)
--- a/dirich/config_compile_frankfurt.pl
+++ b/dirich/config_compile_frankfurt.pl
@@ -13,7 +13,7 @@ synplify_path                => '/d/jspc29/lattice/synplify/L-2016.09-1/',
 # synplify_command             => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
 # synplify_command             => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #",
 nodelist_file                => 'nodelist_frankfurt.txt',
-pinout_file                  => 'dirich',
+pinout_file                  => 'dirich2',
 par_options                  => '../par.p2t',
 
 

diff --git a/pinout/dirich.lpf b/pinout/dirich.lpf
index b7d212f7395f55c15338d34c96e6bb020d36d2a2..4a1168978b983104403d2b417651f731763e3646 100644 (file)
--- a/pinout/dirich.lpf
+++ b/pinout/dirich.lpf
@@ -156,19 +156,3 @@ DEFINE PORT GROUP "TEST_group" "TEST*" ;
 IOBUF GROUP  "TEST_group" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
 
 
-LOCATE COMP "MISO_IN[0]"          SITE "E7";    #DAC1_CTRL0
-LOCATE COMP "MISO_IN[1]"          SITE "A17";   #DAC2_CTRL0
-LOCATE COMP "MOSI_OUT[0]"         SITE "D7";    #DAC1_CTRL1
-LOCATE COMP "MOSI_OUT[1]"         SITE "A18";   #DAC2_CTRL1
-LOCATE COMP "SCLK_OUT[0]"         SITE "E6";    #DAC1_CTRL2
-LOCATE COMP "SCLK_OUT[1]"         SITE "B19";   #DAC2_CTRL2
-LOCATE COMP "CS_OUT[0]"           SITE "D6";    #DAC1_CTRL3
-LOCATE COMP "CS_OUT[1]"           SITE "B18";   #DAC2_CTRL3
-IOBUF PORT "MISO_IN[0]" IO_TYPE=LVCMOS25 PULLMODE=UP;
-IOBUF PORT "MOSI_OUT[0]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
-IOBUF PORT "SCLK_OUT[0]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
-IOBUF PORT "CS_OUT[0]"    IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
-IOBUF PORT "MISO_IN[1]" IO_TYPE=LVCMOS25 PULLMODE=UP;
-IOBUF PORT "MOSI_OUT[1]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
-IOBUF PORT "SCLK_OUT[1]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
-IOBUF PORT "CS_OUT[1]"    IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;

diff --git a/pinout/dirich2.lpf b/pinout/dirich2.lpf
new file mode 100644 (file)
index 0000000..e8aa392
--- /dev/null
+++ b/pinout/dirich2.lpf
@@ -0,0 +1,139 @@
+SYSCONFIG MCCLK_FREQ=38.8 CONFIG_IOVOLTAGE=3.3 ; #BACKGROUND_RECONFIG=ON
+# BANK 0 VCCIO 2.5 V;
+# BANK 1 VCCIO 2.5 V;
+BANK 2 VCCIO 2.5 V;
+BANK 3 VCCIO 2.5 V;
+BANK 6 VCCIO 2.5 V;
+BANK 7 VCCIO 2.5 V;
+BANK 8 VCCIO 3.3 V;
+
+
+LOCATE COMP "INPUT[1]"  SITE "E5";
+LOCATE COMP "INPUT[2]"  SITE "F4";
+LOCATE COMP "INPUT[3]"  SITE "E4";
+LOCATE COMP "INPUT[4]"  SITE "B5";
+LOCATE COMP "INPUT[5]"  SITE "A4";
+LOCATE COMP "INPUT[6]"  SITE "C4";
+LOCATE COMP "INPUT[7]"  SITE "A3";
+LOCATE COMP "INPUT[8]"  SITE "C3";
+LOCATE COMP "INPUT[9]"  SITE "A2";
+LOCATE COMP "INPUT[10]"  SITE "B2";
+LOCATE COMP "INPUT[11]" SITE "C1";
+LOCATE COMP "INPUT[12]" SITE "D2";
+LOCATE COMP "INPUT[13]" SITE "F2";
+LOCATE COMP "INPUT[14]" SITE "G3";
+LOCATE COMP "INPUT[15]" SITE "H4";
+LOCATE COMP "INPUT[16]" SITE "H5";
+LOCATE COMP "INPUT[17]" SITE "T19";
+LOCATE COMP "INPUT[18]" SITE "T20";
+LOCATE COMP "INPUT[19]" SITE "U19";
+LOCATE COMP "INPUT[20]" SITE "P20";
+LOCATE COMP "INPUT[21]" SITE "R16";
+LOCATE COMP "INPUT[22]" SITE "N19";
+LOCATE COMP "INPUT[23]" SITE "P19";
+LOCATE COMP "INPUT[24]" SITE "L18";
+LOCATE COMP "INPUT[25]" SITE "N18";
+LOCATE COMP "INPUT[26]" SITE "D18";
+LOCATE COMP "INPUT[27]" SITE "E16";
+LOCATE COMP "INPUT[28]" SITE "L16";
+LOCATE COMP "INPUT[29]" SITE "N16";
+LOCATE COMP "INPUT[30]" SITE "N17";
+LOCATE COMP "INPUT[31]" SITE "U16";
+LOCATE COMP "INPUT[32]" SITE "U18";
+DEFINE PORT GROUP "INP_group" "INP*" ;
+IOBUF GROUP  "INP_group" IO_TYPE=LVDS  DIFFRESISTOR=OFF BANK_VCCIO=2.5;
+
+LOCATE COMP "CLOCK_IN"   SITE "L20";
+LOCATE COMP "CLOCK_CAL"                 SITE "J20";
+DEFINE PORT GROUP "CLK_group" "CL*" ;
+IOBUF GROUP  "CLK_group" IO_TYPE=LVDS  DIFFRESISTOR=100 BANK_VCCIO=2.5;
+
+LOCATE COMP "TRIG_IN" SITE "L19";
+DEFINE PORT GROUP "TRIG_group" "TRIG*" ;
+IOBUF GROUP  "TRIG_group" IO_TYPE=LVDS  DIFFRESISTOR=100 BANK_VCCIO=2.5;
+
+
+LOCATE COMP "LED_GREEN"                      SITE "G16";
+LOCATE COMP "LED_ORANGE"                     SITE "H16";
+LOCATE COMP "LED_RED"                        SITE "H18";
+LOCATE COMP "LED_YELLOW"                     SITE "H17";
+DEFINE PORT GROUP "LED_group" "LED*" ;
+IOBUF GROUP  "LED_group" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+
+LOCATE COMP "ADC_CS"                         SITE "J16";
+LOCATE COMP "ADC_DIN"                        SITE "K17";
+LOCATE COMP "ADC_DOUT"                       SITE "K16";
+LOCATE COMP "ADC_SCLK"                       SITE "J17";
+IOBUF PORT  "ADC_CS" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+IOBUF PORT  "ADC_DIN" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+IOBUF PORT  "ADC_DOUT" IO_TYPE=LVCMOS25  BANK_VCCIO=2.5;
+IOBUF PORT  "ADC_SCLK" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+
+
+
+LOCATE COMP "PROGRAMN"                       SITE "T1";
+IOBUF PORT  "PROGRAMN" IO_TYPE=LVTTL33  DRIVE=8 BANK_VCCIO=3.3;
+
+LOCATE COMP "SIG[1]"                           SITE "N4";
+LOCATE COMP "SIG[2]"                           SITE "N5";
+LOCATE COMP "SIG[3]"                           SITE "M5";
+LOCATE COMP "SIG[4]"                           SITE "M4";
+# LOCATE COMP "SIG[5]"                           SITE "L5";
+IOBUF PORT    "SIG[1]" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5 PULLMODE=DOWN;
+IOBUF PORT    "SIG[2]" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+IOBUF PORT    "SIG[3]" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+IOBUF PORT    "SIG[4]" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+
+
+LOCATE COMP "FLASH_CLK"                        SITE "U1";
+LOCATE COMP "FLASH_CS"                         SITE "R2";
+LOCATE COMP "FLASH_IN"                         SITE "W2";
+LOCATE COMP "FLASH_OUT"                        SITE "V2";
+LOCATE COMP "FLASH_HOLD"                       SITE "W1";
+LOCATE COMP "FLASH_WP"                         SITE "Y2";
+IOBUF PORT  "FLASH_CLK" IO_TYPE=LVTTL33  DRIVE=8 BANK_VCCIO=3.3;
+IOBUF PORT  "FLASH_IN"  IO_TYPE=LVTTL33  DRIVE=8 BANK_VCCIO=3.3;
+IOBUF PORT  "FLASH_OUT" IO_TYPE=LVTTL33   BANK_VCCIO=3.3;
+IOBUF PORT  "FLASH_CS"  IO_TYPE=LVTTL33  DRIVE=8 BANK_VCCIO=3.3;
+IOBUF PORT  "FLASH_HOLD" IO_TYPE=LVTTL33   BANK_VCCIO=3.3;
+IOBUF PORT  "FLASH_WP" IO_TYPE=LVTTL33   BANK_VCCIO=3.3;
+
+
+LOCATE COMP "TEMP_LINE"                      SITE "R1";
+IOBUF PORT  "TEMP_LINE" IO_TYPE=LVTTL33  DRIVE=8 BANK_VCCIO=3.3;
+
+
+LOCATE COMP "TEST_LINE[1]"                          SITE "N3";
+LOCATE COMP "TEST_LINE[2]"                          SITE "M3";
+LOCATE COMP "TEST_LINE[3]"                          SITE "L3";
+LOCATE COMP "TEST_LINE[4]"                          SITE "K3";
+LOCATE COMP "TEST_LINE[5]"                          SITE "N2";
+LOCATE COMP "TEST_LINE[6]"                          SITE "J3";
+LOCATE COMP "TEST_LINE[7]"                          SITE "P1";
+LOCATE COMP "TEST_LINE[8]"                          SITE "L2";
+LOCATE COMP "TEST_LINE[9]"                          SITE "P2";
+LOCATE COMP "TEST_LINE[10]"                         SITE "L1";
+LOCATE COMP "TEST_LINE[11]"                         SITE "P3";
+LOCATE COMP "TEST_LINE[12]"                         SITE "M1";
+LOCATE COMP "TEST_LINE[13]"                         SITE "P4";
+LOCATE COMP "TEST_LINE[14]"                         SITE "N1";
+DEFINE PORT GROUP "TEST_group" "TEST*" ;
+IOBUF GROUP  "TEST_group" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;
+
+
+LOCATE COMP "MISO_IN[0]"          SITE "E7";    #DAC1_CTRL0
+LOCATE COMP "MISO_IN[1]"          SITE "A17";   #DAC2_CTRL0
+LOCATE COMP "MOSI_OUT[0]"         SITE "D7";    #DAC1_CTRL1
+LOCATE COMP "MOSI_OUT[1]"         SITE "A18";   #DAC2_CTRL1
+LOCATE COMP "SCLK_OUT[0]"         SITE "E6";    #DAC1_CTRL2
+LOCATE COMP "SCLK_OUT[1]"         SITE "B19";   #DAC2_CTRL2
+LOCATE COMP "CS_OUT[0]"           SITE "D6";    #DAC1_CTRL3
+LOCATE COMP "CS_OUT[1]"           SITE "B18";   #DAC2_CTRL3
+IOBUF PORT "MISO_IN[0]" IO_TYPE=LVCMOS25 PULLMODE=UP;
+IOBUF PORT "MOSI_OUT[0]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+IOBUF PORT "SCLK_OUT[0]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+IOBUF PORT "CS_OUT[0]"    IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+IOBUF PORT "MISO_IN[1]" IO_TYPE=LVCMOS25 PULLMODE=UP;
+IOBUF PORT "MOSI_OUT[1]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+IOBUF PORT "SCLK_OUT[1]"  IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;
+IOBUF PORT "CS_OUT[1]"    IO_TYPE=LVCMOS25 DRIVE=4 SLEWRATE=SLOW;