Adding some logic to bus_handler_record to cope with misbehaving slaves

diff --git a/trb_net16_regio_bus_handler_record.vhd b/trb_net16_regio_bus_handler_record.vhd
index 9bc65ed346f54f88e7a957b2458121f36c9ee68d..0f07343eadd8f5d74f49d03ac4abfe04ee7775d0 100644 (file)
--- a/trb_net16_regio_bus_handler_record.vhd
+++ b/trb_net16_regio_bus_handler_record.vhd
@@ -61,7 +61,7 @@ architecture regio_bus_handler_arch of trb_net16_regio_bus_handler_record is
   signal buf_BUS_WRITE_ACK_IN         : std_logic_vector(PORT_NUMBER downto 0);
   signal buf_BUS_NO_MORE_DATA_IN      : std_logic_vector(PORT_NUMBER downto 0);
   signal buf_BUS_UNKNOWN_ADDR_IN      : std_logic_vector(PORT_NUMBER downto 0);
-
+  
   attribute syn_preserve : boolean;
   attribute syn_keep : boolean;
   attribute syn_preserve of buf_BUS_ADDR_OUT : signal is true;
@@ -93,11 +93,11 @@ begin
   proc_rw_signals : process(CLK)
     begin
       if rising_edge(CLK) then
-        if RESET = '1' then
-          buf_BUS_READ_OUT  <= (others => '0');
-          buf_BUS_WRITE_OUT <= (others => '0');
-          port_select_int <= PORT_NUMBER;
-        else
+--         if RESET = '1' then
+--           buf_BUS_READ_OUT  <= (others => '0');
+--           buf_BUS_WRITE_OUT <= (others => '0');
+--           port_select_int <= PORT_NUMBER;
+--         else
           buf_BUS_READ_OUT  <= (others => '0');
           buf_BUS_WRITE_OUT <= (others => '0');
           if REGIO_RX.write = '1' or REGIO_RX.read = '1' then
@@ -111,8 +111,14 @@ begin
           if REGIO_RX.write = '1' then
             buf_BUS_WRITE_OUT(next_port_select_int) <= '1';
           end if;
+          if (buf_BUS_DATAREADY_IN(port_select_int) or 
+              buf_BUS_WRITE_ACK_IN(port_select_int) or
+              buf_BUS_UNKNOWN_ADDR_IN(port_select_int) or
+              buf_BUS_NO_MORE_DATA_IN(port_select_int)) = '1' then
+            port_select_int <= PORT_NUMBER;
+          end if;  
         end if;
-      end if;
+--       end if;
     end process;
 
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