entity trb_net16_fifo is
generic (
USE_VENDOR_CORES : integer range 0 to 1 := c_NO;
+ use_data_count : integer range 0 to 1 := c_NO;
DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets
);
port (
entity trb_net16_fifo is
generic (
USE_VENDOR_CORES : integer range 0 to 1 := c_NO;
+ use_data_count : integer range 0 to 1 := c_NO;
DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets
);
port (
[Device]
Family=latticescm
PartType=LFSCM3GA40EP1
-PartName=LFSCM3GA40EP1-6FC1152C
-SpeedGrade=-6
-Package=FCBGA1152
+PartName=LFSCM3GA40EP1-6FF1020C
+SpeedGrade=6
+Package=FFBGA1020
OperatingCondition=COM
Status=P
CoreType=LPM
CoreStatus=Demo
CoreName=PLL
-CoreRevision=5.1
+CoreRevision=5.2
ModuleName=pll_in200_out100
-SourceFormat=Schematic/VHDL
+SourceFormat=VHDL
ParameterFileVersion=1.0
-Date=06/22/2010
-Time=13:23:32
+Date=10/19/2011
+Time=18:27:25
[Parameters]
Verilog=0
U_OFrq=100
OP_Tol=0.0
ClkOP_Freq= 100.000000
-U_SFrq=100
+U_SFrq=200
OS_Tol=0.0
-ClkOS_Freq= 100.000000
+ClkOS_Freq= 200.000000
Phase=0
FineDelay=0
-FeedbackClk=CLKOP
-Frequency= 100.000000
+FeedbackClk=Internal
+Frequency=200
enSpectrum=0
smiport=0
enRSTN=0
lock=Frequency
enGSR=0
VcoRate= 600.000000
-Bandwidth= 5.262395
+Bandwidth= 7.130030
enHighBand=0
enBypassP=0
-enBypassS=0
+enBypassS=1
--- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41)
--- Module Version: 5.1
---/d/sugar/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n pll_in200_out100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type pll -fin 200 -mfreq 100 -nfreq 100 -tap 0 -clkos_fdel 0 -fb 1 -clki_del 0 -clki_fdel 0 -clkfb_del 0 -clkfb_fdel 0 -mtol 0.0 -ntol 0.0 -bw LOW -e
+-- VHDL netlist generated by SCUBA Diamond_1.3_Production (92)
+-- Module Version: 5.2
+--/d/sugar/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n pll_in200_out100 -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type pll -fin 200 -mfreq 100 -nfreq 200 -bypasss -clkos_fdel 0 -fb 0 -clki_del 0 -clki_fdel 0 -clkfb_del 0 -clkfb_fdel 0 -mtol 0.0 -ntol 0.0 -bw LOW -e
--- Tue Jun 22 13:23:33 2010
+-- Wed Oct 19 18:27:25 2011
library IEEE;
use IEEE.std_logic_1164.all;
signal scuba_vlo: std_logic;
signal scuba_vhi: std_logic;
signal clkos_t: std_logic;
+ signal fb: std_logic;
signal clkop_t: std_logic;
signal clk_t: std_logic;
attribute CLKFB_DIV : string;
attribute CLKI_DIV : string;
attribute ip_type of pll_in200_out100_0_0 : label is "EHXPLLA";
- attribute FREQUENCY_PIN_CLKOS of pll_in200_out100_0_0 : label is "100.000000";
+ attribute FREQUENCY_PIN_CLKOS of pll_in200_out100_0_0 : label is "200.000000";
attribute FREQUENCY_PIN_CLKOP of pll_in200_out100_0_0 : label is "100.000000";
attribute FREQUENCY_PIN_CLKI of pll_in200_out100_0_0 : label is "200.000000";
attribute VCO_LOWERFREQ of pll_in200_out100_0_0 : label is "DISABLED";
attribute CLKI_FDEL of pll_in200_out100_0_0 : label is "0";
attribute CLKFB_PDEL of pll_in200_out100_0_0 : label is "DEL0";
attribute CLKI_PDEL of pll_in200_out100_0_0 : label is "DEL0";
- attribute LF_RESISTOR of pll_in200_out100_0_0 : label is "0b111010";
+ attribute LF_RESISTOR of pll_in200_out100_0_0 : label is "0b111011";
attribute LF_IX5UA of pll_in200_out100_0_0 : label is "31";
attribute CLKOS_FDEL of pll_in200_out100_0_0 : label is "0";
attribute CLKOS_VCODEL of pll_in200_out100_0_0 : label is "0";
attribute PHASEADJ of pll_in200_out100_0_0 : label is "0";
- attribute CLKOS_MODE of pll_in200_out100_0_0 : label is "DIV";
+ attribute CLKOS_MODE of pll_in200_out100_0_0 : label is "BYPASS";
attribute CLKOP_MODE of pll_in200_out100_0_0 : label is "DIV";
attribute CLKOS_DIV of pll_in200_out100_0_0 : label is "6";
attribute CLKOP_DIV of pll_in200_out100_0_0 : label is "6";
- attribute CLKFB_DIV of pll_in200_out100_0_0 : label is "1";
- attribute CLKI_DIV of pll_in200_out100_0_0 : label is "2";
+ attribute CLKFB_DIV of pll_in200_out100_0_0 : label is "3";
+ attribute CLKI_DIV of pll_in200_out100_0_0 : label is "1";
attribute syn_keep : boolean;
attribute syn_noprune : boolean;
attribute syn_noprune of Structure : architecture is true;
generic map (SMI_OFFSET=> SMI_OFFSET
-- synopsys translate_off
, GSR=> "ENABLED", CLKFB_FDEL=> 0, CLKI_FDEL=> 0,
- CLKOS_FDEL=> 0, CLKOS_VCODEL=> 0, PHASEADJ=> 0, CLKOS_MODE=> "DIV",
- CLKOP_MODE=> "DIV", CLKOS_DIV=> 6, CLKOP_DIV=> 6, CLKFB_DIV=> 1,
- CLKI_DIV=> 2
+ CLKOS_FDEL=> 0, CLKOS_VCODEL=> 0, PHASEADJ=> 0, CLKOS_MODE=> "BYPASS",
+ CLKOP_MODE=> "DIV", CLKOS_DIV=> 6, CLKOP_DIV=> 6, CLKFB_DIV=> 3,
+ CLKI_DIV=> 1
-- synopsys translate_on
)
port map (SMIADDR9=>scuba_vlo, SMIADDR8=>scuba_vlo,
SMIADDR3=>scuba_vlo, SMIADDR2=>scuba_vlo,
SMIADDR1=>scuba_vlo, SMIADDR0=>scuba_vlo, SMIRD=>scuba_vlo,
SMIWR=>scuba_vlo, SMICLK=>scuba_vlo, SMIWDATA=>scuba_vlo,
- SMIRSTN=>scuba_vlo, CLKI=>clk_t, CLKFB=>clkop_t,
- RSTN=>scuba_vhi, CLKOS=>clkos_t, CLKOP=>clkop_t, LOCK=>lock,
- CLKINTFB=>open, SMIRDATA=>open);
+ SMIRSTN=>scuba_vlo, CLKI=>clk_t, CLKFB=>fb, RSTN=>scuba_vhi,
+ CLKOS=>clkos_t, CLKOP=>clkop_t, LOCK=>lock, CLKINTFB=>fb,
+ SMIRDATA=>open);
clkos <= clkos_t;
clkop <= clkop_t;
generic(
SERDES_NUM : integer range 0 to 3 := 0;
EXT_CLOCK : integer range 0 to 1 := c_NO;
- USE_200_MHZ: integer range 0 to 1 := c_YES
+ USE_200_MHZ: integer range 0 to 1 := c_YES;
+ USE_125_MHZ: integer range 0 to 1 := c_NO
);
port(
CLK : in std_logic; -- SerDes clock
--Media interface for Lattice ECP3 using PCS at 2GHz, RX clock == TX clock
+--For fully synchronized FPGAs only!
+--Either 200 MHz input for 2GBit or 125 MHz for 2.5GBit.
+--system clock can be 100 MHz or 125 MHz
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
entity trb_net16_med_ecp3_sfp_4_onboard is
generic(
REVERSE_ORDER : integer range 0 to 1 := c_NO;
- FREQUENCY : integer range 125 to 200 := 200
+ FREQUENCY : integer range 125 to 200 := 200 --200 or 125
-- USED_PORTS : std_logic-vector(3 downto 0) := "1111"
);
port(
signal pwr_up : std_logic_vector(4*1-1 downto 0);
signal clear_n : std_logic;
+ signal clk_sys : std_logic;
+ signal clk_tx : std_logic;
+ signal clk_rx : std_logic;
+ signal clk_ref : std_logic;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
begin
--------------------------------------------------------------------------
--- Internal Lane Resets
+-- Select proper clock configuration
--------------------------------------------------------------------------
- clear_n <= not clear;
+gen_clocks_200 : if FREQUENCY = 200 generate
+ clk_sys <= SYSCLK;
+ clk_tx <= SYSCLK;
+ clk_rx <= SYSCLK;
+ clk_ref <= CLK;
+end generate;
+gen_clocks_125 : if FREQUENCY = 125 generate
+ clk_sys <= SYSCLK;
+ clk_tx <= CLK;
+ clk_rx <= CLK;
+ clk_ref <= CLK;
+end generate;
- PROC_RESET : process(SYSCLK)
+--------------------------------------------------------------------------
+-- Internal Resets
+--------------------------------------------------------------------------
+ clear_n <= not clear;
+
+ PROC_RESET : process(clk_sys)
begin
- if rising_edge(SYSCLK) then
+ if rising_edge(clk_sys) then
reset_i <= RESET;
send_reset_in(0) <= ctrl_op(15);
send_reset_in(1) <= ctrl_op(15+16);
--------------------------------------------------------------------------
-- Input synchronizer for SFP_PRESENT and SFP_LOS signals (external signals from SFP)
-THE_SFP_STATUS_SYNC: signal_sync
- generic map(
- DEPTH => 1,
- WIDTH => 8
- )
- port map(
- RESET => '0',
- D_IN(3 downto 0) => SD_PRSNT_N_IN,
- D_IN(7 downto 4) => SD_LOS_IN,
- CLK0 => sysclk,
- CLK1 => sysclk,
- D_OUT(3 downto 0) => sfp_prsnt_n,
- D_OUT(7 downto 4) => sfp_los
- );
+sfp_prsnt_n <= SD_PRSNT_N_IN when rising_edge(clk_sys);
+sfp_los <= SD_LOS_IN when rising_edge(clk_sys);
+rx_k_q <= rx_k when rising_edge(clk_sys);
-
-rx_k_q <= rx_k;
send_reset_words_q <= send_reset_words;
make_trbnet_reset_q <= make_trbnet_reset;
reset_i_rx <= reset_i;
-
-THE_RX_DATA_DELAY: signal_sync
- generic map(
- DEPTH => 1,
- WIDTH => 64
- )
- port map(
- RESET => reset_i,
- D_IN => comb_rx_data,
- CLK0 => sysclk,
- CLK1 => sysclk,
- D_OUT => rx_data
- );
-THE_RX_K_DELAY: signal_sync
- generic map(
- DEPTH => 1,
- WIDTH => 8
- )
- port map(
- RESET => reset_i,
- D_IN => comb_rx_k,
- CLK0 => sysclk,
- CLK1 => sysclk,
- D_OUT => rx_k
- );
--- Delay for ALLOW signals
-THE_RX_ALLOW_SYNC: signal_sync
- generic map(
- DEPTH => 2,
- WIDTH => 8
- )
- port map(
- RESET => reset_i,
- D_IN(3 downto 0) => rx_allow,
- D_IN(7 downto 4) => tx_allow,
- CLK0 => sysclk,
- CLK1 => sysclk,
- D_OUT(3 downto 0) => rx_allow_q,
- D_OUT(7 downto 4) => tx_allow_q
- );
+rx_data <= comb_rx_data when rising_edge(clk_rx);
+rx_k <= comb_rx_k when rising_edge(clk_rx);
-THE_TX_SYNC: signal_sync
- generic map(
- DEPTH => 1,
- WIDTH => 8
- )
- port map(
- RESET => '0',
- D_IN(3 downto 0) => send_reset_in,
- D_IN(7 downto 4) => tx_allow,
- CLK0 => sysclk,
- CLK1 => sysclk,
- D_OUT(3 downto 0) => send_reset_in_qtx,
- D_OUT(7 downto 4) => tx_allow_qtx
- );
+rx_allow_q <= rx_allow when rising_edge(clk_sys);
+tx_allow_q <= tx_allow when rising_edge(clk_sys);
+
+send_reset_in_qtx <= send_reset_in when rising_edge(clk_tx);
+tx_allow_qtx <= tx_allow when rising_edge(clk_tx);
--------------------------------------------------------------------------
gen_LSM : for i in 0 to 3 generate
THE_SFP_LSM: trb_net16_lsm_sfp
port map(
- SYSCLK => sysclk,
+ SYSCLK => clk_sys,
RESET => reset_i,
CLEAR => clear,
SFP_MISSING_IN => sfp_prsnt_n(i),
end generate;
-- Instantiation of serdes module
-gen_SERDES_200 : if FREQUENCY = 200 generate
+gen_serdes_200 : if FREQUENCY = 200 generate
THE_SERDES: serdes_onboard_full
port map(
HDINP_CH0 => sd_rxd_p_in(0),
HDOUTP_CH3 => sd_txd_p_out(3),
HDOUTN_CH3 => sd_txd_n_out(3),
- RXICLK_CH0 => sysclk,
- TXICLK_CH0 => sysclk,
- RXICLK_CH1 => sysclk,
- TXICLK_CH1 => sysclk,
- RXICLK_CH2 => sysclk,
- TXICLK_CH2 => sysclk,
- RXICLK_CH3 => sysclk,
- TXICLK_CH3 => sysclk,
- FPGA_RXREFCLK_CH0 => CLK,
- FPGA_RXREFCLK_CH1 => CLK,
- FPGA_RXREFCLK_CH2 => CLK,
- FPGA_RXREFCLK_CH3 => CLK,
- FPGA_TXREFCLK => CLK,
+ RXICLK_CH0 => clk_rx,
+ TXICLK_CH0 => clk_tx,
+ RXICLK_CH1 => clk_rx,
+ TXICLK_CH1 => clk_tx,
+ RXICLK_CH2 => clk_rx,
+ TXICLK_CH2 => clk_tx,
+ RXICLK_CH3 => clk_rx,
+ TXICLK_CH3 => clk_tx,
+ FPGA_RXREFCLK_CH0 => clk_ref,
+ FPGA_RXREFCLK_CH1 => clk_ref,
+ FPGA_RXREFCLK_CH2 => clk_ref,
+ FPGA_RXREFCLK_CH3 => clk_ref,
+ FPGA_TXREFCLK => clk_ref,
RX_FULL_CLK_CH0 => open,
RX_HALF_CLK_CH0 => open,
TX_FULL_CLK_CH0 => open,
);
end generate;
-gen_SERDES_125 : if FREQUENCY = 125 generate
+gen_serdes_125 : if FREQUENCY = 125 generate
THE_SERDES: serdes_onboard_full_125
port map(
HDINP_CH0 => sd_rxd_p_in(0),
HDOUTP_CH3 => sd_txd_p_out(3),
HDOUTN_CH3 => sd_txd_n_out(3),
- RXICLK_CH0 => sysclk,
- TXICLK_CH0 => sysclk,
- RXICLK_CH1 => sysclk,
- TXICLK_CH1 => sysclk,
- RXICLK_CH2 => sysclk,
- TXICLK_CH2 => sysclk,
- RXICLK_CH3 => sysclk,
- TXICLK_CH3 => sysclk,
- FPGA_RXREFCLK_CH0 => CLK,
- FPGA_RXREFCLK_CH1 => CLK,
- FPGA_RXREFCLK_CH2 => CLK,
- FPGA_RXREFCLK_CH3 => CLK,
- FPGA_TXREFCLK => CLK,
+ RXICLK_CH0 => clk_rx,
+ TXICLK_CH0 => clk_tx,
+ RXICLK_CH1 => clk_rx,
+ TXICLK_CH1 => clk_tx,
+ RXICLK_CH2 => clk_rx,
+ TXICLK_CH2 => clk_tx,
+ RXICLK_CH3 => clk_rx,
+ TXICLK_CH3 => clk_tx,
+ FPGA_RXREFCLK_CH0 => clk_ref,
+ FPGA_RXREFCLK_CH1 => clk_ref,
+ FPGA_RXREFCLK_CH2 => clk_ref,
+ FPGA_RXREFCLK_CH3 => clk_ref,
+ FPGA_TXREFCLK => clk_ref,
RX_FULL_CLK_CH0 => open,
RX_HALF_CLK_CH0 => open,
TX_FULL_CLK_CH0 => open,
generic map(
USE_STATUS_FLAGS => c_NO
)
- port map( read_clock_in => sysclk,
- write_clock_in => sysclk, -- CHANGED
+ port map( read_clock_in => clk_sys,
+ write_clock_in => clk_rx,
read_enable_in => fifo_rx_rd_en(i),
write_enable_in => fifo_rx_wr_en(i),
fifo_gsr_in => fifo_rx_reset(i),
-- Received bytes need to be swapped if the SerDes is "off by one" in its internal 8bit path
THE_BYTE_SWAP_PROC: process
begin
- wait until rising_edge(sysclk); --CHANGED
+ wait until rising_edge(clk_rx); --CHANGED sysclk
last_rx(i*9+8 downto i*9) <= rx_k(i*2+1) & rx_data(i*16+15 downto i*16+8);
if( swap_bytes(i) = '0' ) then
fifo_rx_din(i*18+17 downto i*18) <= rx_k(i*2+1) & rx_k(i*2+0)
THE_CNT_RESET_PROC : process
begin
- wait until rising_edge(sysclk); --CHANGED
+ wait until rising_edge(clk_rx); --CHANGED sysclk
if reset_i_rx = '1' then
send_reset_words(i) <= '0';
make_trbnet_reset(i) <= '0';
THE_SYNC_PROC: process
begin
- wait until rising_edge(sysclk);
+ wait until rising_edge(clk_sys);
med_dataready_out(i) <= buf_med_dataready_out(i);
med_data_out(i*16+15 downto i*16) <= buf_med_data_out(i*16+15 downto i*16);
med_packet_num_out(i*3+2 downto i*3) <= buf_med_packet_num_out(i*3+2 downto i*3);
--rx packet counter
---------------------
- THE_RX_PACKETS_PROC: process( sysclk )
+ THE_RX_PACKETS_PROC: process( clk_sys )
begin
if( rising_edge(sysclk) ) then
last_fifo_rx_empty(i) <= fifo_rx_empty(i);
generic map(
USE_STATUS_FLAGS => c_NO
)
- port map( read_clock_in => sysclk,
- write_clock_in => sysclk,
+ port map( read_clock_in => clk_tx,--sysclk,
+ write_clock_in => clk_sys,
read_enable_in => fifo_tx_rd_en(i),
write_enable_in => fifo_tx_wr_en(i),
fifo_gsr_in => fifo_tx_reset(i),
fifo_tx_rd_en(i) <= tx_allow_qtx(i);
- THE_SERDES_INPUT_PROC: process( sysclk )
- begin
- if( rising_edge(sysclk) ) then
- last_fifo_tx_empty(i) <= fifo_tx_empty(i);
- first_idle(i) <= not last_fifo_tx_empty(i) and fifo_tx_empty(i);
- if send_reset_in(i) = '1' then
- tx_data(i*16+15 downto i*16) <= x"FEFE";
- tx_k(i*2+1 downto i*2) <= "11";
- elsif( (last_fifo_tx_empty(i) = '1') or (tx_allow_qtx(i) = '0') ) then
- tx_data(i*16+15 downto i*16) <= x"50bc";
- tx_k(i*2+1 downto i*2) <= "01";
- tx_correct(i*2+1 downto i*2) <= first_idle(i) & '0';
- else
- tx_data(i*16+15 downto i*16) <= fifo_tx_dout(i*18+15 downto i*18);
- tx_k(i*2+1 downto i*2) <= "00";
- tx_correct(i*2+1 downto i*2) <= "00";
- end if;
- end if;
- end process THE_SERDES_INPUT_PROC;
+ THE_SERDES_INPUT_PROC: process begin
+ wait until rising_edge(clk_tx);
+ last_fifo_tx_empty(i) <= fifo_tx_empty(i);
+ first_idle(i) <= not last_fifo_tx_empty(i) and fifo_tx_empty(i);
+ if send_reset_in(i) = '1' then
+ tx_data(i*16+15 downto i*16) <= x"FEFE";
+ tx_k(i*2+1 downto i*2) <= "11";
+ elsif( (last_fifo_tx_empty(i) = '1') or (tx_allow_qtx(i) = '0') ) then
+ tx_data(i*16+15 downto i*16) <= x"50bc";
+ tx_k(i*2+1 downto i*2) <= "01";
+ tx_correct(i*2+1 downto i*2) <= first_idle(i) & '0';
+ else
+ tx_data(i*16+15 downto i*16) <= fifo_tx_dout(i*18+15 downto i*18);
+ tx_k(i*2+1 downto i*2) <= "00";
+ tx_correct(i*2+1 downto i*2) <= "00";
+ end if;
+ end process THE_SERDES_INPUT_PROC;
end generate;
--------------------------------------------------------------------------
-- SerDes clock output to FPGA fabric
refclk2core_out <= '0';
---Generate LED signals
-----------------------
-process( sysclk )
- begin
- if rising_edge(sysclk) then
- led_counter <= led_counter + to_unsigned(1,1);
-
- if led_counter = 0 then
- rx_led <= x"0";
- else
- rx_led <= rx_led or buf_med_dataready_out;
- end if;
- if led_counter = 0 then
- tx_led <= x"0";
- else
- tx_led <= tx_led or not (tx_k(6) & tx_k(4) & tx_k(2) & tx_k(0));
- end if;
+--------------------------------------------------------------------------
+--Generate LED signals
+--------------------------------------------------------------------------
+ PROC_LED : process begin
+ wait until rising_edge(clk_sys);
+ led_counter <= led_counter + to_unsigned(1,1);
+
+ if led_counter = 0 then
+ rx_led <= x"0";
+ else
+ rx_led <= rx_led or buf_med_dataready_out;
+ end if;
+ if led_counter = 0 then
+ tx_led <= x"0";
+ else
+ tx_led <= tx_led or not (tx_k(6) & tx_k(4) & tx_k(2) & tx_k(0));
end if;
end process;
stat_debug(i*64+63 downto i*64+60) <= buf_stat_debug(i*16+3 downto i*16+0);
end generate;
---stat_debug(3 downto 0) <= buf_stat_debug(3 downto 0); -- state_bits
---stat_debug(4) <= buf_stat_debug(4); -- alignme
---stat_debug(5) <= sfp_prsnt_n;
---stat_debug(6) <= tx_k(0);
---stat_debug(7) <= tx_k(1);
---stat_debug(8) <= rx_k_q(0);
---stat_debug(9) <= rx_k_q(1);
---stat_debug(18 downto 10) <= link_error;
---stat_debug(19) <= '0';
---stat_debug(20) <= link_ok(0);
---stat_debug(38 downto 21) <= fifo_rx_din;
---stat_debug(39) <= swap_bytes;
---stat_debug(40) <= buf_stat_debug(7); -- sfp_missing_in
---stat_debug(41) <= buf_stat_debug(8); -- sfp_los_in
---stat_debug(42) <= buf_stat_debug(6); -- resync
---stat_debug(59 downto 43) <= (others => '0');
---stat_debug(63 downto 60) <= link_error(3 downto 0);
-
end architecture;
\ No newline at end of file
-- Components
-component serdes_gbe_0_100 is
-generic(
- USER_CONFIG_FILE : String := "serdes_gbe_0_100.txt"
-);
-port(
- refclkp : in std_logic;
- refclkn : in std_logic;
- rxrefclk : in std_logic;
- refclk : in std_logic;
- rxa_pclk : out std_logic;
- rxb_pclk : out std_logic;
- hdinp_0 : in std_logic;
- hdinn_0 : in std_logic;
- hdoutp_0 : out std_logic;
- hdoutn_0 : out std_logic;
- tclk_0 : in std_logic;
- rclk_0 : in std_logic;
- tx_rst_0 : in std_logic;
- rx_rst_0 : in std_logic;
- ref_0_sclk : out std_logic;
- rx_0_sclk : out std_logic;
- txd_0 : in std_logic_vector(15 downto 0);
- tx_k_0 : in std_logic_vector(1 downto 0);
- tx_force_disp_0 : in std_logic_vector(1 downto 0);
- tx_disp_sel_0 : in std_logic_vector(1 downto 0);
- rxd_0 : out std_logic_vector(15 downto 0);
- rx_k_0 : out std_logic_vector(1 downto 0);
- rx_disp_err_detect_0 : out std_logic_vector(1 downto 0);
- rx_cv_detect_0 : out std_logic_vector(1 downto 0);
- tx_crc_init_0 : in std_logic_vector(1 downto 0);
- rx_crc_eop_0 : out std_logic_vector(1 downto 0);
- word_align_en_0 : in std_logic;
- mca_align_en_0 : in std_logic;
- felb_0 : in std_logic;
- lsm_en_0 : in std_logic;
- lsm_status_0 : out std_logic;
- mca_resync_01 : in std_logic;
- quad_rst : in std_logic;
- serdes_rst : in std_logic;
- ref_pclk : out std_logic
-);
-end component serdes_gbe_0_100;
-
component serdes_gbe_0_100_ext is
generic(
USER_CONFIG_FILE : String := "serdes_gbe_0_100_ext.txt"
);
end component;
-component serdes_gbe_0_200 is
+component serdes_200_int is
generic(
- USER_CONFIG_FILE : String := "serdes_gbe_0_200.txt"
+ USER_CONFIG_FILE : String := "serdes_200_int.txt"
);
port(
- refclkp : in std_logic;
- refclkn : in std_logic;
rxrefclk : in std_logic;
refclk : in std_logic;
rxa_pclk : out std_logic;
serdes_rst : in std_logic;
ref_pclk : out std_logic
);
-end component serdes_gbe_0_200;
+end component;
-component serdes_100_ext is
-generic(
- USER_CONFIG_FILE : String := "serdes_100_ext.txt"
-);
-port(
- refclkp : in std_logic;
- refclkn : in std_logic;
- rxrefclk : in std_logic;
- refclk : in std_logic;
- rxa_pclk : out std_logic;
- rxb_pclk : out std_logic;
- hdinp_0 : in std_logic;
- hdinn_0 : in std_logic;
- hdoutp_0 : out std_logic;
- hdoutn_0 : out std_logic;
- tclk_0 : in std_logic;
- rclk_0 : in std_logic;
- tx_rst_0 : in std_logic;
- rx_rst_0 : in std_logic;
- ref_0_sclk : out std_logic;
- rx_0_sclk : out std_logic;
- txd_0 : in std_logic_vector(15 downto 0);
- tx_k_0 : in std_logic_vector(1 downto 0);
- tx_force_disp_0 : in std_logic_vector(1 downto 0);
- tx_disp_sel_0 : in std_logic_vector(1 downto 0);
- rxd_0 : out std_logic_vector(15 downto 0);
- rx_k_0 : out std_logic_vector(1 downto 0);
- rx_disp_err_detect_0 : out std_logic_vector(1 downto 0);
- rx_cv_detect_0 : out std_logic_vector(1 downto 0);
- tx_crc_init_0 : in std_logic_vector(1 downto 0);
- rx_crc_eop_0 : out std_logic_vector(1 downto 0);
- word_align_en_0 : in std_logic;
- mca_align_en_0 : in std_logic;
- felb_0 : in std_logic;
- lsm_en_0 : in std_logic;
- lsm_status_0 : out std_logic;
- mca_resync_01 : in std_logic;
- quad_rst : in std_logic;
- serdes_rst : in std_logic;
- ref_pclk : out std_logic
-);
-end component serdes_100_ext;
-- LSM state machine signals
signal swap_bytes : std_logic; -- sysclk
-------------------------------------------------------------------------
-------------------------------------------------------------------------
-gen_serdes_0_100 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_NO generate
- THE_SERDES: serdes_gbe_0_100
- port map(
- refclkp => SD_REFCLK_P_IN, -- not used here
- refclkn => SD_REFCLK_N_IN, -- not used here
- rxrefclk => CLK, -- raw 200MHz clock
- refclk => CLK, -- raw 200MHz clock
- rxa_pclk => rx_halfclk, -- clock multiplier set by data bus width
- rxb_pclk => open,
- hdinp_0 => SD_RXD_P_IN, -- SerDes I/O
- hdinn_0 => SD_RXD_N_IN, -- SerDes I/O
- hdoutp_0 => SD_TXD_P_OUT, -- SerDes I/O
- hdoutn_0 => SD_TXD_N_OUT, -- SerDes I/O
- tclk_0 => tx_halfclk, -- 100MHz
- rclk_0 => rx_halfclk, -- 100MHz
- tx_rst_0 => '0', --JM101206 lane_rst, -- async reset
- rx_rst_0 => '0', --lane_rst, -- async reset --reset when sd_los=0 and disp_err=1 or cv=1
- ref_0_sclk => open, --tx_halfclk,
- rx_0_sclk => open, --rx_halfclk,
- txd_0 => tx_data,
- tx_k_0 => tx_k,
- tx_force_disp_0 => b"00", -- BUGBUG
- tx_disp_sel_0 => b"00", -- BUGBUG
- rxd_0 => rx_data,
- rx_k_0 => rx_k,
- rx_disp_err_detect_0 => open,
- rx_cv_detect_0 => link_error(7 downto 6),
- tx_crc_init_0 => b"00", -- CRC init (not needed)
- rx_crc_eop_0 => open, -- (not needed)
- word_align_en_0 => '1', -- word alignment
- mca_align_en_0 => '0', -- (not needed)
- felb_0 => '0', -- far end loopback disable
- lsm_en_0 => '1', -- enable LinkStateMachine
- lsm_status_0 => link_ok(0), -- link synchronisation successfull
- mca_resync_01 => '0', -- not needed
- quad_rst => '0', -- hands off - kills registers!
- serdes_rst => '0', --JM101203 quad_rst, -- unknown if will work
- ref_pclk => tx_halfclk -- clock multiplier set by data bus width
- );
-end generate;
+-- gen_serdes_0_100 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_NO generate
+-- THE_SERDES: serdes_gbe_0_100
+-- port map(
+-- refclkp => SD_REFCLK_P_IN, -- not used here
+-- refclkn => SD_REFCLK_N_IN, -- not used here
+-- rxrefclk => CLK, -- raw 200MHz clock
+-- refclk => CLK, -- raw 200MHz clock
+-- rxa_pclk => rx_halfclk, -- clock multiplier set by data bus width
+-- rxb_pclk => open,
+-- hdinp_0 => SD_RXD_P_IN, -- SerDes I/O
+-- hdinn_0 => SD_RXD_N_IN, -- SerDes I/O
+-- hdoutp_0 => SD_TXD_P_OUT, -- SerDes I/O
+-- hdoutn_0 => SD_TXD_N_OUT, -- SerDes I/O
+-- tclk_0 => tx_halfclk, -- 100MHz
+-- rclk_0 => rx_halfclk, -- 100MHz
+-- tx_rst_0 => '0', --JM101206 lane_rst, -- async reset
+-- rx_rst_0 => '0', --lane_rst, -- async reset --reset when sd_los=0 and disp_err=1 or cv=1
+-- ref_0_sclk => open, --tx_halfclk,
+-- rx_0_sclk => open, --rx_halfclk,
+-- txd_0 => tx_data,
+-- tx_k_0 => tx_k,
+-- tx_force_disp_0 => b"00", -- BUGBUG
+-- tx_disp_sel_0 => b"00", -- BUGBUG
+-- rxd_0 => rx_data,
+-- rx_k_0 => rx_k,
+-- rx_disp_err_detect_0 => open,
+-- rx_cv_detect_0 => link_error(7 downto 6),
+-- tx_crc_init_0 => b"00", -- CRC init (not needed)
+-- rx_crc_eop_0 => open, -- (not needed)
+-- word_align_en_0 => '1', -- word alignment
+-- mca_align_en_0 => '0', -- (not needed)
+-- felb_0 => '0', -- far end loopback disable
+-- lsm_en_0 => '1', -- enable LinkStateMachine
+-- lsm_status_0 => link_ok(0), -- link synchronisation successfull
+-- mca_resync_01 => '0', -- not needed
+-- quad_rst => '0', -- hands off - kills registers!
+-- serdes_rst => '0', --JM101203 quad_rst, -- unknown if will work
+-- ref_pclk => tx_halfclk -- clock multiplier set by data bus width
+-- );
+-- end generate;
gen_serdes_0_200 : if SERDES_NUM = 0 and EXT_CLOCK = c_NO and USE_200_MHZ = c_YES generate
- THE_SERDES: serdes_gbe_0_200
+ THE_SERDES: serdes_200_int
port map(
- refclkp => SD_REFCLK_P_IN, -- not used here
- refclkn => SD_REFCLK_N_IN, -- not used here
rxrefclk => CLK, -- raw 200MHz clock
refclk => CLK, -- raw 200MHz clock
- rxa_pclk => open, --rx_halfclk, -- clock multiplier set by data bus width
+ rxa_pclk => rx_halfclk, --rx_halfclk, -- clock multiplier set by data bus width
rxb_pclk => open,
hdinp_0 => SD_RXD_P_IN, -- SerDes I/O
hdinn_0 => SD_RXD_N_IN, -- SerDes I/O
rclk_0 => rx_halfclk, -- 100MHz
tx_rst_0 => '0', --JM101206 lane_rst, -- async reset
rx_rst_0 => '0', --lane_rst, -- async reset --reset when sd_los=0 and disp_err=1 or cv=1
- ref_0_sclk => tx_halfclk,
- rx_0_sclk => rx_halfclk,
+ ref_0_sclk => open,
+ rx_0_sclk => open,
txd_0 => tx_data,
tx_k_0 => tx_k,
tx_force_disp_0 => b"00", -- BUGBUG
mca_resync_01 => '0', -- not needed
quad_rst => '0', -- hands off - kills registers!
serdes_rst => '0', --JM101203 quad_rst, -- unknown if will work
- ref_pclk => open --tx_halfclk -- clock multiplier set by data bus width
+ ref_pclk => tx_halfclk --tx_halfclk -- clock multiplier set by data bus width
);
end generate;
wait until rising_edge(CLK);
if RESET = '1' then
delayed_restart_fpga <= '0';
- restart_fpga_counter <= x"FFF";
+ restart_fpga_counter <= x"000";
else
delayed_restart_fpga <= '0';
if DO_REBOOT = '1' then
- restart_fpga_counter <= x"000";
- elsif restart_fpga_counter /= x"FFF" then
+ restart_fpga_counter <= x"001";
+ elsif restart_fpga_counter /= x"000" then
restart_fpga_counter <= restart_fpga_counter + 1;
if restart_fpga_counter >= x"F00" then
delayed_restart_fpga <= '1';
sender_control <= (others => '0');
sender_target <= (others => '0');
sender_error <= (others => '0');
- dma_control_i <= (1 => RESET_TRBNET, others => '0');
+ dma_control_i <= (others => '0');
reg_extended_trigger_information <= (others => '0');
dma_config_i <= x"00000020";
wren_length_fifo <= '0';
wren_addr_fifo <= '0';
else
- dma_control_i <= (1 => RESET_TRBNET, others => '0');
+ dma_control_i <= (others => '0');
do_reprogram_i <= '0';
wren_length_fifo <= '0';
wren_addr_fifo <= '0';
begin
process begin
-
dataready <= '0';
data <= (others => '0');
packet_num <= "100";
APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0);
APL_SEQNR_OUT : out std_logic_vector (7 downto 0);
APL_LENGTH_IN : in std_logic_vector (15 downto 0);
- APL_FIFO_COUNT_OUT : out std_logic_vector (10 downto 0);
+ APL_FIFO_COUNT_OUT : out std_logic_vector (10 downto 0) := (others => '0');
-- Internal direction port
-- the ports with master or slave in their name are to be mapped by the active api
signal fifo_to_int_empty : std_logic;
-- signals for the INT to APL:
- signal fifo_to_apl_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal fifo_to_apl_packet_num_in : std_logic_vector(1 downto 0);
+ signal fifo_to_apl_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal fifo_to_apl_packet_num_in : std_logic_vector(1 downto 0) := (others => '0');
signal fifo_to_apl_write : std_logic;
- signal fifo_to_apl_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal fifo_to_apl_packet_num_out : std_logic_vector(1 downto 0);
- signal fifo_to_apl_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0);
+ signal fifo_to_apl_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal fifo_to_apl_packet_num_out : std_logic_vector(1 downto 0) := (others => '0');
+ signal fifo_to_apl_long_packet_num_out : std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
signal fifo_to_apl_read : std_logic;
signal fifo_to_apl_full : std_logic;
signal fifo_to_apl_empty : std_logic;
- signal fifo_to_apl_data_count : std_logic_vector(10 downto 0);
- signal next_fifo_to_apl_data_out : std_logic_vector(15 downto 0);
- signal next_fifo_to_apl_packet_num_out : std_logic_vector(1 downto 0);
+ signal fifo_to_apl_data_count : std_logic_vector(10 downto 0) := (others => '0');
+ signal next_fifo_to_apl_data_out : std_logic_vector(15 downto 0) := (others => '0');
+ signal next_fifo_to_apl_packet_num_out : std_logic_vector(1 downto 0) := (others => '0');
signal next_fifo_to_apl_full : std_logic;
signal next_fifo_to_apl_empty : std_logic;
signal next_last_fifo_to_apl_read: std_logic;
signal next_INT_MASTER_DATAREADY_OUT: std_logic;
signal sbuf_free, sbuf_next_READ: std_logic;
signal reg_INT_SLAVE_READ_OUT: std_logic;
- signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic;
- signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0);
- signal next_APL_PACKET_NUM_OUT, reg_APL_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0);
- signal next_APL_TYP_OUT, reg_APL_TYP_OUT, buf_APL_TYP_OUT: std_logic_vector(2 downto 0);
+ signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic := '0';
+ signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal next_APL_PACKET_NUM_OUT, reg_APL_PACKET_NUM_OUT: std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
+ signal next_APL_TYP_OUT, reg_APL_TYP_OUT, buf_APL_TYP_OUT: std_logic_vector(2 downto 0) := (others => '0');
type OUTPUT_SELECT is (HDR, DAT, TRM, TRM_COMB);
signal out_select: OUTPUT_SELECT;
- signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0);
- signal combined_header_F0, combined_header_F1, combined_header_F2, combined_header_F3 : std_logic_vector(15 downto 0);
- signal registered_header_F0, registered_header_F1, registered_header_F2, registered_header_F3 : std_logic_vector(15 downto 0);
- signal combined_trailer_F0, combined_trailer_F1, combined_trailer_F2, combined_trailer_F3 : std_logic_vector(15 downto 0);
- signal registered_trailer_F0,registered_trailer_F1, registered_trailer_F2, registered_trailer_F3 : std_logic_vector(15 downto 0);
- signal current_combined_header, current_registered_trailer, current_data : std_logic_vector(15 downto 0);
+ signal sequence_counter,next_sequence_counter : std_logic_vector(7 downto 0) := (others => '0');
+ signal combined_header_F0, combined_header_F1, combined_header_F2, combined_header_F3 : std_logic_vector(15 downto 0) := (others => '0');
+ signal registered_header_F0, registered_header_F1, registered_header_F2, registered_header_F3 : std_logic_vector(15 downto 0) := (others => '0');
+ signal combined_trailer_F0, combined_trailer_F1, combined_trailer_F2, combined_trailer_F3 : std_logic_vector(15 downto 0) := (others => '0');
+ signal registered_trailer_F0,registered_trailer_F1, registered_trailer_F2, registered_trailer_F3 : std_logic_vector(15 downto 0) := (others => '0');
+ signal current_combined_header, current_registered_trailer, current_data : std_logic_vector(15 downto 0) := (others => '0');
signal update_registered_trailer: std_logic;
signal update_registered_header : std_logic;
signal sbuf_status : std_logic_vector(2 downto 0);
signal buf_APL_RUN_OUT : std_logic;
- signal apl_send_in_down_timeout : std_logic;
- signal apl_send_in_timeout_counter : std_logic_vector(3 downto 0);
+ signal apl_send_in_down_timeout : std_logic := '0';
+ signal apl_send_in_timeout_counter : std_logic_vector(3 downto 0) := (others => '0');
begin
---------------------------------------
INT_SLAVE_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0);
INT_SLAVE_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0);
INT_SLAVE_READ_OUT : out std_logic;
-
+ CTRL_SEQNR_RESET : in std_logic;
-- Status and control port
STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0);
STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0)
signal m_READ_IN : std_logic_vector (2**c_MUX_WIDTH-1 downto 0);
signal m_DATAREADY_IN : std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);
-signal m_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
-signal m_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
+signal m_DATA_IN : std_logic_vector (4*c_DATA_WIDTH-1 downto 0);
+signal m_PACKET_NUM_IN : std_logic_vector (4*c_NUM_WIDTH-1 downto 0);
signal m_READ_OUT : std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);
signal buf_api_stat_fifo_to_apl : std_logic_vector(2**(c_MUX_WIDTH-1)*32-1 downto 0);
INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*3-1 downto i*3),
INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i),
-- Status and control port
+ CTRL_SEQNR_RESET => '0',
STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((i+1)*32-1 downto i*32),
STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((i+1)*32-1 downto i*32)
);
constant total_point_num : integer := MII_NUMBER*2**(c_MUX_WIDTH-1) + INT_NUMBER + 1;
- signal m_DATAREADY_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0);
- signal m_DATA_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0);
- signal m_PACKET_NUM_OUT: std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0);
- signal m_READ_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0);
- signal m_DATAREADY_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)-1 downto 0);
- signal m_DATA_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0);
- signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0);
- signal m_READ_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)-1 downto 0);
- signal m_ERROR_IN : std_logic_vector (MII_NUMBER*3-1 downto 0);
-
- signal hub_to_buf_INIT_DATAREADY: std_logic_vector (total_point_num-1 downto 0);
- signal hub_to_buf_INIT_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0);
- signal hub_to_buf_INIT_PACKET_NUM:std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0);
- signal hub_to_buf_INIT_READ : std_logic_vector (total_point_num-1 downto 0);
-
- signal buf_to_hub_INIT_DATAREADY : std_logic_vector (total_point_num-1 downto 0);
- signal buf_to_hub_INIT_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0);
- signal buf_to_hub_INIT_PACKET_NUM: std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0);
- signal buf_to_hub_INIT_READ : std_logic_vector (total_point_num-1 downto 0);
-
- signal hub_to_buf_REPLY_DATAREADY : std_logic_vector (total_point_num-1 downto 0);
- signal hub_to_buf_REPLY_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0);
- signal hub_to_buf_REPLY_PACKET_NUM : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0);
- signal hub_to_buf_REPLY_READ : std_logic_vector (total_point_num-1 downto 0);
-
- signal buf_to_hub_REPLY_DATAREADY : std_logic_vector (total_point_num-1 downto 0);
- signal buf_to_hub_REPLY_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0);
- signal buf_to_hub_REPLY_PACKET_NUM : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0);
- signal buf_to_hub_REPLY_READ : std_logic_vector (total_point_num-1 downto 0);
+ signal m_DATAREADY_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0) := (others => '0');
+ signal m_DATA_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal m_PACKET_NUM_OUT: std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)*c_NUM_WIDTH-1 downto 0) := (others => '0');
+ signal m_READ_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH)-1 downto 0) := (others => '0');
+ signal m_DATAREADY_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)-1 downto 0) := (others => '0');
+ signal m_DATA_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)*c_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal m_PACKET_NUM_IN : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)*c_NUM_WIDTH-1 downto 0) := (others => '0');
+ signal m_READ_OUT : std_logic_vector (MII_NUMBER*2**(c_MUX_WIDTH-1)-1 downto 0) := (others => '0');
+ signal m_ERROR_IN : std_logic_vector (MII_NUMBER*3-1 downto 0) := (others => '0');
+
+ signal hub_to_buf_INIT_DATAREADY: std_logic_vector (total_point_num-1 downto 0) := (others => '0');
+ signal hub_to_buf_INIT_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal hub_to_buf_INIT_PACKET_NUM:std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0) := (others => '0');
+ signal hub_to_buf_INIT_READ : std_logic_vector (total_point_num-1 downto 0) := (others => '0');
+
+ signal buf_to_hub_INIT_DATAREADY : std_logic_vector (total_point_num-1 downto 0) := (others => '0');
+ signal buf_to_hub_INIT_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal buf_to_hub_INIT_PACKET_NUM: std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0) := (others => '0');
+ signal buf_to_hub_INIT_READ : std_logic_vector (total_point_num-1 downto 0) := (others => '0');
+
+ signal hub_to_buf_REPLY_DATAREADY : std_logic_vector (total_point_num-1 downto 0) := (others => '0');
+ signal hub_to_buf_REPLY_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal hub_to_buf_REPLY_PACKET_NUM : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0) := (others => '0');
+ signal hub_to_buf_REPLY_READ : std_logic_vector (total_point_num-1 downto 0) := (others => '0');
+
+ signal buf_to_hub_REPLY_DATAREADY : std_logic_vector (total_point_num-1 downto 0) := (others => '0');
+ signal buf_to_hub_REPLY_DATA : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal buf_to_hub_REPLY_PACKET_NUM : std_logic_vector (total_point_num*c_NUM_WIDTH-1 downto 0) := (others => '0');
+ signal buf_to_hub_REPLY_READ : std_logic_vector (total_point_num-1 downto 0) := (others => '0');
signal HUB_INIT_DATAREADY_OUT : std_logic_vector (total_point_num-1 downto 0);
signal HUB_INIT_DATA_OUT : std_logic_vector (total_point_num*c_DATA_WIDTH-1 downto 0);
signal HUB_locked : std_logic_vector (2**(c_MUX_WIDTH-1)-1 downto 0);
- signal HC_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0);
- signal HC_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0);
+ signal HC_DATA_IN : std_logic_vector (c_DATA_WIDTH-1 downto 0) := (others => '0');
+ signal HC_PACKET_NUM_IN : std_logic_vector (c_NUM_WIDTH-1 downto 0) := (others => '0');
signal HC_DATAREADY_IN : std_logic;
signal HC_READ_OUT : std_logic;
signal HC_SHORT_TRANSFER_IN : std_logic;
signal HC_READ_IN : std_logic;
signal HC_RUN_OUT : std_logic;
signal HC_SEQNR_OUT : std_logic_vector (7 downto 0);
- signal HC_STAT_REGS : std_logic_vector (64*32-1 downto 0);
+ signal HC_STAT_REGS : std_logic_vector (64*32-1 downto 0) := (others => '0');
signal HUB_SCTRL_ERROR : std_logic_vector (MII_NUMBER-1 downto 0);
signal STAT_REG_STROBE : std_logic_vector (2**6-1 downto 0);
signal reg_STROBES : std_logic_vector (2**6-1 downto 0);
signal timer_us_tick : std_logic;
signal stat_ipu_fsm : std_logic_vector(31 downto 0);
- signal DAT_ADDR_OUT : std_logic_vector(16-1 downto 0);
+ signal DAT_ADDR_OUT : std_logic_vector(16-1 downto 0) := (others => '0');
signal DAT_READ_ENABLE_OUT : std_logic;
signal DAT_WRITE_ENABLE_OUT : std_logic;
- signal DAT_DATA_OUT : std_logic_vector(32-1 downto 0);
+ signal DAT_DATA_OUT : std_logic_vector(32-1 downto 0) := (others => '0');
signal DAT_DATA_IN : std_logic_vector(32-1 downto 0) := (others => '0');
signal DAT_DATAREADY_IN : std_logic := '0';
signal DAT_NO_MORE_DATA_IN : std_logic := '0';
signal local_network_reset : std_logic_vector(MII_NUMBER-1 downto 0);
signal local_reset_med : std_logic_vector(MII_NUMBER-1 downto 0);
- signal network_reset_counter : std_logic_vector(11 downto 0);
+ signal network_reset_counter : std_logic_vector(11 downto 0) := (others => '0');
signal stream_port_connected : std_logic;
signal iobuf_reset_sctrl_counter : std_logic;
type tv_t is array (2**(c_MUX_WIDTH-1)-1 downto 0) of std_logic_vector(15 downto 0);
- signal current_timeout_value : tv_t;
+ signal current_timeout_value : tv_t := (others => (others => '0'));
signal hub_level : std_logic_vector(3 downto 0);
type cnt_t is array (MII_NUMBER-1 downto 0) of unsigned(31 downto 0);
- signal busy_counter_excl : cnt_t;
- signal busy_counter_incl : cnt_t;
+ signal busy_counter_excl : cnt_t := (others => (others => '0'));
+ signal busy_counter_incl : cnt_t := (others => (others => '0'));
signal reg_STAT_POINTS_locked : std_logic_vector(MII_NUMBER-1 downto 0);
signal reg_excl_enable : std_logic_vector(MII_NUMBER-1 downto 0);
signal iobuf_stat_init_obuf_debug_i : std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0);
signal iobuf_stat_reply_obuf_debug_i : std_logic_vector (MII_NUMBER*32*2**(c_MUX_WIDTH-1)-1 downto 0);
- signal led_counter : unsigned(9 downto 0);
+ signal led_counter : unsigned(9 downto 0) := (others => '0');
signal hub_led_i : std_logic_vector(MII_NUMBER-1 downto 0);
signal hub_show_port : std_logic_vector(MII_NUMBER-1 downto 0);
signal buf_HUB_MISMATCH_PATTERN : std_logic_vector(31 downto 0);
type counter8b_t is array (0 to 15) of unsigned(7 downto 0);
- signal received_retransmit_requests : counter8b_t;
- signal sent_retransmit_requests : counter8b_t;
+ signal received_retransmit_requests : counter8b_t := (others => (others => '0'));
+ signal sent_retransmit_requests : counter8b_t := (others => (others => '0'));
signal dummy : std_logic_vector(270 downto 0);
signal tmp_buf_to_hub_REPLY_DATA_ctrl : std_logic_vector(15 downto 0);
local_network_reset <= (others => '0');
local_reset_med <= (others => '0');
elsif and_all(network_reset_counter(9 downto 0)) = '1' then
- local_reset_med <= local_network_reset;
+ local_reset_med <= local_network_reset;
elsif network_reset_counter /= 0 then
network_reset_counter <= network_reset_counter + 1;
else
);
end generate;
gen_trmbuf: if HUB_USED_CHANNELS(k) = 0 generate
+-- hub_to_buf_INIT_DATAREADY(i) <= '0';
+-- hub_to_buf_INIT_DATA(i*16+15 downto i*16) <= (others => '0');
+-- hub_to_buf_INIT_PACKET_NUM(i*3+2 downto i*3) <= (others => '0');
hub_to_buf_init_read(i) <= '0';
buf_to_hub_init_dataready(i) <= '0';
buf_to_hub_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH) <= (others => '0');
);
buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16) <= (others => '0');
end generate;
- gen_select_no_logic : if i = 2 generate
- buf_STAT_POINTS_locked((i+1)*32-1 downto i*32) <= (others => '0');
- buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16) <= (others => '0');
- HUB_locked(i) <= '0';
- HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32) <= (others => '0');
- HUB_REPLY_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0');
- HUB_REPLY_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH) <= (others => '0');
- HUB_REPLY_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0');
- HUB_REPLY_READ_IN(next_point_num-1 downto first_point_num) <= (others => '0');
- HUB_INIT_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0');
- HUB_INIT_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH) <= (others => '0');
- HUB_INIT_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0');
- HUB_INIT_READ_IN(next_point_num-1 downto first_point_num) <= (others => '0');
- buf_HUB_ALL_ERROR_BITS((i+1)*32-1 downto i*32) <= (others => '0');
- HUB_STAT_ERRORBITS((i+1)*32-1 downto i*32) <= (others => '0');
- hub_ctrl_final_activepoints((i+1)*32-1 downto i*32) <= (others => '0');
- buf_HUB_ALL_ERROR_BITS((i+1)*32*16-1 downto i*32*16) <= (others => '0');
- iobuf_stat_data_counter((i+1)*32-1 downto i*32) <= (others => '0');
- stat_timeout((i+1)*32-1 downto i*32) <= (others => '0');
- end generate;
end generate;
+ gen_select_no_logic : if HUB_USED_CHANNELS(i) = c_NO generate
+ HUB_REPLY_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH) <= (others => '0');
+ HUB_REPLY_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0');
+ HUB_REPLY_DATAREADY_OUT(next_point_num-1 downto first_point_num) <= (others => '0');
+ HUB_REPLY_READ_IN(next_point_num-1 downto first_point_num) <= (others => '0');
+ HUB_INIT_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0');
+ HUB_INIT_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH) <= (others => '0');
+ HUB_INIT_DATAREADY_OUT(next_point_num-1 downto first_point_num) <= (others => '0');
+ HUB_INIT_PACKET_NUM_IN(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0');
+ HUB_INIT_READ_OUT(next_point_num-1 downto first_point_num) <= (others => '0');
+ end generate;
end generate;
-
+ gen_unused_signals : if 1 =1 generate
+ constant i : integer := 2;
+ begin
+ buf_STAT_POINTS_locked((i+1)*32-1 downto i*32) <= (others => '0');
+ buf_HUB_STAT_CHANNEL((i+1)*16-1 downto i*16) <= (others => '0');
+ HUB_locked(i) <= '0';
+ HUB_CTRL_final_activepoints((i+1)*32-1 downto i*32) <= (others => '0');
+ buf_HUB_ALL_ERROR_BITS((i+1)*32-1 downto i*32) <= (others => '0');
+ HUB_STAT_ERRORBITS((i+1)*32-1 downto i*32) <= (others => '0');
+ hub_ctrl_final_activepoints((i+1)*32-1 downto i*32) <= (others => '0');
+ buf_HUB_ALL_ERROR_BITS((i+1)*32*16-1 downto i*32*16) <= (others => '0');
+ iobuf_stat_data_counter((i+1)*32-1 downto i*32) <= (others => '0');
+ stat_timeout((i+1)*32-1 downto i*32) <= (others => '0');
+ end generate;
---------------------------------------------------------------------
--Control RegIO
---------------------------------------------------------------------
);
-
--- THE_BUS_HANDLER : trb_net16_regio_bus_handler
--- generic map(
--- PORT_NUMBER => 7,
--- PORT_ADDRESSES => (0 => x"8000", 1 => x"4000", 2 => x"4020", 3 => x"4030", 4 => x"4040", 5 => x"4050", 6 => x"4060", others => x"0000"),
--- PORT_ADDR_MASK => (0 => 15, 1 => 5, 2 => 4, 3 => 4, 4 => 4, 5 => 0, 6 => 4, others => 0)
--- )
--- port map(
--- CLK => CLK,
--- RESET => reset_i,
---
--- DAT_ADDR_IN => DAT_ADDR_OUT,
--- DAT_DATA_IN => DAT_DATA_OUT,
--- DAT_DATA_OUT => DAT_DATA_IN,
--- DAT_READ_ENABLE_IN => DAT_READ_ENABLE_OUT,
--- DAT_WRITE_ENABLE_IN => DAT_WRITE_ENABLE_OUT,
--- DAT_TIMEOUT_IN => DAT_TIMEOUT_OUT,
--- DAT_DATAREADY_OUT => DAT_DATAREADY_IN,
--- DAT_WRITE_ACK_OUT => DAT_WRITE_ACK_IN,
--- DAT_NO_MORE_DATA_OUT => DAT_NO_MORE_DATA_IN,
--- DAT_UNKNOWN_ADDR_OUT => DAT_UNKNOWN_ADDR_IN,
---
--- BUS_ADDR_OUT(15 downto 0) => REGIO_ADDR_OUT,
--- BUS_DATA_OUT(31 downto 0) => REGIO_DATA_OUT,
--- BUS_READ_ENABLE_OUT(0) => REGIO_READ_ENABLE_OUT,
--- BUS_WRITE_ENABLE_OUT(0) => REGIO_WRITE_ENABLE_OUT,
--- BUS_TIMEOUT_OUT(0) => REGIO_TIMEOUT_OUT,
--- BUS_DATA_IN(31 downto 0) => REGIO_DATA_IN,
--- BUS_DATAREADY_IN(0) => REGIO_DATAREADY_IN,
--- BUS_WRITE_ACK_IN(0) => REGIO_WRITE_ACK_IN,
--- BUS_NO_MORE_DATA_IN(0) => REGIO_NO_MORE_DATA_IN,
--- BUS_UNKNOWN_ADDR_IN(0) => REGIO_UNKNOWN_ADDR_IN,
---
--- BUS_ADDR_OUT(20 downto 16) => stat_packets_addr,
--- BUS_ADDR_OUT(31 downto 21) => open,
--- BUS_DATA_OUT(63 downto 32) => open,
--- BUS_READ_ENABLE_OUT(1) => stat_packets_read,
--- BUS_WRITE_ENABLE_OUT(1) => stat_packets_write,
--- BUS_TIMEOUT_OUT(1) => open,
--- BUS_DATA_IN(63 downto 32) => stat_packets_data,
--- BUS_DATAREADY_IN(1) => stat_packets_ready,
--- BUS_WRITE_ACK_IN(1) => stat_packets_ack,
--- BUS_NO_MORE_DATA_IN(1) => '0',
--- BUS_UNKNOWN_ADDR_IN(1) => stat_packets_unknown,
---
--- BUS_ADDR_OUT(35 downto 32) => stat_errorbits_addr,
--- BUS_ADDR_OUT(47 downto 36) => open,
--- BUS_DATA_OUT(95 downto 64) => open,
--- BUS_READ_ENABLE_OUT(2) => stat_errorbits_read,
--- BUS_WRITE_ENABLE_OUT(2) => stat_errorbits_write,
--- BUS_TIMEOUT_OUT(2) => open,
--- BUS_DATA_IN(95 downto 64) => stat_errorbits_data,
--- BUS_DATAREADY_IN(2) => stat_errorbits_ready,
--- BUS_WRITE_ACK_IN(2) => '0',
--- BUS_NO_MORE_DATA_IN(2) => '0',
--- BUS_UNKNOWN_ADDR_IN(2) => stat_packets_unknown,
---
--- BUS_ADDR_OUT(51 downto 48) => stat_busycntincl_addr,
--- BUS_ADDR_OUT(63 downto 52) => open,
--- BUS_DATA_OUT(127 downto 96) => open,
--- BUS_READ_ENABLE_OUT(3) => stat_busycntincl_read,
--- BUS_WRITE_ENABLE_OUT(3) => stat_busycntincl_write,
--- BUS_TIMEOUT_OUT(3) => open,
--- BUS_DATA_IN(127 downto 96) => stat_busycntincl_data,
--- BUS_DATAREADY_IN(3) => stat_busycntincl_ready,
--- BUS_WRITE_ACK_IN(3) => stat_busycntincl_ack,
--- BUS_NO_MORE_DATA_IN(3) => '0',
--- BUS_UNKNOWN_ADDR_IN(3) => stat_busycntincl_unknown,
---
--- BUS_ADDR_OUT(67 downto 64) => stat_busycntexcl_addr,
--- BUS_ADDR_OUT(79 downto 68) => open,
--- BUS_DATA_OUT(159 downto 128) => open,
--- BUS_READ_ENABLE_OUT(4) => stat_busycntexcl_read,
--- BUS_WRITE_ENABLE_OUT(4) => stat_busycntexcl_write,
--- BUS_TIMEOUT_OUT(4) => open,
--- BUS_DATA_IN(159 downto 128) => stat_busycntexcl_data,
--- BUS_DATAREADY_IN(4) => stat_busycntexcl_ready,
--- BUS_WRITE_ACK_IN(4) => stat_busycntexcl_ack,
--- BUS_NO_MORE_DATA_IN(4) => '0',
--- BUS_UNKNOWN_ADDR_IN(4) => stat_busycntexcl_unknown,
---
--- BUS_ADDR_OUT(95 downto 80) => open,
--- BUS_DATA_OUT(191 downto 160) => open,
--- BUS_READ_ENABLE_OUT(5) => stat_globaltime_read,
--- BUS_WRITE_ENABLE_OUT(5) => stat_globaltime_write,
--- BUS_TIMEOUT_OUT(5) => open,
--- BUS_DATA_IN(191 downto 160) => global_time,
--- BUS_DATAREADY_IN(5) => last_stat_globaltime_read,
--- BUS_WRITE_ACK_IN(5) => '0',
--- BUS_NO_MORE_DATA_IN(5) => '0',
--- BUS_UNKNOWN_ADDR_IN(5) => last_stat_globaltime_write,
---
--- BUS_ADDR_OUT(99 downto 96) => lsm_addr,
--- BUS_ADDR_OUT(111 downto 100) => open,
--- BUS_DATA_OUT(223 downto 192) => open,
--- BUS_READ_ENABLE_OUT(6) => lsm_read,
--- BUS_WRITE_ENABLE_OUT(6) => lsm_write,
--- BUS_TIMEOUT_OUT(6) => open,
--- BUS_DATA_IN(223 downto 192) => lsm_data,
--- BUS_DATAREADY_IN(6) => last_lsm_read,
--- BUS_WRITE_ACK_IN(6) => '0',
--- BUS_NO_MORE_DATA_IN(6) => '0',
--- BUS_UNKNOWN_ADDR_IN(6) => lsm_write,
---
--- STAT_DEBUG => open
--- );
-
--Fucking Modelsim wants it like this...
THE_BUS_HANDLER : trb_net16_regio_bus_handler
generic map(
end loop;
end if;
- end if;
- end process;
-
-
- PROC_REG_STAT_REGS : process(CLK)
- begin
- if rising_edge(CLK) then
HC_STAT_REGS(8*32-1 downto 0) <= buf_HC_STAT_REGS(8*32-1 downto 0);
HC_STAT_REGS(36*32-1 downto 16*32) <= buf_HC_STAT_REGS(36*32-1 downto 16*32);
HC_STAT_REGS(64*32-1 downto 39*32) <= buf_HC_STAT_REGS(64*32-1 downto 39*32);
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
--- USE IEEE.std_logic_ARITH.ALL;
--- USE IEEE.std_logic_UNSIGNED.ALL;
use ieee.numeric_std.all;
library work;
begin
if rising_edge(CLK) then
if RESET = '1' then
- current_rec_buffer_size_out <= (others => '0');
+ current_rec_buffer_size_out <= x"0";
reg_ack_init_internal <= '0';
reg_ack_reply_internal <= '0';
reg_read_out <= '0';
--- for a description see HADES wiki
--- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIBUF
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
INT_ERROR_OUT : out std_logic_vector (2 downto 0);
-- Status and control port
STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0);
- STAT_BUFFER : out std_logic_vector (31 downto 0)
+ STAT_DATA_COUNTER : out std_logic_vector (31 downto 0);
+ STAT_BUFFER : out std_logic_vector (31 downto 0);
+ CTRL_STAT : in std_logic_vector (15 downto 0)
);
end entity;
begin -- process
got_ack_init_internal <= '0';
got_ack_reply_internal <= '0';
- next_read_out <= not fifo_full;
+ next_read_out <= '1';
fifo_write <= '0';
next_rec_buffer_size_out <= current_rec_buffer_size_out;
next_error_state <= current_error_state;
begin
if rising_edge(CLK) then
if RESET = '1' then
- current_rec_buffer_size_out <= (others => '0');
+ current_rec_buffer_size_out <= x"6";
reg_ack_init_internal <= '0';
reg_ack_reply_internal <= '0';
reg_read_out <= '0';
signal port_select_int : integer range 0 to PORT_NUMBER; --c_BUS_HANDLER_MAX_PORTS;
signal next_port_select_int : integer range 0 to PORT_NUMBER; --c_BUS_HANDLER_MAX_PORTS;
- signal buf_BUS_READ_OUT : std_logic_vector(PORT_NUMBER downto 0);
- signal buf_BUS_WRITE_OUT : std_logic_vector(PORT_NUMBER downto 0);
- signal buf_BUS_DATA_OUT : std_logic_vector(31 downto 0);
- signal buf_BUS_ADDR_OUT : std_logic_vector(15 downto 0);
+ signal buf_BUS_READ_OUT : std_logic_vector(PORT_NUMBER downto 0) := (others => '0');
+ signal buf_BUS_WRITE_OUT : std_logic_vector(PORT_NUMBER downto 0) := (others => '0');
+ signal buf_BUS_DATA_OUT : std_logic_vector(31 downto 0) := x"00000000";
+ signal buf_BUS_ADDR_OUT : std_logic_vector(15 downto 0) := x"0000";
signal buf_BUS_DATA_IN : std_logic_vector(32*PORT_NUMBER+31 downto 0);
signal buf_BUS_DATAREADY_IN : std_logic_vector(PORT_NUMBER downto 0);
generic(\r
SERDES_NUM : integer range 0 to 3 := 0;\r
EXT_CLOCK : integer range 0 to 1 := c_NO;\r
- USE_200_MHZ: integer range 0 to 1 := c_YES\r
+ USE_200_MHZ: integer range 0 to 1 := c_YES;\r
+ USE_125_MHZ: integer range 0 to 1 := c_NO\r
);\r
port(\r
CLK : in std_logic; -- SerDes clock\r
\r
\r
\r
+component priority_arbiter is\r
+ generic(\r
+ INPUT_WIDTH : integer := 8\r
+ );\r
+ port(\r
+ CLK : in std_logic;\r
+ ENABLE : in std_logic;\r
+ INPUT : in std_logic_vector(INPUT_WIDTH-1 downto 0);\r
+ OUTPUT_VEC : out std_logic_vector(INPUT_WIDTH-1 downto 0);\r
+ OUTPUT_NUM : out integer\r
+ );\r
+end component;\r
\r
\r
\r
when "001" => ID_OUT(31 downto 16) <= word;
when "010" => ID_OUT(47 downto 32) <= word;
when "011" => ID_OUT(63 downto 48) <= word;
+ when others => null;
end case;
end if;
end process;
when "001" => ID_OUT(31 downto 16) <= buf_DATA_OUT;
when "010" => ID_OUT(47 downto 32) <= buf_DATA_OUT;
when "011" => ID_OUT(63 downto 48) <= buf_DATA_OUT;
+ when others => null;
end case;
end if;
end process;
);\r
end component fifo_19x16_obuf;\r
\r
+\r
+\r
-- State description:\r
--\r
-- IDLE: wait for any data to be written into the FIFO\r
AmFullThresh => x"b",\r
Q => fifo_data_o,\r
WCNT => fifo_wcnt_stdlv,\r
+ Empty => open,\r
Full => fifo_full,\r
AlmostFull => fifo_almostfull\r
);\r
\r
fifo_wcnt <= unsigned(fifo_wcnt_stdlv);\r
\r
+\r
---------------------------------------------------------------------\r
-- State machine\r
---------------------------------------------------------------------\r
jspc29 / trbnet.git / commitdiff