--- /dev/null
+library ieee;
+ use ieee.std_logic_1164.all;
+ use ieee.numeric_std.all;
+
+library work;
+ use work.trb_net_components.all;
+ use work.trb_net_std.all;
+ use work.trb3_components.all;
+ use work.config.all;
+
+entity clock_reset_handler_240 is
+ port (
+ CLOCK_IN : in std_logic; -- oscillator
+ RESET_FROM_NET : in std_logic;
+ CLOCK_SELECT_IN : in std_logic;
+
+ BUS_RX : in CTRLBUS_RX;
+ BUS_TX : out CTRLBUS_TX;
+
+ RESET_OUT : out std_logic;
+ CLEAR_OUT : out std_logic;
+ GSR_OUT : out std_logic;
+
+ RAW_CLK_OUT : out std_logic; -- 200/240 MHz for FPGA fabric
+ SYS_CLK_OUT : out std_logic; -- 100/120 MHz for FPGA fabric
+ REF_CLK_OUT : out std_logic; -- 200/240 internal reference clock
+ REF_CLK_240_OUT : out std_logic;
+
+ DEBUG_OUT : out std_logic_vector(31 downto 0)
+ );
+end entity;
+
+architecture clock_reset_handler_240_arch of clock_reset_handler_240 is
+
+attribute syn_keep : boolean;
+attribute syn_preserve : boolean;
+signal clock_100, clock_120, clock_200, clock_240: std_logic;
+signal sys_clk_i : std_logic;
+signal timer : unsigned(16 downto 0) := (others => '0');
+signal clear_n_i : std_logic := '0';
+signal reset_i : std_logic;
+
+signal pll_lock_200 : std_logic;
+signal pll_lock_240 : std_logic;
+signal pll_lock : std_logic;
+
+attribute syn_keep of clear_n_i : signal is true;
+attribute syn_preserve of clear_n_i : signal is true;
+
+begin
+
+
+SYS_CLK_OUT <= sys_clk_i;
+GSR_OUT <= not pll_lock or clear_n_i;
+
+ THE_INT_PLL : entity work.pll_200_100
+ port map(
+ CLK => CLOCK_IN,
+ CLKOP => clock_100,
+ CLKOS => clock_200,
+ LOCK => pll_lock_200
+ );
+
+ THE_PLL_240 : entity work.pll_200_240
+ port map(
+ CLK => CLOCK_IN,
+ CLKOP => clock_240,
+ LOCK => pll_lock_240
+ );
+
+ pll_lock <= pll_lock_200 and pll_lock_240;
+
+--
+--
+-- THE_PLL : entity work.pll_240_100
+-- port map(
+-- CLKI => CLOCK_IN,
+-- CLKOP => clock_200,
+-- CLKOS => clock_100,
+-- CLKOS2 => clock_240,
+-- CLKOS3 => clock_120,
+-- LOCK => pll_lock
+-- );
+
+gen_slow_clock : if USE_120_MHZ = 0 generate
+ RAW_CLK_OUT <= CLOCK_IN;
+ sys_clk_i <= clock_100;
+ REF_CLK_OUT <= clock_200;
+end generate;
+
+REF_CLK_240_OUT <= clock_240;
+
+-- gen_fast_clock : if USE_120_MHZ = 1 generate
+-- RAW_CLK_OUT <= clock_240;
+-- sys_clk_i <= clock_120;
+-- REF_CLK_OUT <= clock_240;
+-- end generate;
+
+
+clear_n_i <= timer(16) when rising_edge(CLOCK_IN);
+
+process begin
+ wait until rising_edge(sys_clk_i);
+ if timer(16) = '1' then
+ timer <= timer;
+ else
+ timer <= timer + 1;
+ end if;
+end process;
+
+
+---------------------------------------------------------------------------
+-- Reset generation
+---------------------------------------------------------------------------
+THE_RESET_HANDLER : trb_net_reset_handler
+ generic map(
+ RESET_DELAY => x"FEEE"
+ )
+ port map(
+ CLEAR_IN => '0', -- reset input (high active, async)
+ CLEAR_N_IN => clear_n_i, -- reset input (low active, async)
+ CLK_IN => CLOCK_IN, -- raw master clock, NOT from PLL/DLL!
+ SYSCLK_IN => sys_clk_i, -- PLL/DLL remastered clock
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
+ RESET_IN => '0', -- general reset signal (SYSCLK)
+ TRB_RESET_IN => RESET_FROM_NET, -- TRBnet reset signal (SYSCLK)
+ CLEAR_OUT => CLEAR_OUT, -- async reset out, USE WITH CARE!
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
+ DEBUG_OUT => open
+ );
+
+RESET_OUT <= reset_i;
+
+
+---------------------------------------------------------------------------
+-- Slow clock for DCDC converters
+---------------------------------------------------------------------------
+DEBUG_OUT(0) <= pll_lock;
+DEBUG_OUT(1) <= clear_n_i;
+DEBUG_OUT(31 downto 2) <= (others => '0');
+
+
+THE_REG : process begin
+ wait until rising_edge(sys_clk_i);
+ BUS_TX.unknown <= '0';
+ BUS_TX.ack <= '0';
+ BUS_TX.nack <= '0';
+ if BUS_RX.read = '1' then
+ BUS_TX.data <= (others => '0');
+ BUS_TX.data(0) <= CLOCK_SELECT_IN;
+ BUS_TX.ack <= '1';
+ elsif BUS_RX.write = '1' then
+ BUS_TX.unknown <= '1';
+ end if;
+
+end process;
+
+
+
+
+
+
+end architecture;
MULTICYCLE TO CLKNET "THE_MEDIA*/sci_write_i" 15 ns;
MULTICYCLE FROM CLKNET "THE_MEDIA*/sci_write_i" 15 ns;
-MULTICYCLE FROM CELL "THE_MEDIA*/gen_control.*.gen_used_control.THE_MED_CONTROL/THE_RX_FSM/cs*" TO CELL "THE_MEDIA*/THE_SCI_READER/*" 20 ns;
+MULTICYCLE FROM CELL "THE_MEDIA*/*THE_MED_CONTROL/THE_RX_FSM/cs*" TO CELL "THE_MEDIA*/THE_SCI_READER/*" 20 ns;
MULTICYCLE TO ASIC "THE_MEDIA*/THE_SERDES/PCSD_INST" PIN SCIRD 15 ns;
MAXDELAY TO ASIC "THE_MEDIA*/THE_SERDES/PCSD_INST" PIN SCIRD 15 ns;
BLOCK PATH FROM PORT "TEMPSENS";
BLOCK PATH TO PORT "TEST_LINE";
+BLOCK PATH FROM CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/sd_los_i" TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_FSM/rst_n_refclk*";
+BLOCK PATH FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset_2[1]" TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_FSM/rst_n_refclk*";
+BLOCK PATH FROM CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/gen_link_reset.link_reset_pulse/pulse_b" TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_RX_FSM/rst_n_refclk*";
#Basic Infrastructure
add_file -vhdl -lib work "../cores/pll_200_100.vhd"
+add_file -vhdl -lib work "../cores/pll_200_240.vhd"
add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd"
add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd"
add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd"
-add_file -vhdl -lib work "../code/clock_reset_handler_combiner.vhd"
+add_file -vhdl -lib work "../code/clock_reset_handler_combiner_240.vhd"
add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd"
add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_240_0.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_240_3.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4_slave3.vhd"
-add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd"
+add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_240.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4.vhd"
add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd"
constant mii : integer := INTERFACE_NUM-1;
signal clk_sys, clk_full, clk_full_osc : std_logic;
+ signal ref_clk_240 : std_logic;
signal GSR_N : std_logic;
signal reset_i : std_logic;
signal clear_i : std_logic;
---------------------------------------------------------------------------
-- Clock & Reset Handling
---------------------------------------------------------------------------
-THE_CLOCK_RESET : entity work.clock_reset_handler
+THE_CLOCK_RESET : entity work.clock_reset_handler_240
port map(
CLOCK_IN => CLOCK_PCLK,
RESET_FROM_NET => make_reset,--med2int(INTERFACE_NUM).stat_op(13),--make_reset
RAW_CLK_OUT => open,
SYS_CLK_OUT => clk_sys,
REF_CLK_OUT => clk_full_osc,
+ REF_CLK_240_OUT => ref_clk_240,
DEBUG_OUT => debug_clock_reset
);
-- TrbNet Uplink
---------------------------------------------------------------------------
-THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync
+THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync_240
generic map(
SERDES_NUM => 0,
IS_SYNC_SLAVE => c_YES
)
port map(
CLK_REF_FULL => med2int(INTERFACE_NUM).clk_full,
- CLK_INTERNAL_FULL => clk_full_osc,
+ CLK_INTERNAL_FULL => ref_clk_240,
SYSCLK => clk_sys,
RESET => reset_i,
CLEAR => clear_i,
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_200_240" module="pll_200_240" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2020 09 22 09:45:48.827" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="pll_200_240.lpc" type="lpc" modified="2020 09 22 09:45:44.000"/>
+ <File name="pll_200_240.vhd" type="top_level_vhdl" modified="2020 09 22 09:45:44.000"/>
+ <File name="pll_200_240_tmpl.vhd" type="template_vhdl" modified="2020 09 22 09:45:44.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=latticeecp3
+PartType=LAE3-17EA
+PartName=LAE3-17EA-6FN484E
+SpeedGrade=6
+Package=FPBGA484
+OperatingCondition=AUTO
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll_200_240
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=09/22/2020
+Time=09:45:44
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+Type=ehxpllb
+mode=normal
+IFrq=200
+Div=5
+ClkOPBp=0
+Post=4
+U_OFrq=240
+OP_Tol=0.0
+OFrq=240.000000
+DutyTrimP=Rising
+DelayMultP=0
+fb_mode=Internal
+Mult=6
+Phase=0.0
+Duty=8
+DelayMultS=0
+DPD=50% Duty
+DutyTrimS=Rising
+DelayMultD=0
+ClkOSDelay=0
+PhaseDuty=Static
+CLKOK_INPUT=CLKOP
+SecD=2
+U_KFrq=50
+OK_Tol=0.0
+KFrq=
+ClkRst=0
+PCDR=0
+FINDELA=0
+VcoRate=
+Bandwidth=1.461042
+;DelayControl=No
+EnCLKOS=0
+ClkOSBp=0
+EnCLKOK=0
+ClkOKBp=0
+enClkOK2=0
+
+[Command]
+cmd_line= -w -n pll_200_240 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 240 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -noclkok -norst -noclkok2 -bw
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.2.446
+-- Module Version: 5.7
+--/usr/local/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll_200_240 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 240 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -noclkok -norst -noclkok2 -bw
+
+-- Tue Sep 22 09:45:44 2020
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp3;
+use ecp3.components.all;
+-- synopsys translate_on
+
+entity pll_200_240 is
+ port (
+ CLK: in std_logic;
+ CLKOP: out std_logic;
+ LOCK: out std_logic);
+end pll_200_240;
+
+architecture Structure of pll_200_240 is
+
+ -- internal signal declarations
+ signal CLKOP_t: std_logic;
+ signal CLKFB_t: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component EHXPLLF
+ generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String;
+ DELAY_PWD : in String; DELAY_VAL : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String;
+ CLKOS_BYPASS : in String; CLKOP_BYPASS : in String;
+ PHASE_DELAY_CNTL : in String; DUTY : in Integer;
+ PHASEADJ : in String; CLKOK_DIV : in Integer;
+ CLKOP_DIV : in Integer; CLKFB_DIV : in Integer;
+ CLKI_DIV : in Integer; FIN : in String);
+ port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic;
+ RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic;
+ DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic;
+ DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic;
+ DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic;
+ FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic;
+ CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic;
+ LOCK: out std_logic; CLKINTFB: out std_logic);
+ end component;
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "240.000000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLF
+ generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED",
+ CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED",
+ CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0,
+ CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING",
+ PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0",
+ CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 6, CLKI_DIV=> 5,
+ FIN=> "200.000000")
+ port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>scuba_vlo,
+ RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo,
+ DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo,
+ DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo,
+ DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo,
+ FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t,
+ CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK,
+ CLKINTFB=>CLKFB_t);
+
+ CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library ecp3;
+configuration Structure_CON of pll_200_240 is
+ for Structure
+ for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for;
+ for all:VLO use entity ecp3.VLO(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
jspc29 / dirich.git / commitdiff