added TDC DATA FORMAT information to the config.vhd

diff --git a/32PinAddOn/config.vhd b/32PinAddOn/config.vhd
index bc76880440a9fd31fe32a6e2300e45bf0c7943c4..75926416f562ccc8e447f178daf3929b95fb7de3 100644 (file)
--- a/32PinAddOn/config.vhd
+++ b/32PinAddOn/config.vhd
@@ -18,11 +18,18 @@ package config is
   -- 1: same channel,
   -- 2: alternating channels,
   -- 3: same channel with stretcher
-  constant RING_BUFFER_SIZE        : integer range 0 to 7  := 1;  --ring buffer size:  0, 1, 2,  3,  7   --> change names in constraints file
-                                                                  --ring buffer size: 32,64,96,128,dyn
-
-  constant EVENT_BUFFER_SIZE       : integer range 9 to 13 := 11; -- size of the event buffer, 2**N
-  constant EVENT_MAX_SIZE          : integer := 1024;             --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
+  constant RING_BUFFER_SIZE        : integer range 0 to 7  := 0;  --ring buffer size
+  -- mode:  0,  1,  2,   3,   7
+  -- size: 32, 64, 96, 128, dyn
+  constant TDC_DATA_FORMAT         : integer range 0 to 15 := 1;  --type of data format for the TDC
+  --  0: Single fine time as the sum of the two transitions
+  --  1: Double fine time, individual transitions
+  -- 13: Debug - single fine time and the chain for the 0x3ff hits
+  -- 14: Debug - single fine time and the ROM addresses for the two transitions
+  -- 15: Debug - complete carry chain dump
+  
+  constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 11;  -- size of the event buffer, 2**N
+  constant EVENT_MAX_SIZE    : integer               := 1024;  --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2
 
   constant INCLUDE_UART           : integer  := c_NO;
   constant INCLUDE_SPI            : integer  := c_YES;

diff --git a/32PinAddOn/trb3_periph_32PinAddOn.prj b/32PinAddOn/trb3_periph_32PinAddOn.prj
index aac04c1300ee94ca3bf05bde5002f956dab6df6d..84d3791a36ac3b130231535d9712af8479fcc5a0 100644 (file)
--- a/32PinAddOn/trb3_periph_32PinAddOn.prj
+++ b/32PinAddOn/trb3_periph_32PinAddOn.prj
@@ -1,3 +1,5 @@
+# load configuration derived from config.vhd by compile_constraints.pl
+source workdir/trb3_periph_32PinAddOn_prjconfig.tcl
 
 # implementation: "workdir"
 impl -add workdir -type fpga
@@ -87,6 +89,7 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd"
 
 add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd"
@@ -110,6 +113,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd"
 add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd"
+add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd"
 add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd"
 
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" 
@@ -153,6 +157,7 @@ add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd"
 add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd"
 add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd"
+add_file -vhdl -lib work "../base/code/input_to_trigger_logic.vhd"
 add_file -vhdl -lib work "../base/code/input_to_trigger_logic_record.vhd"
 add_file -vhdl -lib work "../base/code/input_statistics.vhd"
 add_file -vhdl -lib work "../base/code/sedcheck.vhd"
@@ -161,22 +166,22 @@ add_file -vhdl -lib work "../base/code/sedcheck.vhd"
 add_file -vhdl -lib work "tdc_release/tdc_components.vhd"
 add_file -vhdl -lib work "tdc_release/bit_sync.vhd"
 add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd"
-add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
+#add_file -vhdl -lib work "tdc_release/BusHandler.vhd"
 add_file -vhdl -lib work "tdc_release/Channel.vhd"
+add_file -vhdl -lib work "tdc_release/Channel_200.vhd"
 add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd"
+#add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd"
 add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd"
 add_file -vhdl -lib work "tdc_release/hit_mux.vhd"
 add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd"
-add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
 add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd"
 add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp3.vhd"
 add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd"
 add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd"
 add_file -vhdl -lib work "tdc_release/Stretcher_B.vhd"
 add_file -vhdl -lib work "tdc_release/Stretcher.vhd"
-add_file -vhdl -lib work "tdc_release/TDC.vhd"
+#add_file -vhdl -lib work "tdc_release/TDC.vhd"
 add_file -vhdl -lib work "tdc_release/TDC_record.vhd"
-add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
 add_file -vhdl -lib work "tdc_release/up_counter.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd"
@@ -187,5 +192,16 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd"
 add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in125_out33.vhd"
 
+if {$TDC_DATA_FORMAT == 0 | $TDC_DATA_FORMAT == 1 | $TDC_DATA_FORMAT == 14} {
+add_file -vhdl -lib work "tdc_release/Readout_record.vhd"
+add_file -vhdl -lib work "tdc_release/TriggerHandler.vhd"
+}
+if {$TDC_DATA_FORMAT == 13 | $TDC_DATA_FORMAT == 15} {
+add_file -vhdl -lib work "tdc_release/Readout_record_noDecode.vhd"
+add_file -vhdl -lib work "tdc_release/TriggerHandler_noDecode.vhd"
+}
+
+
+
 add_file -vhdl -lib work "trb3_periph_32PinAddOn.vhd"