---Media interface for Lattice ECP3 using PCS at 2GHz
--- TAB=3
-LIBRARY IEEE;
-USE IEEE.std_logic_1164.ALL;
-USE IEEE.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.med_sync_define.all;
-use work.soda_components.all;
-
-entity med_ecp3_sfp_sync_up is
- generic( SERDES_NUM : integer range 0 to 3 := 0;
- IS_SYNC_SLAVE : integer := c_YES); --select slave mode
- port(
- OSCCLK : in std_logic; -- 200 MHz reference clock
- SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock
- RESET : in std_logic; -- synchronous reset
- CLEAR : in std_logic; -- asynchronous reset
- --Internal Connection TX
- MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);
- MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);
- MED_DATAREADY_IN : in std_logic;
- MED_READ_OUT : out std_logic := '0';
- --Internal Connection RX
- MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');
- MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');
- MED_DATAREADY_OUT : out std_logic := '0';
- MED_READ_IN : in std_logic;
- RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
- RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
- TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz
- TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz
- RX_CDR_LOL_OUT : out std_logic := '0'; -- CLOCK_DATA RECOVERY LOSS_OF_LOCK !PL14082014
-
- --Sync operation
- RX_DLM : out std_logic := '0';
- RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";
- TX_DLM : in std_logic := '0';
- TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";
- TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL!
- LINK_PHASE_OUT : out std_logic := '0'; --PL!
- LINK_READY_OUT : out std_logic := '0'; --PL!
-
- --SFP Connection
- SD_RXD_P_IN : in std_logic;
- SD_RXD_N_IN : in std_logic;
- SD_TXD_P_OUT : out std_logic;
- SD_TXD_N_OUT : out std_logic;
- SD_REFCLK_P_IN : in std_logic; --not used
- SD_REFCLK_N_IN : in std_logic; --not used
- SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)
- SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)
- SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable
- --Control Interface
- SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');
- SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');
- SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');
- SCI_READ : in std_logic := '0';
- SCI_WRITE : in std_logic := '0';
- SCI_ACK : out std_logic := '0';
- SCI_NACK : out std_logic := '0';
- -- Status and control port
- STAT_OP : out std_logic_vector (15 downto 0);
- CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');
- STAT_DEBUG : out std_logic_vector (63 downto 0);
- CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')
- );
-end entity;
-
-
-architecture med_ecp3_sfp_sync_up_arch of med_ecp3_sfp_sync_up is
-
--- Placer Directives
-attribute HGROUP : string;
--- for whole architecture
-attribute HGROUP of med_ecp3_sfp_sync_up_arch : architecture is "media_uplink_group";
-attribute syn_sharing : string;
-attribute syn_sharing of med_ecp3_sfp_sync_up_arch : architecture is "off";
-
-
-component DCS
--- synthesis translate_off
+--Media interface for Lattice ECP3 using PCS at 2GHz\r
+-- TAB=3\r
+LIBRARY IEEE;\r
+USE IEEE.std_logic_1164.ALL;\r
+USE IEEE.numeric_std.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.med_sync_define.all;\r
+use work.soda_components.all;\r
+\r
+entity med_ecp3_sfp_sync_up is\r
+ generic( SERDES_NUM : integer range 0 to 3 := 0;\r
+ IS_SYNC_SLAVE : integer := c_YES); --select slave mode\r
+ port(\r
+ OSCCLK : in std_logic; -- 200 MHz reference clock\r
+ SYSCLK : in std_logic; -- 100 MHz main clock net, synchronous to RX clock\r
+ RESET : in std_logic; -- synchronous reset\r
+ CLEAR : in std_logic; -- asynchronous reset\r
+ --Internal Connection TX\r
+ MED_DATA_IN : in std_logic_vector(c_DATA_WIDTH-1 downto 0);\r
+ MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0);\r
+ MED_DATAREADY_IN : in std_logic;\r
+ MED_READ_OUT : out std_logic := '0';\r
+ --Internal Connection RX\r
+ MED_DATA_OUT : out std_logic_vector(c_DATA_WIDTH-1 downto 0) := (others => '0');\r
+ MED_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0) := (others => '0');\r
+ MED_DATAREADY_OUT : out std_logic := '0';\r
+ MED_READ_IN : in std_logic;\r
+ RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz\r
+ RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz\r
+ TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz\r
+ TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz\r
+ RX_CDR_LOL_OUT : out std_logic := '0'; -- CLOCK_DATA RECOVERY LOSS_OF_LOCK !PL14082014\r
+\r
+ --Sync operation\r
+ RX_DLM : out std_logic := '0';\r
+ RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00";\r
+ TX_DLM : in std_logic := '0';\r
+ TX_DLM_WORD : in std_logic_vector(7 downto 0) := x"00";\r
+ TX_DLM_PREVIEW_IN : in std_logic := '0'; --PL!\r
+ LINK_PHASE_OUT : out std_logic := '0'; --PL!\r
+ LINK_READY_OUT : out std_logic := '0'; --PL!\r
+\r
+ --SFP Connection\r
+ SD_RXD_P_IN : in std_logic;\r
+ SD_RXD_N_IN : in std_logic;\r
+ SD_TXD_P_OUT : out std_logic;\r
+ SD_TXD_N_OUT : out std_logic;\r
+ SD_REFCLK_P_IN : in std_logic; --not used\r
+ SD_REFCLK_N_IN : in std_logic; --not used\r
+ SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted)\r
+ SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal)\r
+ SD_TXDIS_OUT : out std_logic := '0'; -- SFP disable\r
+ --Control Interface\r
+ SCI_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0');\r
+ SCI_DATA_OUT : out std_logic_vector(7 downto 0) := (others => '0');\r
+ SCI_ADDR : in std_logic_vector(8 downto 0) := (others => '0');\r
+ SCI_READ : in std_logic := '0';\r
+ SCI_WRITE : in std_logic := '0';\r
+ SCI_ACK : out std_logic := '0';\r
+ SCI_NACK : out std_logic := '0';\r
+ -- Status and control port\r
+ STAT_OP : out std_logic_vector (15 downto 0);\r
+ CTRL_OP : in std_logic_vector (15 downto 0) := (others => '0');\r
+ STAT_DEBUG : out std_logic_vector (63 downto 0);\r
+ CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0')\r
+ );\r
+end entity;\r
+\r
+\r
+architecture med_ecp3_sfp_sync_up_arch of med_ecp3_sfp_sync_up is\r
+\r
+-- Placer Directives\r
+attribute HGROUP : string;\r
+-- for whole architecture\r
+attribute HGROUP of med_ecp3_sfp_sync_up_arch : architecture is "media_uplink_group";\r
+attribute syn_sharing : string;\r
+attribute syn_sharing of med_ecp3_sfp_sync_up_arch : architecture is "off";\r
+\r
+\r
+component DCS\r
+-- synthesis translate_off\r
generic(\r
DSCMODE : string :="POS"\r
-);
--- synthesis translate_on
-port (
-CLK0 :in std_logic ;
-CLK1 :in std_logic ;
-SEL :in std_logic ;
-DCSOUT :out std_logic) ;
-end component;
-
-
-signal clk_200_osc : std_logic;
-signal rx_full_clk : std_logic;
-signal rx_half_clk : std_logic;
-signal tx_full_clk : std_logic;
-signal tx_half_clk : std_logic;
-
-signal tx_data : std_logic_vector(7 downto 0);
-signal tx_k : std_logic;
-signal rx_data : std_logic_vector(7 downto 0);
-signal rx_k : std_logic;
-signal rx_error : std_logic;
-
-signal rst_n : std_logic;
-signal rst : std_logic; -- PL!
-signal rx_serdes_rst : std_logic;
-signal tx_serdes_rst : std_logic;
-signal tx_pcs_rst : std_logic;
-signal rx_pcs_rst : std_logic;
-signal rst_qd : std_logic;
-signal serdes_rst_qd : std_logic;
-signal sd_los_i : std_logic; --PL!
-
-signal rx_los_low : std_logic;
-signal lsm_status : std_logic;
-signal rx_cdr_lol : std_logic;
-signal tx_pll_lol : std_logic;
-
-signal sci_ch_i : std_logic_vector(3 downto 0);
-signal sci_qd_i : std_logic;
-signal sci_reg_i : std_logic;
-signal sci_addr_i : std_logic_vector(8 downto 0);
-signal sci_data_in_i : std_logic_vector(7 downto 0);
-signal sci_data_out_i : std_logic_vector(7 downto 0);
-signal sci_read_i : std_logic;
-signal sci_write_i : std_logic;
-signal sci_write_shift_i : std_logic_vector(2 downto 0);
-signal sci_read_shift_i : std_logic_vector(2 downto 0);
-
--- fix signal names for constraining
-attribute syn_preserve : boolean;
-attribute syn_keep : boolean;
+);\r
+-- synthesis translate_on\r
+port (\r
+CLK0 :in std_logic ;\r
+CLK1 :in std_logic ;\r
+SEL :in std_logic ;\r
+DCSOUT :out std_logic) ;\r
+end component;\r
+\r
+\r
+signal clk_200_osc : std_logic;\r
+signal rx_full_clk : std_logic;\r
+signal rx_half_clk : std_logic;\r
+signal tx_full_clk : std_logic;\r
+signal tx_half_clk : std_logic;\r
+\r
+signal tx_data : std_logic_vector(7 downto 0);\r
+signal tx_k : std_logic;\r
+signal rx_data : std_logic_vector(7 downto 0);\r
+signal rx_k : std_logic;\r
+signal rx_error : std_logic;\r
+\r
+signal rst_n : std_logic;\r
+signal rst : std_logic; -- PL!\r
+signal rx_serdes_rst : std_logic;\r
+signal tx_serdes_rst : std_logic;\r
+signal tx_pcs_rst : std_logic;\r
+signal rx_pcs_rst : std_logic;\r
+signal rst_qd : std_logic;\r
+signal serdes_rst_qd : std_logic;\r
+signal sd_los_i : std_logic; --PL!\r
+\r
+signal rx_los_low : std_logic;\r
+signal lsm_status : std_logic;\r
+signal rx_cdr_lol : std_logic;\r
+signal tx_pll_lol : std_logic;\r
+\r
+signal sci_ch_i : std_logic_vector(3 downto 0);\r
+signal sci_qd_i : std_logic;\r
+signal sci_reg_i : std_logic;\r
+signal sci_addr_i : std_logic_vector(8 downto 0);\r
+signal sci_data_in_i : std_logic_vector(7 downto 0);\r
+signal sci_data_out_i : std_logic_vector(7 downto 0);\r
+signal sci_read_i : std_logic;\r
+signal sci_write_i : std_logic;\r
+signal sci_write_shift_i : std_logic_vector(2 downto 0);\r
+signal sci_read_shift_i : std_logic_vector(2 downto 0);\r
+\r
+-- fix signal names for constraining\r
+attribute syn_preserve : boolean;\r
+attribute syn_keep : boolean;\r
attribute syn_useioff : boolean;\r
\r
-attribute syn_useioff of sd_los_i : signal is false; -- do not use an IOFF for this signal
-\r
-attribute syn_preserve of sci_ch_i : signal is true;
-attribute syn_keep of sci_ch_i : signal is true;
-attribute syn_preserve of sci_qd_i : signal is true;
-attribute syn_keep of sci_qd_i : signal is true;
-attribute syn_preserve of sci_reg_i : signal is true;
-attribute syn_keep of sci_reg_i : signal is true;
-attribute syn_preserve of sci_addr_i : signal is true;
-attribute syn_keep of sci_addr_i : signal is true;
-attribute syn_preserve of sci_data_in_i : signal is true;
-attribute syn_keep of sci_data_in_i : signal is true;
-attribute syn_preserve of sci_data_out_i : signal is true;
-attribute syn_keep of sci_data_out_i : signal is true;
-attribute syn_preserve of sci_read_i : signal is true;
-attribute syn_keep of sci_read_i : signal is true;
-attribute syn_preserve of sci_write_i : signal is true;
-attribute syn_keep of sci_write_i : signal is true;
-attribute syn_preserve of sci_write_shift_i : signal is true;
-attribute syn_keep of sci_write_shift_i : signal is true;
-attribute syn_preserve of sci_read_shift_i : signal is true;
-attribute syn_keep of sci_read_shift_i : signal is true;
-
-signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";
-signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";
-signal tx_allow : std_logic;
-signal rx_allow : std_logic;
-signal tx_allow_q : std_logic;
-signal rx_allow_q : std_logic;
-signal link_phase_S : std_logic; --PL!
-signal request_retr_i : std_logic;
-signal start_retr_i : std_logic;
-signal request_retr_position_i : std_logic_vector(7 downto 0);
-signal start_retr_position_i : std_logic_vector(7 downto 0);
-signal send_link_reset_i : std_logic;
-signal make_link_reset_i : std_logic;
-signal got_link_ready_i : std_logic;
-signal internal_make_link_reset_out : std_logic;
-
-attribute syn_preserve of wa_position : signal is true;
-attribute syn_keep of wa_position : signal is true;
-attribute syn_preserve of wa_position_rx : signal is true;
-attribute syn_keep of wa_position_rx : signal is true;
-
-signal stat_rx_control_i : std_logic_vector(31 downto 0);
-signal stat_tx_control_i : std_logic_vector(31 downto 0);
-signal debug_rx_control_i : std_logic_vector(31 downto 0);
-signal debug_tx_control_i : std_logic_vector(31 downto 0);
-signal rx_fsm_state : std_logic_vector(3 downto 0);
-signal tx_fsm_state : std_logic_vector(3 downto 0);
-signal debug_reg : std_logic_vector(63 downto 0);
-
-type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
-signal sci_state : sci_ctrl;
-signal sci_timer : unsigned(12 downto 0) := (others => '0');
-signal start_timer : unsigned(18 downto 0) := (others => '0');
-signal watchdog_timer : unsigned(20 downto 0) := (others => '0');
-signal watchdog_trigger : std_logic :='0';
-
-begin
-
-clk_200_osc <= OSCCLK;
-
-RX_HALF_CLK_OUT <= rx_half_clk;
-RX_FULL_CLK_OUT <= rx_full_clk;
-TX_HALF_CLK_OUT <= tx_half_clk;
-TX_FULL_CLK_OUT <= tx_full_clk;
-RX_CDR_LOL_OUT <= rx_cdr_lol; -- !PL14082014
-
-SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready
-
-LINK_READY_OUT <= got_link_ready_i when rising_edge(rx_half_clk);
-
-
---rst_n <= not CLEAR; PL!
-rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
-rst <= (CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);
-
-
---gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate
--- clk_200_i <= rx_full_clk;
---end generate;
-
---gen_master_clock : if IS_SYNC_SLAVE = c_NO generate
--- clk_200_i <= clk_200_internal;
---end generate;
-
-
--------------------------------------------------
--- Serdes
--------------------------------------------------
-THE_SERDES : entity work.serdes_sync_upstream
- port map(
- hdinp_ch3 => SD_RXD_P_IN,
- hdinn_ch3 => SD_RXD_N_IN,
- hdoutp_ch3 => SD_TXD_P_OUT,
- hdoutn_ch3 => SD_TXD_N_OUT,
- txiclk_ch3 => rx_full_clk,
- rx_full_clk_ch3 => rx_full_clk,
- rx_half_clk_ch3 => rx_half_clk,
- tx_full_clk_ch3 => tx_full_clk,
- tx_half_clk_ch3 => tx_half_clk,
- fpga_rxrefclk_ch3 => clk_200_osc,
- txdata_ch3 => tx_data,
- tx_k_ch3 => tx_k,
- tx_force_disp_ch3 => '0',
- tx_disp_sel_ch3 => '0',
- rxdata_ch3 => rx_data,
- rx_k_ch3 => rx_k,
- rx_disp_err_ch3 => open,
- rx_cv_err_ch3 => rx_error,
- rx_serdes_rst_ch3_c => rx_serdes_rst,
- sb_felb_ch3_c => '0',
- sb_felb_rst_ch3_c => '0',
- tx_pcs_rst_ch3_c => tx_pcs_rst,
- tx_pwrup_ch3_c => '1',
- rx_pcs_rst_ch3_c => rx_pcs_rst,
- rx_pwrup_ch3_c => '1',
- rx_los_low_ch3_s => rx_los_low,
- lsm_status_ch3_s => lsm_status,
- rx_cdr_lol_ch3_s => rx_cdr_lol,
- tx_div2_mode_ch3_c => '0',
- rx_div2_mode_ch3_c => '0',
-
- SCI_WRDATA => sci_data_in_i,
- SCI_RDDATA => sci_data_out_i,
- SCI_ADDR => sci_addr_i(5 downto 0),
- SCI_SEL_QUAD => sci_qd_i,
- SCI_SEL_ch3 => sci_ch_i(3),
- SCI_RD => sci_read_i,
- SCI_WRN => sci_write_i,
-
- fpga_txrefclk => clk_200_osc, --rx_full_clk,
- tx_serdes_rst_c => tx_serdes_rst,
- tx_pll_lol_qd_s => tx_pll_lol,
- rst_qd_c => rst_qd,
- serdes_rst_qd_c => serdes_rst_qd
-
- );
-
--------------------------------------------------
--- Reset FSM & Link states
--------------------------------------------------
-THE_RX_FSM : rx_reset_fsm
- port map(
- RST_N => rst_n,
- RX_REFCLK => clk_200_osc, -- allways running PL!
- TX_PLL_LOL_QD_S => tx_pll_lol,
- RX_SERDES_RST_CH_C => rx_serdes_rst,
- RX_CDR_LOL_CH_S => rx_cdr_lol,
- RX_LOS_LOW_CH_S => rx_los_low,
- RX_PCS_RST_CH_C => rx_pcs_rst,
- WA_POSITION => wa_position_rx(15 downto 12),
- STATE_OUT => rx_fsm_state
- );
-
-THE_TX_FSM : tx_reset_fsm
- port map(
- RST_N => rst_n,
- TX_REFCLK => clk_200_osc, -- allways running PL! 18-06 was clk_200_i
- TX_PLL_LOL_QD_S => tx_pll_lol,
- RST_QD_C => rst_qd,
- TX_PCS_RST_CH_C => tx_pcs_rst,
- STATE_OUT => tx_fsm_state
- );
-
--- Master does not do bit-locking
-wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000";
-
-
---Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable
-PROC_ALLOW : process begin
- wait until rising_edge(rx_full_clk); --clk_200_osc); --clk_200_i);
- if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
- rx_allow <= '1';
- else
- rx_allow <= '0';
- end if;
- if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then
- tx_allow <= '1';
- else
- tx_allow <= '0';
- end if;
-end process;
-
-rx_allow_q <= rx_allow when rising_edge(rx_half_clk); --SYSCLK);
-tx_allow_q <= tx_allow when rising_edge(rx_half_clk); --SYSCLK);
-
-
-PROC_START_TIMER : process(rx_full_clk) --clk_200_osc) --clk_200_i)
-begin
- if rising_edge(rx_full_clk) then --clk_200_osc) then
- if got_link_ready_i = '1' then
- watchdog_timer <= (others => '0');
- if start_timer(start_timer'left) = '0' then
- start_timer <= start_timer + 1;
- end if;
- else
- start_timer <= (others => '0');
- if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 2) = '1')) then
- watchdog_trigger <= '1';
- else
- watchdog_trigger <= '0';
- end if;
- if watchdog_trigger = '0' then
- watchdog_timer <= watchdog_timer + 1;
- else
- watchdog_timer <= (others => '0');
- end if;
- end if;
- end if;
-end process;
--------------------------------------------------
--- TX Data
--------------------------------------------------
-THE_TX : soda_tx_control
- port map(
- CLK_200 => rx_full_clk, --clk_200_osc, --clk_200_i,
- CLK_100 => rx_half_clk, --SYSCLK,
- RESET_IN => rst, --CLEAR, PL!
-
- TX_DATA_IN => MED_DATA_IN,
- TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN,
- TX_WRITE_IN => MED_DATAREADY_IN,
- TX_READ_OUT => MED_READ_OUT,
-
- TX_DATA_OUT => tx_data,
- TX_K_OUT => tx_k,
-
- REQUEST_RETRANSMIT_IN => request_retr_i, --TODO
- REQUEST_POSITION_IN => request_retr_position_i, --TODO
-
- START_RETRANSMIT_IN => start_retr_i, --TODO
- START_POSITION_IN => request_retr_position_i, --TODO
-
- TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN,
- SEND_DLM => TX_DLM,
- SEND_DLM_WORD => TX_DLM_WORD,
-
- SEND_LINK_RESET_IN => CTRL_OP(15),
- TX_ALLOW_IN => tx_allow,
- RX_ALLOW_IN => rx_allow,
- LINK_PHASE_OUT => link_phase_S, --PL!
-
- DEBUG_OUT => debug_tx_control_i,
- STAT_REG_OUT => stat_tx_control_i
-);
-
-LINK_PHASE_OUT <= link_phase_S; --PL!
--------------------------------------------------
--- RX Data
--------------------------------------------------
-THE_RX_CONTROL : rx_control
- port map(
- CLK_200 => rx_full_clk,
+attribute syn_useioff of sd_los_i : signal is false; -- do not use an IOFF for this signal\r
+\r
+attribute syn_preserve of sci_ch_i : signal is true;\r
+attribute syn_keep of sci_ch_i : signal is true;\r
+attribute syn_preserve of sci_qd_i : signal is true;\r
+attribute syn_keep of sci_qd_i : signal is true;\r
+attribute syn_preserve of sci_reg_i : signal is true;\r
+attribute syn_keep of sci_reg_i : signal is true;\r
+attribute syn_preserve of sci_addr_i : signal is true;\r
+attribute syn_keep of sci_addr_i : signal is true;\r
+attribute syn_preserve of sci_data_in_i : signal is true;\r
+attribute syn_keep of sci_data_in_i : signal is true;\r
+attribute syn_preserve of sci_data_out_i : signal is true;\r
+attribute syn_keep of sci_data_out_i : signal is true;\r
+attribute syn_preserve of sci_read_i : signal is true;\r
+attribute syn_keep of sci_read_i : signal is true;\r
+attribute syn_preserve of sci_write_i : signal is true;\r
+attribute syn_keep of sci_write_i : signal is true;\r
+attribute syn_preserve of sci_write_shift_i : signal is true;\r
+attribute syn_keep of sci_write_shift_i : signal is true;\r
+attribute syn_preserve of sci_read_shift_i : signal is true;\r
+attribute syn_keep of sci_read_shift_i : signal is true;\r
+\r
+signal wa_position : std_logic_vector(15 downto 0) := x"FFFF";\r
+signal wa_position_rx : std_logic_vector(15 downto 0) := x"FFFF";\r
+signal tx_allow : std_logic;\r
+signal rx_allow : std_logic;\r
+signal tx_allow_q : std_logic;\r
+signal rx_allow_q : std_logic;\r
+signal link_phase_S : std_logic; --PL!\r
+signal request_retr_i : std_logic;\r
+signal start_retr_i : std_logic;\r
+signal request_retr_position_i : std_logic_vector(7 downto 0);\r
+signal start_retr_position_i : std_logic_vector(7 downto 0);\r
+signal send_link_reset_i : std_logic;\r
+signal make_link_reset_i : std_logic;\r
+signal got_link_ready_i : std_logic;\r
+signal internal_make_link_reset_out : std_logic;\r
+\r
+attribute syn_preserve of wa_position : signal is true;\r
+attribute syn_keep of wa_position : signal is true;\r
+attribute syn_preserve of wa_position_rx : signal is true;\r
+attribute syn_keep of wa_position_rx : signal is true;\r
+\r
+signal stat_rx_control_i : std_logic_vector(31 downto 0);\r
+signal stat_tx_control_i : std_logic_vector(31 downto 0);\r
+signal debug_rx_control_i : std_logic_vector(31 downto 0);\r
+signal debug_tx_control_i : std_logic_vector(31 downto 0);\r
+signal rx_fsm_state : std_logic_vector(3 downto 0);\r
+signal tx_fsm_state : std_logic_vector(3 downto 0);\r
+signal debug_reg : std_logic_vector(63 downto 0);\r
+\r
+type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);\r
+signal sci_state : sci_ctrl;\r
+signal sci_timer : unsigned(12 downto 0) := (others => '0');\r
+signal start_timer : unsigned(18 downto 0) := (others => '0');\r
+signal watchdog_timer : unsigned(20 downto 0) := (others => '0');\r
+signal watchdog_trigger : std_logic :='0';\r
+\r
+begin\r
+\r
+clk_200_osc <= OSCCLK;\r
+\r
+RX_HALF_CLK_OUT <= rx_half_clk;\r
+RX_FULL_CLK_OUT <= rx_full_clk;\r
+TX_HALF_CLK_OUT <= tx_half_clk;\r
+TX_FULL_CLK_OUT <= tx_full_clk;\r
+RX_CDR_LOL_OUT <= rx_cdr_lol; -- !PL14082014\r
+\r
+SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready\r
+\r
+LINK_READY_OUT <= got_link_ready_i when rising_edge(rx_half_clk);\r
+\r
+\r
+--rst_n <= not CLEAR; PL!\r
+rst_n <= not(CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);\r
+rst <= (CLEAR or sd_los_i or internal_make_link_reset_out or watchdog_trigger);\r
+\r
+\r
+--gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate\r
+-- clk_200_i <= rx_full_clk;\r
+--end generate;\r
+\r
+--gen_master_clock : if IS_SYNC_SLAVE = c_NO generate\r
+-- clk_200_i <= clk_200_internal;\r
+--end generate;\r
+\r
+\r
+------------------------------------------------- \r
+-- Serdes\r
+------------------------------------------------- \r
+THE_SERDES : entity work.serdes_sync_upstream\r
+ port map(\r
+ hdinp_ch3 => SD_RXD_P_IN,\r
+ hdinn_ch3 => SD_RXD_N_IN,\r
+ hdoutp_ch3 => SD_TXD_P_OUT,\r
+ hdoutn_ch3 => SD_TXD_N_OUT,\r
+ txiclk_ch3 => rx_full_clk,\r
+ rx_full_clk_ch3 => rx_full_clk,\r
+ rx_half_clk_ch3 => rx_half_clk,\r
+ tx_full_clk_ch3 => tx_full_clk,\r
+ tx_half_clk_ch3 => tx_half_clk,\r
+ fpga_rxrefclk_ch3 => clk_200_osc,\r
+ txdata_ch3 => tx_data,\r
+ tx_k_ch3 => tx_k,\r
+ tx_force_disp_ch3 => '0',\r
+ tx_disp_sel_ch3 => '0',\r
+ rxdata_ch3 => rx_data,\r
+ rx_k_ch3 => rx_k,\r
+ rx_disp_err_ch3 => open,\r
+ rx_cv_err_ch3 => rx_error,\r
+ rx_serdes_rst_ch3_c => rx_serdes_rst,\r
+ sb_felb_ch3_c => '0',\r
+ sb_felb_rst_ch3_c => '0',\r
+ tx_pcs_rst_ch3_c => tx_pcs_rst,\r
+ tx_pwrup_ch3_c => '1',\r
+ rx_pcs_rst_ch3_c => rx_pcs_rst,\r
+ rx_pwrup_ch3_c => '1',\r
+ rx_los_low_ch3_s => rx_los_low,\r
+ lsm_status_ch3_s => lsm_status,\r
+ rx_cdr_lol_ch3_s => rx_cdr_lol,\r
+ tx_div2_mode_ch3_c => '0',\r
+ rx_div2_mode_ch3_c => '0',\r
+ \r
+ SCI_WRDATA => sci_data_in_i,\r
+ SCI_RDDATA => sci_data_out_i,\r
+ SCI_ADDR => sci_addr_i(5 downto 0),\r
+ SCI_SEL_QUAD => sci_qd_i,\r
+ SCI_SEL_ch3 => sci_ch_i(3),\r
+ SCI_RD => sci_read_i,\r
+ SCI_WRN => sci_write_i,\r
+ \r
+ fpga_txrefclk => rx_full_clk, --clk_200_osc,\r
+ tx_serdes_rst_c => tx_serdes_rst,\r
+ tx_pll_lol_qd_s => tx_pll_lol,\r
+ rst_qd_c => rst_qd,\r
+ serdes_rst_qd_c => serdes_rst_qd\r
+\r
+ );\r
+\r
+------------------------------------------------- \r
+-- Reset FSM & Link states\r
+------------------------------------------------- \r
+THE_RX_FSM : rx_reset_fsm\r
+ port map(\r
+ RST_N => rst_n,\r
+ RX_REFCLK => clk_200_osc, -- allways running PL!\r
+ TX_PLL_LOL_QD_S => tx_pll_lol,\r
+ RX_SERDES_RST_CH_C => rx_serdes_rst,\r
+ RX_CDR_LOL_CH_S => rx_cdr_lol,\r
+ RX_LOS_LOW_CH_S => rx_los_low,\r
+ RX_PCS_RST_CH_C => rx_pcs_rst,\r
+ WA_POSITION => wa_position_rx(15 downto 12),\r
+ STATE_OUT => rx_fsm_state\r
+ );\r
+ \r
+THE_TX_FSM : tx_reset_fsm\r
+ port map(\r
+ RST_N => rst_n,\r
+ TX_REFCLK => clk_200_osc, -- allways running PL! 18-06 was clk_200_i\r
+ TX_PLL_LOL_QD_S => tx_pll_lol,\r
+ RST_QD_C => rst_qd,\r
+ TX_PCS_RST_CH_C => tx_pcs_rst,\r
+ STATE_OUT => tx_fsm_state\r
+ );\r
+\r
+-- Master does not do bit-locking \r
+wa_position_rx <= wa_position when (IS_SYNC_SLAVE = c_YES) else x"0000";\r
+\r
+\r
+--Slave enables RX/TX when sync is done, Master waits additional time to make sure link is stable\r
+PROC_ALLOW : process begin\r
+ wait until rising_edge(rx_full_clk); --clk_200_osc); --clk_200_i);\r
+ if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then\r
+ rx_allow <= '1';\r
+ else\r
+ rx_allow <= '0';\r
+ end if;\r
+ if rx_fsm_state = x"6" and (IS_SYNC_SLAVE = c_YES or start_timer(start_timer'left) = '1') then\r
+ tx_allow <= '1';\r
+ else\r
+ tx_allow <= '0';\r
+ end if;\r
+end process;\r
+\r
+rx_allow_q <= rx_allow when rising_edge(rx_half_clk); --SYSCLK);\r
+tx_allow_q <= tx_allow when rising_edge(rx_half_clk); --SYSCLK);\r
+\r
+\r
+PROC_START_TIMER : process(rx_full_clk) --clk_200_osc) --clk_200_i)\r
+begin\r
+ if rising_edge(rx_full_clk) then --clk_200_osc) then\r
+ if got_link_ready_i = '1' then\r
+ watchdog_timer <= (others => '0');\r
+ if start_timer(start_timer'left) = '0' then\r
+ start_timer <= start_timer + 1;\r
+ end if; \r
+ else\r
+ start_timer <= (others => '0');\r
+ if ((watchdog_timer(watchdog_timer'left) = '1') and (watchdog_timer(watchdog_timer'left - 2) = '1')) then\r
+ watchdog_trigger <= '1';\r
+ else \r
+ watchdog_trigger <= '0';\r
+ end if;\r
+ if watchdog_trigger = '0' then\r
+ watchdog_timer <= watchdog_timer + 1;\r
+ else \r
+ watchdog_timer <= (others => '0');\r
+ end if;\r
+ end if;\r
+ end if;\r
+end process;\r
+------------------------------------------------- \r
+-- TX Data\r
+------------------------------------------------- \r
+THE_TX : soda_tx_control\r
+ port map(\r
+ CLK_200 => rx_full_clk, --clk_200_osc, --clk_200_i,\r
+ CLK_100 => rx_half_clk, --SYSCLK,\r
+ RESET_IN => rst, --CLEAR, PL!\r
+\r
+ TX_DATA_IN => MED_DATA_IN,\r
+ TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN,\r
+ TX_WRITE_IN => MED_DATAREADY_IN,\r
+ TX_READ_OUT => MED_READ_OUT,\r
+\r
+ TX_DATA_OUT => tx_data,\r
+ TX_K_OUT => tx_k,\r
+\r
+ REQUEST_RETRANSMIT_IN => request_retr_i, --TODO\r
+ REQUEST_POSITION_IN => request_retr_position_i, --TODO\r
+\r
+ START_RETRANSMIT_IN => start_retr_i, --TODO\r
+ START_POSITION_IN => request_retr_position_i, --TODO\r
+\r
+ TX_DLM_PREVIEW_IN => TX_DLM_PREVIEW_IN,\r
+ SEND_DLM => TX_DLM,\r
+ SEND_DLM_WORD => TX_DLM_WORD,\r
+\r
+ SEND_LINK_RESET_IN => CTRL_OP(15),\r
+ TX_ALLOW_IN => tx_allow,\r
+ RX_ALLOW_IN => rx_allow,\r
+ LINK_PHASE_OUT => link_phase_S, --PL!\r
+\r
+ DEBUG_OUT => debug_tx_control_i,\r
+ STAT_REG_OUT => stat_tx_control_i\r
+); \r
+\r
+LINK_PHASE_OUT <= link_phase_S; --PL!\r
+------------------------------------------------- \r
+-- RX Data\r
+------------------------------------------------- \r
+THE_RX_CONTROL : rx_control\r
+ port map(\r
+ CLK_200 => rx_full_clk,\r
CLK_100 => rx_half_clk,\r
- RESET_IN => rst,
-
- RX_DATA_OUT => MED_DATA_OUT,
- RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT,
- RX_WRITE_OUT => MED_DATAREADY_OUT,
- RX_READ_IN => MED_READ_IN,
-
- RX_DATA_IN => rx_data,
- RX_K_IN => rx_k,
-
- REQUEST_RETRANSMIT_OUT => request_retr_i,
- REQUEST_POSITION_OUT => request_retr_position_i,
-
- START_RETRANSMIT_OUT => start_retr_i,
- START_POSITION_OUT => start_retr_position_i,
-
- --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM
- RX_DLM => RX_DLM,
- RX_DLM_WORD => RX_DLM_WORD,
-
- SEND_LINK_RESET_OUT => send_link_reset_i,
- MAKE_RESET_OUT => make_link_reset_i,
- RX_ALLOW_IN => rx_allow,
- GOT_LINK_READY => got_link_ready_i,
-
- DEBUG_OUT => debug_rx_control_i,
- STAT_REG_OUT => stat_rx_control_i
- );
-
-
-
--------------------------------------------------
--- SCI
--------------------------------------------------
---gives access to serdes config port from slow control and reads word alignment every ~ 40 us
-PROC_SCI_CTRL: process
- variable cnt : integer range 0 to 4 := 0;
-begin
- wait until rising_edge(rx_half_clk); --SYSCLK);
- SCI_ACK <= '0';
- case sci_state is
- when IDLE =>
- sci_ch_i <= x"0";
- sci_qd_i <= '0';
- sci_reg_i <= '0';
- sci_read_i <= '0';
- sci_write_i <= '0';
- sci_timer <= sci_timer + 1;
- if SCI_READ = '1' or SCI_WRITE = '1' then
- sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);
- sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);
- sci_addr_i <= SCI_ADDR;
- sci_data_in_i <= SCI_DATA_IN;
- sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));
- sci_state <= SCTRL;
- elsif sci_timer(sci_timer'left) = '1' then
- sci_timer <= (others => '0');
- sci_state <= GET_WA;
- end if;
- when SCTRL =>
- if sci_reg_i = '1' then
- SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
- else
- sci_state <= SCTRL_WAIT;
- end if;
- when SCTRL_WAIT =>
- sci_state <= SCTRL_WAIT2;
- when SCTRL_WAIT2 =>
- sci_state <= SCTRL_FINISH;
- when SCTRL_FINISH =>
- SCI_DATA_OUT <= sci_data_out_i;
- SCI_ACK <= '1';
- sci_write_i <= '0';
- sci_read_i <= '0';
- sci_state <= IDLE;
-
- when GET_WA =>
- if cnt = 4 then
- cnt := 0;
- sci_state <= IDLE;
- else
- sci_state <= GET_WA_WAIT;
- sci_addr_i <= '0' & x"22";
- sci_ch_i <= x"0";
- sci_ch_i(cnt) <= '1';
- sci_read_i <= '1';
- end if;
- when GET_WA_WAIT =>
- sci_state <= GET_WA_WAIT2;
- when GET_WA_WAIT2 =>
- sci_state <= GET_WA_FINISH;
- when GET_WA_FINISH =>
- wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);
- sci_state <= GET_WA;
- cnt := cnt + 1;
- end case;
-
- if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then
- SCI_NACK <= '1';
- else
- SCI_NACK <= '0';
- end if;
-
-end process;
-
-
--------------------------------------------------
--- Debug Registers
--------------------------------------------------
-debug_reg(3 downto 0) <= rx_fsm_state;
-debug_reg(4) <= rx_k;
-debug_reg(5) <= rx_error;
-debug_reg(6) <= rx_los_low;
-debug_reg(7) <= rx_cdr_lol;
-
-debug_reg(8) <= tx_k;
-debug_reg(9) <= tx_pll_lol;
-debug_reg(10) <= lsm_status;
-debug_reg(11) <= make_link_reset_i;
-debug_reg(15 downto 12) <= tx_fsm_state;
--- debug_reg(31 downto 24) <= tx_data;
-
-debug_reg(16) <= '0';
-debug_reg(17) <= tx_allow;
-debug_reg(18) <= RESET;
-debug_reg(19) <= CLEAR;
-debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);
-
-debug_reg(35 downto 32) <= wa_position(3 downto 0);
-debug_reg(36) <= debug_tx_control_i(6);
-debug_reg(39 downto 37) <= "000";
-debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);
-
-
-STAT_DEBUG <= debug_reg;
-
-internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0';
-sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL!
-
-STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK);
-STAT_OP(14) <= '0';
-STAT_OP(13) <= internal_make_link_reset_out when rising_edge(SYSCLK); --make trbnet reset
-STAT_OP(12) <= tx_pll_lol; --'0';
-STAT_OP(11) <= rx_cdr_lol; --'0';
-STAT_OP(10) <= rx_allow;
-STAT_OP(9) <= tx_allow;
---STAT_OP(8 downto 4) <= (others => '0');
-STAT_OP(8) <= got_link_ready_i when rising_edge(rx_half_clk);
-STAT_OP(7) <= send_link_reset_i;
-STAT_OP(6) <= make_link_reset_i;
-STAT_OP(5) <= request_retr_i;
-STAT_OP(4) <= start_retr_i;
-STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";
+ RESET_IN => rst,\r
+\r
+ RX_DATA_OUT => MED_DATA_OUT,\r
+ RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT,\r
+ RX_WRITE_OUT => MED_DATAREADY_OUT,\r
+ RX_READ_IN => MED_READ_IN,\r
+\r
+ RX_DATA_IN => rx_data,\r
+ RX_K_IN => rx_k,\r
+\r
+ REQUEST_RETRANSMIT_OUT => request_retr_i,\r
+ REQUEST_POSITION_OUT => request_retr_position_i,\r
+\r
+ START_RETRANSMIT_OUT => start_retr_i,\r
+ START_POSITION_OUT => start_retr_position_i,\r
+\r
+ --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM\r
+ RX_DLM => RX_DLM,\r
+ RX_DLM_WORD => RX_DLM_WORD,\r
+ \r
+ SEND_LINK_RESET_OUT => send_link_reset_i,\r
+ MAKE_RESET_OUT => make_link_reset_i,\r
+ RX_ALLOW_IN => rx_allow,\r
+ GOT_LINK_READY => got_link_ready_i,\r
+\r
+ DEBUG_OUT => debug_rx_control_i,\r
+ STAT_REG_OUT => stat_rx_control_i\r
+ ); \r
+ \r
+ \r
+ \r
+------------------------------------------------- \r
+-- SCI\r
+------------------------------------------------- \r
+--gives access to serdes config port from slow control and reads word alignment every ~ 40 us\r
+PROC_SCI_CTRL: process \r
+ variable cnt : integer range 0 to 4 := 0;\r
+begin\r
+ wait until rising_edge(rx_half_clk); --SYSCLK);\r
+ SCI_ACK <= '0';\r
+ case sci_state is\r
+ when IDLE =>\r
+ sci_ch_i <= x"0";\r
+ sci_qd_i <= '0';\r
+ sci_reg_i <= '0';\r
+ sci_read_i <= '0';\r
+ sci_write_i <= '0';\r
+ sci_timer <= sci_timer + 1;\r
+ if SCI_READ = '1' or SCI_WRITE = '1' then\r
+ sci_ch_i(0) <= not SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);\r
+ sci_ch_i(1) <= SCI_ADDR(6) and not SCI_ADDR(7) and not SCI_ADDR(8);\r
+ sci_ch_i(2) <= not SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);\r
+ sci_ch_i(3) <= SCI_ADDR(6) and SCI_ADDR(7) and not SCI_ADDR(8);\r
+ sci_qd_i <= not SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);\r
+ sci_reg_i <= SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8);\r
+ sci_addr_i <= SCI_ADDR;\r
+ sci_data_in_i <= SCI_DATA_IN;\r
+ sci_read_i <= SCI_READ and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));\r
+ sci_write_i <= SCI_WRITE and not (SCI_ADDR(6) and not SCI_ADDR(7) and SCI_ADDR(8));\r
+ sci_state <= SCTRL;\r
+ elsif sci_timer(sci_timer'left) = '1' then\r
+ sci_timer <= (others => '0');\r
+ sci_state <= GET_WA;\r
+ end if; \r
+ when SCTRL =>\r
+ if sci_reg_i = '1' then\r
+ SCI_DATA_OUT <= debug_reg(8*(to_integer(unsigned(SCI_ADDR(3 downto 0))))+7 downto 8*(to_integer(unsigned(SCI_ADDR(3 downto 0)))));\r
+ SCI_ACK <= '1';\r
+ sci_write_i <= '0';\r
+ sci_read_i <= '0';\r
+ sci_state <= IDLE;\r
+ else\r
+ sci_state <= SCTRL_WAIT;\r
+ end if;\r
+ when SCTRL_WAIT =>\r
+ sci_state <= SCTRL_WAIT2;\r
+ when SCTRL_WAIT2 =>\r
+ sci_state <= SCTRL_FINISH;\r
+ when SCTRL_FINISH =>\r
+ SCI_DATA_OUT <= sci_data_out_i;\r
+ SCI_ACK <= '1';\r
+ sci_write_i <= '0';\r
+ sci_read_i <= '0';\r
+ sci_state <= IDLE;\r
+ \r
+ when GET_WA =>\r
+ if cnt = 4 then\r
+ cnt := 0;\r
+ sci_state <= IDLE;\r
+ else\r
+ sci_state <= GET_WA_WAIT;\r
+ sci_addr_i <= '0' & x"22";\r
+ sci_ch_i <= x"0";\r
+ sci_ch_i(cnt) <= '1';\r
+ sci_read_i <= '1';\r
+ end if;\r
+ when GET_WA_WAIT =>\r
+ sci_state <= GET_WA_WAIT2;\r
+ when GET_WA_WAIT2 =>\r
+ sci_state <= GET_WA_FINISH;\r
+ when GET_WA_FINISH =>\r
+ wa_position(cnt*4+3 downto cnt*4) <= sci_data_out_i(3 downto 0);\r
+ sci_state <= GET_WA; \r
+ cnt := cnt + 1;\r
+ end case;\r
+ \r
+ if (SCI_READ = '1' or SCI_WRITE = '1') and sci_state /= IDLE then\r
+ SCI_NACK <= '1';\r
+ else\r
+ SCI_NACK <= '0';\r
+ end if;\r
+ \r
+end process;\r
+\r
+\r
+------------------------------------------------- \r
+-- Debug Registers\r
+------------------------------------------------- \r
+debug_reg(3 downto 0) <= rx_fsm_state;\r
+debug_reg(4) <= rx_k;\r
+debug_reg(5) <= rx_error;\r
+debug_reg(6) <= rx_los_low;\r
+debug_reg(7) <= rx_cdr_lol;\r
+\r
+debug_reg(8) <= tx_k;\r
+debug_reg(9) <= tx_pll_lol;\r
+debug_reg(10) <= lsm_status;\r
+debug_reg(11) <= make_link_reset_i;\r
+debug_reg(15 downto 12) <= tx_fsm_state;\r
+-- debug_reg(31 downto 24) <= tx_data; \r
+\r
+debug_reg(16) <= '0';\r
+debug_reg(17) <= tx_allow;\r
+debug_reg(18) <= RESET;\r
+debug_reg(19) <= CLEAR;\r
+debug_reg(31 downto 20) <= debug_rx_control_i(4) & debug_rx_control_i(2 downto 0) & debug_rx_control_i(15 downto 8);\r
+\r
+debug_reg(35 downto 32) <= wa_position(3 downto 0);\r
+debug_reg(36) <= debug_tx_control_i(6);\r
+debug_reg(39 downto 37) <= "000";\r
+debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0);\r
+\r
+ \r
+STAT_DEBUG <= debug_reg;\r
+\r
+internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = c_YES else '0';\r
+sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); -- PL!\r
+\r
+STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK);\r
+STAT_OP(14) <= '0';\r
+STAT_OP(13) <= internal_make_link_reset_out when rising_edge(SYSCLK); --make trbnet reset\r
+STAT_OP(12) <= tx_pll_lol; --'0';\r
+STAT_OP(11) <= rx_cdr_lol; --'0';\r
+STAT_OP(10) <= rx_allow;\r
+STAT_OP(9) <= tx_allow;\r
+--STAT_OP(8 downto 4) <= (others => '0');\r
+STAT_OP(8) <= got_link_ready_i when rising_edge(rx_half_clk);\r
+STAT_OP(7) <= send_link_reset_i;\r
+STAT_OP(6) <= make_link_reset_i;\r
+STAT_OP(5) <= request_retr_i;\r
+STAT_OP(4) <= start_retr_i;\r
+STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7";\r
end med_ecp3_sfp_sync_up_arch;
\ No newline at end of file
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.trb_net_std.all;
-use work.trb_net_components.all;
-use work.trb_net16_hub_func.all;
-use work.trb3_components.all;
-use work.soda_components.all;
-use work.med_sync_define.all;
-use work.version.all;
-
-entity trb3_periph_sodasource is
- generic(
- SYNC_MODE : integer range 0 to 1 := c_NO; --use the RX clock for internal logic and transmission. Should be NO for soda tests!
- USE_125_MHZ : integer := c_NO;
- CLOCK_FREQUENCY : integer := 100;
- NUM_INTERFACES : integer := 2
- );
- port(
- --Clocks
- CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz
- CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA
- CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
- CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!
-
- --serdes I/O - connect as you like, no real use
- SERDES_ADDON_TX : out std_logic_vector(15 downto 0);
- SERDES_ADDON_RX : in std_logic_vector(15 downto 0);
-
- --Inter-FPGA Communication
- FPGA5_COMM : inout std_logic_vector(11 downto 0);
- --Bit 0/1 input, serial link RX active
- --Bit 2/3 output, serial link TX active
- --others yet undefined
- --Connection to AddOn
- LED_LINKOK : out std_logic_vector(6 downto 1);
- LED_RX : out std_logic_vector(6 downto 1);
- LED_TX : out std_logic_vector(6 downto 1);
- SFP_MOD0 : in std_logic_vector(6 downto 1);
- SFP_TXDIS : out std_logic_vector(6 downto 1);
- SFP_LOS : in std_logic_vector(6 downto 1);
- --Flash ROM & Reboot
- FLASH_CLK : out std_logic;
- FLASH_CS : out std_logic;
- FLASH_DIN : out std_logic;
- FLASH_DOUT : in std_logic;
- PROGRAMN : out std_logic; --reboot FPGA
-
- --Misc
- TEMPSENS : inout std_logic; --Temperature Sensor
- CODE_LINE : in std_logic_vector(1 downto 0);
- LED_GREEN : out std_logic;
- LED_ORANGE : out std_logic;
- LED_RED : out std_logic;
- LED_YELLOW : out std_logic;
- SUPPL : in std_logic; --terminated diff pair, PCLK, Pads
-
- --Test Connectors
- TEST_LINE : out std_logic_vector(15 downto 0)
- );
-
-
- attribute syn_useioff : boolean;
- --no IO-FF for LEDs relaxes timing constraints
- attribute syn_useioff of LED_GREEN : signal is false;
- attribute syn_useioff of LED_ORANGE : signal is false;
- attribute syn_useioff of LED_RED : signal is false;
- attribute syn_useioff of LED_YELLOW : signal is false;
- attribute syn_useioff of TEMPSENS : signal is false;
- attribute syn_useioff of PROGRAMN : signal is false;
- attribute syn_useioff of CODE_LINE : signal is false;
- attribute syn_useioff of LED_LINKOK : signal is false;
- attribute syn_useioff of LED_TX : signal is false;
- attribute syn_useioff of LED_RX : signal is false;
- attribute syn_useioff of SFP_MOD0 : signal is false;
- attribute syn_useioff of SFP_TXDIS : signal is false;
- attribute syn_useioff of SFP_LOS : signal is false;
- attribute syn_useioff of TEST_LINE : signal is false;
-
- --important signals _with_ IO-FF
- attribute syn_useioff of FLASH_CLK : signal is true;
- attribute syn_useioff of FLASH_CS : signal is true;
- attribute syn_useioff of FLASH_DIN : signal is true;
- attribute syn_useioff of FLASH_DOUT : signal is true;
- attribute syn_useioff of FPGA5_COMM : signal is true;
-
-
-end entity;
-
-architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is
- --Constants
- constant REGIO_NUM_STAT_REGS : integer := 0;
- constant REGIO_NUM_CTRL_REGS : integer := 2;
-
- attribute syn_keep : boolean;
- attribute syn_preserve : boolean;
-
- constant USE_200_MHZ : integer := 1 - USE_125_MHZ;
-
- --Clock / Reset
- -- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL
- -- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL
- signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.
- signal clear_i : std_logic;
- signal reset_i : std_logic;
- signal GSR_N : std_logic;
- attribute syn_keep of GSR_N : signal is true;
- attribute syn_preserve of GSR_N : signal is true;
- signal clk_100_osc : std_logic;
- signal clk_200_osc : std_logic;
--- signal rx_clock_half : std_logic;
--- signal rx_clock_full : std_logic;
--- signal clk_tdc : std_logic;
- signal time_counter : unsigned(31 downto 0);
- --Media Interface
- signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);
- signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0);
- signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);
- signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
- signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);
-
- --Slow Control channel
- signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);
- signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
- signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);
- signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);
- signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);
- signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);
- signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);
-
- --RegIO
- signal my_address : std_logic_vector (15 downto 0);
- signal regio_addr_out : std_logic_vector (15 downto 0);
- signal regio_read_enable_out : std_logic;
- signal regio_write_enable_out : std_logic;
- signal regio_data_out : std_logic_vector (31 downto 0);
- signal regio_data_in : std_logic_vector (31 downto 0);
- signal regio_dataready_in : std_logic;
- signal regio_no_more_data_in : std_logic;
- signal regio_write_ack_in : std_logic;
- signal regio_unknown_addr_in : std_logic;
- signal regio_timeout_out : std_logic;
-
- --Timer
- signal global_time : std_logic_vector(31 downto 0);
- signal local_time : std_logic_vector(7 downto 0);
- signal time_since_last_trg : std_logic_vector(31 downto 0);
- signal timer_ticks : std_logic_vector(1 downto 0);
-
- --Flash
- signal spimem_read_en : std_logic;
- signal spimem_write_en : std_logic;
- signal spimem_data_in : std_logic_vector(31 downto 0);
- signal spimem_addr : std_logic_vector(8 downto 0);
- signal spimem_data_out : std_logic_vector(31 downto 0);
- signal spimem_dataready_out : std_logic;
- signal spimem_no_more_data_out : std_logic;
- signal spimem_unknown_addr_out : std_logic;
- signal spimem_write_ack_out : std_logic;
-
- signal sci1_ack : std_logic;
- signal sci1_write : std_logic;
- signal sci1_read : std_logic;
- signal sci1_data_in : std_logic_vector(7 downto 0);
- signal sci1_data_out : std_logic_vector(7 downto 0);
- signal sci1_addr : std_logic_vector(8 downto 0);
- signal sci2_ack : std_logic;
- signal sci2_nack : std_logic;
- signal sci2_write : std_logic;
- signal sci2_read : std_logic;
- signal sci2_data_in : std_logic_vector(7 downto 0);
- signal sci2_data_out : std_logic_vector(7 downto 0);
- signal sci2_addr : std_logic_vector(8 downto 0);
- signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1');
-
- --SODA
- signal soda_ack : std_logic;
- signal soda_write : std_logic;
- signal soda_read : std_logic;
- signal soda_data_in : std_logic_vector(31 downto 0);
- signal soda_data_out : std_logic_vector(31 downto 0);
- signal soda_addr : std_logic_vector(3 downto 0);
- signal soda_leds : std_logic_vector(3 downto 0);
-
-
- --TDC
- signal hit_in_i : std_logic_vector(63 downto 0);
-
- signal soda_rx_clock_half : std_logic;
- signal soda_rx_clock_full : std_logic;
- signal soda_tx_clock_half : std_logic;
- signal soda_tx_clock_full : std_logic;
- signal tx_dlm_i : std_logic;
- signal rx_dlm_i : std_logic;
- signal tx_dlm_word : std_logic_vector(7 downto 0);
- signal rx_dlm_word : std_logic_vector(7 downto 0);
- signal tx_dlm_preview_S : std_logic; --PL!
- signal link_phase_S : std_logic; --PL!
-
- --SODA
- signal SOB_S : std_logic := '0';
- signal soda_40mhz_cycle_S : std_logic := '0';
- -- fix signal names for constraining
- attribute syn_preserve of soda_rx_clock_full : signal is true;
- attribute syn_keep of soda_rx_clock_full : signal is true;
- attribute syn_preserve of soda_rx_clock_half : signal is true;
- attribute syn_keep of soda_rx_clock_half : signal is true;
- attribute syn_preserve of soda_tx_clock_full : signal is true;
- attribute syn_keep of soda_tx_clock_full : signal is true;
- attribute syn_preserve of soda_tx_clock_half : signal is true;
- attribute syn_keep of soda_tx_clock_half : signal is true;
- attribute syn_preserve of clk_100_osc : signal is true;
- attribute syn_keep of clk_100_osc : signal is true;
- attribute syn_preserve of clk_200_osc : signal is true;
- attribute syn_keep of clk_200_osc : signal is true;
- attribute syn_preserve of tx_dlm_i : signal is true;
- attribute syn_keep of tx_dlm_i : signal is true;
- attribute syn_preserve of rx_dlm_i : signal is true;
- attribute syn_keep of rx_dlm_i : signal is true;
- attribute syn_preserve of soda_40mhz_cycle_S : signal is true;
- attribute syn_keep of soda_40mhz_cycle_S : signal is true;
-
-
-begin
----------------------------------------------------------------------------
--- Reset Generation
----------------------------------------------------------------------------
-
- GSR_N <= pll_lock;
-
- THE_RESET_HANDLER : trb_net_reset_handler
- generic map(
- RESET_DELAY => x"FEEE"
- )
- port map(
- CLEAR_IN => '0', -- reset input (high active, async)
- CLEAR_N_IN => '1', -- reset input (low active, async)
- CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL!
- SYSCLK_IN => clk_100_osc, -- PLL/DLL remastered clock
- PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)
- RESET_IN => '0', -- general reset signal (SYSCLK)
- TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)
- CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!
- RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)
- DEBUG_OUT => open
- );
-
-
----------------------------------------------------------------------------
--- Clock Handling
----------------------------------------------------------------------------
-gen_200_PLL : if USE_125_MHZ = c_NO generate
- THE_MAIN_PLL : pll_in200_out100
- port map(
- CLK => CLK_GPLL_RIGHT,
- CLKOP => clk_100_osc,
- CLKOK => clk_200_osc,
- LOCK => pll_lock
- );
-end generate;
-
----------------------------------------------------------------------------
--- The TrbNet media interface (to other FPGA)
----------------------------------------------------------------------------
- THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp
- generic map(
- SERDES_NUM => 1, --number of serdes in quad
- EXT_CLOCK => c_NO, --use internal clock
- USE_200_MHZ => USE_200_MHZ, --run on 200 MHz clock
- USE_125_MHZ => USE_125_MHZ,
- USE_CTC => c_NO,
- USE_SLAVE => SYNC_MODE
- )
- port map(
- CLK => clk_200_osc,
- SYSCLK => clk_100_osc,
- RESET => reset_i,
- CLEAR => clear_i,
- CLK_EN => '1',
- --Internal Connection
- MED_DATA_IN => med_data_out(15 downto 0),
- MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),
- MED_DATAREADY_IN => med_dataready_out(0),
- MED_READ_OUT => med_read_in(0),
- MED_DATA_OUT => med_data_in(15 downto 0),
- MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),
- MED_DATAREADY_OUT => med_dataready_in(0),
- MED_READ_IN => med_read_out(0),
- REFCLK2CORE_OUT => open,
- CLK_RX_HALF_OUT => open, --rx_clock_half,
- CLK_RX_FULL_OUT => open, --rx_clock_full,
-
- --SFP Connection
- SD_RXD_P_IN => SERDES_ADDON_RX(2),
- SD_RXD_N_IN => SERDES_ADDON_RX(3),
- SD_TXD_P_OUT => SERDES_ADDON_TX(2),
- SD_TXD_N_OUT => SERDES_ADDON_TX(3),
- SD_REFCLK_P_IN => '0',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => FPGA5_COMM(0),
- SD_LOS_IN => FPGA5_COMM(0),
- SD_TXDIS_OUT => FPGA5_COMM(2),
-
- SCI_DATA_IN => sci1_data_in,
- SCI_DATA_OUT => sci1_data_out,
- SCI_ADDR => sci1_addr,
- SCI_READ => sci1_read,
- SCI_WRITE => sci1_write,
- SCI_ACK => sci1_ack,
- -- Status and control port
- STAT_OP => med_stat_op(15 downto 0),
- CTRL_OP => med_ctrl_op(15 downto 0),
- STAT_DEBUG => med_stat_debug(63 downto 0),
- CTRL_DEBUG => (others => '0')
- );
-
-
----------------------------------------------------------------------------
--- Hub
----------------------------------------------------------------------------
-
-THE_HUB : trb_net16_hub_base
- generic map (
- HUB_USED_CHANNELS => (c_NO,c_NO,c_NO,c_YES),
- IBUF_SECURE_MODE => c_YES,
- MII_NUMBER => NUM_INTERFACES,
- MII_IS_UPLINK => (0 => 1, others => 0),
- MII_IS_DOWNLINK => (0 => 0, others => 1),
- MII_IS_UPLINK_ONLY=> (0 => 1, others => 0),
- INT_NUMBER => 0,
- USE_ONEWIRE => c_YES,
- COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),
--- COMPILE_TIME => VERSION_NUMBER_TIME,
- HARDWARE_VERSION => x"91003200",
- INIT_ENDPOINT_ID => x"0000",
- INIT_ADDRESS => x"F355",
- USE_VAR_ENDPOINT_ID => c_YES,
- BROADCAST_SPECIAL_ADDR => x"45",
- CLOCK_FREQUENCY => CLOCK_FREQUENCY
- )
- port map (
- CLK => clk_100_osc, --clk_sys_i, PL! 30062014
- RESET => reset_i,
- CLK_EN => '1',
-
- --Media interfacces
- MED_DATAREADY_OUT(NUM_INTERFACES*1-1 downto 0) => med_dataready_out,
- MED_DATA_OUT(NUM_INTERFACES*16-1 downto 0) => med_data_out,
- MED_PACKET_NUM_OUT(NUM_INTERFACES*3-1 downto 0) => med_packet_num_out,
- MED_READ_IN(NUM_INTERFACES*1-1 downto 0) => med_read_in,
- MED_DATAREADY_IN(NUM_INTERFACES*1-1 downto 0) => med_dataready_in,
- MED_DATA_IN(NUM_INTERFACES*16-1 downto 0) => med_data_in,
- MED_PACKET_NUM_IN(NUM_INTERFACES*3-1 downto 0) => med_packet_num_in,
- MED_READ_OUT(NUM_INTERFACES*1-1 downto 0) => med_read_out,
- MED_STAT_OP(NUM_INTERFACES*16-1 downto 0) => med_stat_op,
- MED_CTRL_OP(NUM_INTERFACES*16-1 downto 0) => med_ctrl_op,
-
- COMMON_STAT_REGS => common_stat_reg,
- COMMON_CTRL_REGS => common_ctrl_reg,
- MY_ADDRESS_OUT => open,
- --REGIO INTERFACE
- REGIO_ADDR_OUT => regio_addr_out,
- REGIO_READ_ENABLE_OUT => regio_read_enable_out,
- REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,
- REGIO_DATA_OUT => regio_data_out,
- REGIO_DATA_IN => regio_data_in,
- REGIO_DATAREADY_IN => regio_dataready_in,
- REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,
- REGIO_WRITE_ACK_IN => regio_write_ack_in,
- REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,
- REGIO_TIMEOUT_OUT => regio_timeout_out,
- REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,
- REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),
- ONEWIRE => TEMPSENS,
- ONEWIRE_MONITOR_OUT => open,
- --Status ports (for debugging)
- MPLEX_CTRL => (others => '0'),
- CTRL_DEBUG => (others => '0'),
- STAT_DEBUG => open
- );
-
-
-
----------------------------------------------------------------------------
--- Bus Handler
----------------------------------------------------------------------------
- THE_BUS_HANDLER : trb_net16_regio_bus_handler
- generic map(
- PORT_NUMBER => 4,
- PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),
- PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0)
- )
- port map(
- CLK => clk_100_osc,
- RESET => reset_i,
-
- DAT_ADDR_IN => regio_addr_out,
- DAT_DATA_IN => regio_data_out,
- DAT_DATA_OUT => regio_data_in,
- DAT_READ_ENABLE_IN => regio_read_enable_out,
- DAT_WRITE_ENABLE_IN => regio_write_enable_out,
- DAT_TIMEOUT_IN => regio_timeout_out,
- DAT_DATAREADY_OUT => regio_dataready_in,
- DAT_WRITE_ACK_OUT => regio_write_ack_in,
- DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,
- DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,
-
- BUS_READ_ENABLE_OUT(0) => spimem_read_en,
- BUS_READ_ENABLE_OUT(1) => sci1_read,
- BUS_READ_ENABLE_OUT(2) => sci2_read,
- BUS_READ_ENABLE_OUT(3) => soda_read,
-
- BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,
- BUS_WRITE_ENABLE_OUT(1) => sci1_write,
- BUS_WRITE_ENABLE_OUT(2) => sci2_write,
- BUS_WRITE_ENABLE_OUT(3) => soda_write,
-
- BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,
- BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,
- BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,
- BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in,
- BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,
- BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in,
-
- BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,
- BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,
- BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,
- BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,
- BUS_ADDR_OUT(2*16+8 downto 2*16) => sci2_addr,
- BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,
- BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr,
- BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,
-
- BUS_TIMEOUT_OUT(0) => open,
- BUS_TIMEOUT_OUT(1) => open,
- BUS_TIMEOUT_OUT(2) => open,
- BUS_TIMEOUT_OUT(3) => open,
-
- BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,
- BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,
- BUS_DATA_IN(1*32+31 downto 1*32+8) => (others => '0'),
- BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out,
- BUS_DATA_IN(2*32+31 downto 2*32+8) => (others => '0'),
- BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out,
-
- BUS_DATAREADY_IN(0) => spimem_dataready_out,
- BUS_DATAREADY_IN(1) => sci1_ack,
- BUS_DATAREADY_IN(2) => sci2_ack,
- BUS_DATAREADY_IN(3) => soda_ack,
-
- BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,
- BUS_WRITE_ACK_IN(1) => sci1_ack,
- BUS_WRITE_ACK_IN(2) => sci2_ack,
- BUS_WRITE_ACK_IN(3) => soda_ack,
-
- BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,
- BUS_NO_MORE_DATA_IN(1) => '0',
- BUS_NO_MORE_DATA_IN(2) => '0',
- BUS_NO_MORE_DATA_IN(3) => '0',
-
- BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,
- BUS_UNKNOWN_ADDR_IN(1) => '0',
- BUS_UNKNOWN_ADDR_IN(2) => sci2_nack,
- BUS_UNKNOWN_ADDR_IN(3) => '0',
-
- STAT_DEBUG => open
- );
-
----------------------------------------------------------------------------
--- SPI / Flash
----------------------------------------------------------------------------
-
-THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch
- port map(
- CLK_IN => clk_100_osc,
- RESET_IN => reset_i,
-
- BUS_ADDR_IN => spimem_addr,
- BUS_READ_IN => spimem_read_en,
- BUS_WRITE_IN => spimem_write_en,
- BUS_DATAREADY_OUT => spimem_dataready_out,
- BUS_WRITE_ACK_OUT => spimem_write_ack_out,
- BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,
- BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,
- BUS_DATA_IN => spimem_data_in,
- BUS_DATA_OUT => spimem_data_out,
-
- DO_REBOOT_IN => common_ctrl_reg(15),
- PROGRAMN => PROGRAMN,
-
- SPI_CS_OUT => FLASH_CS,
- SPI_SCK_OUT => FLASH_CLK,
- SPI_SDO_OUT => FLASH_DIN,
- SPI_SDI_IN => FLASH_DOUT
- );
-
-
----------------------------------------------------------------------------
--- The synchronous interface for Soda tests
----------------------------------------------------------------------------
-
-THE_SYNC_LINK : med_ecp3_sfp_sync_down
- generic map(
- SERDES_NUM => 0, --number of serdes in quad
- IS_SYNC_SLAVE => c_NO
- )
- port map(
- OSCCLK => clk_200_osc,
- SYSCLK => clk_100_osc,
- RESET => reset_i,
- CLEAR => clear_i,
- --Internal Connection for TrbNet data -> not used a.t.m.
- MED_DATA_IN => med_data_out(31 downto 16),
- MED_PACKET_NUM_IN => med_packet_num_out(5 downto 3),
- MED_DATAREADY_IN => med_dataready_out(1),
- MED_READ_OUT => med_read_in(1),
- MED_DATA_OUT => med_data_in(31 downto 16),
- MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3),
- MED_DATAREADY_OUT => med_dataready_in(1),
- MED_READ_IN => med_read_out(1),
- RX_HALF_CLK_OUT => soda_rx_clock_half,
- RX_FULL_CLK_OUT => soda_rx_clock_full,
- TX_HALF_CLK_OUT => soda_tx_clock_half,
- TX_FULL_CLK_OUT => soda_tx_clock_full,
-
- RX_DLM => rx_dlm_i,
- RX_DLM_WORD => rx_dlm_word,
- TX_DLM => tx_dlm_i,
- TX_DLM_WORD => tx_dlm_word,
- TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL!
- LINK_PHASE_OUT => link_phase_S, --PL!
- --SFP Connection
- SD_RXD_P_IN => SERDES_ADDON_RX(0),
- SD_RXD_N_IN => SERDES_ADDON_RX(1),
- SD_TXD_P_OUT => SERDES_ADDON_TX(0),
- SD_TXD_N_OUT => SERDES_ADDON_TX(1),
- SD_REFCLK_P_IN => '0',
- SD_REFCLK_N_IN => '0',
- SD_PRSNT_N_IN => SFP_MOD0(1),
- SD_LOS_IN => SFP_LOS(1),
- SD_TXDIS_OUT => sfp_txdis_S(1), --SFP_TXDIS(1),
-
- SCI_DATA_IN => sci2_data_in,
- SCI_DATA_OUT => sci2_data_out,
- SCI_ADDR => sci2_addr,
- SCI_READ => sci2_read,
- SCI_WRITE => sci2_write,
- SCI_ACK => sci2_ack,
- SCI_NACK => sci2_nack,
- -- Status and control port
- STAT_OP => med_stat_op(31 downto 16),
- CTRL_OP => med_ctrl_op(31 downto 16),
- STAT_DEBUG => open,
- CTRL_DEBUG => (others => '0')
- );
-
- SFP_TXDIS(1) <= sfp_txdis_S(1);
-
----------------------------------------------------------------------------
--- Burst- and 40MHz cycle generator
----------------------------------------------------------------------------
-
-THE_SOB_SOURCE : soda_start_of_burst_control
- generic map(
- CLOCK_PERIOD => cSODA_CLOCK_PERIOD, -- clock-period in ns
- CYCLE_PERIOD => cSODA_CYCLE_PERIOD, -- cycle-period in ns
- BURST_PERIOD => cBURST_PERIOD -- burst-period in ns
- )
- port map(
- SODA_CLK => clk_200_osc,
- RESET => reset_i,
- SODA_BURST_PULSE_OUT => SOB_S,
- SODA_40MHZ_CYCLE_OUT => soda_40mhz_cycle_S
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+use work.trb_net_components.all;\r
+use work.trb_net16_hub_func.all;\r
+use work.trb3_components.all; \r
+use work.soda_components.all;\r
+use work.med_sync_define.all;\r
+use work.version.all;\r
+\r
+entity trb3_periph_sodasource is\r
+ generic(\r
+ SYNC_MODE : integer range 0 to 1 := c_NO; --use the RX clock for internal logic and transmission. Should be NO for soda tests!\r
+ USE_125_MHZ : integer := c_NO;\r
+ CLOCK_FREQUENCY : integer := 100;\r
+ NUM_INTERFACES : integer := 2\r
+ );\r
+ port(\r
+ --Clocks \r
+ CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz\r
+ CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA\r
+ CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!\r
+ CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right!\r
+\r
+ --serdes I/O - connect as you like, no real use\r
+ SERDES_ADDON_TX : out std_logic_vector(15 downto 0);\r
+ SERDES_ADDON_RX : in std_logic_vector(15 downto 0);\r
+\r
+ --Inter-FPGA Communication\r
+ FPGA5_COMM : inout std_logic_vector(11 downto 0);\r
+ --Bit 0/1 input, serial link RX active\r
+ --Bit 2/3 output, serial link TX active\r
+ --others yet undefined\r
+ --Connection to AddOn\r
+ LED_LINKOK : out std_logic_vector(6 downto 1);\r
+ LED_RX : out std_logic_vector(6 downto 1); \r
+ LED_TX : out std_logic_vector(6 downto 1);\r
+ SFP_MOD0 : in std_logic_vector(6 downto 1);\r
+ SFP_TXDIS : out std_logic_vector(6 downto 1); \r
+ SFP_LOS : in std_logic_vector(6 downto 1);\r
+ --Flash ROM & Reboot \r
+ FLASH_CLK : out std_logic;\r
+ FLASH_CS : out std_logic;\r
+ FLASH_DIN : out std_logic;\r
+ FLASH_DOUT : in std_logic;\r
+ PROGRAMN : out std_logic; --reboot FPGA\r
+\r
+ --Misc\r
+ TEMPSENS : inout std_logic; --Temperature Sensor\r
+ CODE_LINE : in std_logic_vector(1 downto 0);\r
+ LED_GREEN : out std_logic;\r
+ LED_ORANGE : out std_logic;\r
+ LED_RED : out std_logic;\r
+ LED_YELLOW : out std_logic;\r
+ SUPPL : in std_logic; --terminated diff pair, PCLK, Pads\r
+\r
+ --Test Connectors\r
+ TEST_LINE : out std_logic_vector(15 downto 0)\r
+ );\r
+\r
+\r
+ attribute syn_useioff : boolean;\r
+ --no IO-FF for LEDs relaxes timing constraints\r
+ attribute syn_useioff of LED_GREEN : signal is false;\r
+ attribute syn_useioff of LED_ORANGE : signal is false;\r
+ attribute syn_useioff of LED_RED : signal is false;\r
+ attribute syn_useioff of LED_YELLOW : signal is false;\r
+ attribute syn_useioff of TEMPSENS : signal is false;\r
+ attribute syn_useioff of PROGRAMN : signal is false;\r
+ attribute syn_useioff of CODE_LINE : signal is false;\r
+ attribute syn_useioff of LED_LINKOK : signal is false;\r
+ attribute syn_useioff of LED_TX : signal is false;\r
+ attribute syn_useioff of LED_RX : signal is false;\r
+ attribute syn_useioff of SFP_MOD0 : signal is false;\r
+ attribute syn_useioff of SFP_TXDIS : signal is false;\r
+ attribute syn_useioff of SFP_LOS : signal is false;\r
+ attribute syn_useioff of TEST_LINE : signal is false;\r
+\r
+ --important signals _with_ IO-FF\r
+ attribute syn_useioff of FLASH_CLK : signal is true;\r
+ attribute syn_useioff of FLASH_CS : signal is true;\r
+ attribute syn_useioff of FLASH_DIN : signal is true;\r
+ attribute syn_useioff of FLASH_DOUT : signal is true;\r
+ attribute syn_useioff of FPGA5_COMM : signal is true;\r
+\r
+\r
+end entity;\r
+\r
+architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is\r
+ --Constants\r
+ constant REGIO_NUM_STAT_REGS : integer := 0;\r
+ constant REGIO_NUM_CTRL_REGS : integer := 2;\r
+\r
+ attribute syn_keep : boolean;\r
+ attribute syn_preserve : boolean;\r
+\r
+ constant USE_200_MHZ : integer := 1 - USE_125_MHZ;\r
+\r
+ --Clock / Reset\r
+ -- signal clk_sys_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL\r
+ -- signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL\r
+ signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic.\r
+ signal clear_i : std_logic;\r
+ signal reset_i : std_logic;\r
+ signal GSR_N : std_logic;\r
+ attribute syn_keep of GSR_N : signal is true;\r
+ attribute syn_preserve of GSR_N : signal is true;\r
+ signal clk_100_osc : std_logic;\r
+ signal clk_200_osc : std_logic;\r
+-- signal rx_clock_half : std_logic;\r
+-- signal rx_clock_full : std_logic;\r
+-- signal clk_tdc : std_logic;\r
+ --Media Interface\r
+ signal med_stat_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);\r
+ signal med_ctrl_op : std_logic_vector (NUM_INTERFACES*16-1 downto 0);\r
+ signal med_stat_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);\r
+ signal med_ctrl_debug : std_logic_vector (NUM_INTERFACES*64-1 downto 0);\r
+ signal med_data_out : std_logic_vector (NUM_INTERFACES*16-1 downto 0);\r
+ signal med_packet_num_out : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);\r
+ signal med_dataready_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);\r
+ signal med_read_out : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);\r
+ signal med_data_in : std_logic_vector (NUM_INTERFACES*16-1 downto 0);\r
+ signal med_packet_num_in : std_logic_vector (NUM_INTERFACES* 3-1 downto 0);\r
+ signal med_dataready_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);\r
+ signal med_read_in : std_logic_vector (NUM_INTERFACES* 1-1 downto 0);\r
+\r
+ --Slow Control channel\r
+ signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0);\r
+ signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0);\r
+ signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0);\r
+ signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0);\r
+ signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0);\r
+ signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0);\r
+ signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0);\r
+ signal ctrl_reg_strobe : std_logic_vector(2**REGIO_NUM_CTRL_REGS-1 downto 0);\r
+\r
+ --RegIO\r
+ signal my_address : std_logic_vector (15 downto 0);\r
+ signal regio_addr_out : std_logic_vector (15 downto 0);\r
+ signal regio_read_enable_out : std_logic;\r
+ signal regio_write_enable_out : std_logic;\r
+ signal regio_data_out : std_logic_vector (31 downto 0);\r
+ signal regio_data_in : std_logic_vector (31 downto 0);\r
+ signal regio_dataready_in : std_logic;\r
+ signal regio_no_more_data_in : std_logic;\r
+ signal regio_write_ack_in : std_logic;\r
+ signal regio_unknown_addr_in : std_logic;\r
+ signal regio_timeout_out : std_logic;\r
+\r
+ --Timer\r
+ signal global_time : std_logic_vector(31 downto 0);\r
+ signal local_time : std_logic_vector(7 downto 0);\r
+ signal time_since_last_trg : std_logic_vector(31 downto 0);\r
+ signal timer_ticks : std_logic_vector(1 downto 0);\r
+\r
+ --Flash\r
+ signal spimem_read_en : std_logic;\r
+ signal spimem_write_en : std_logic;\r
+ signal spimem_data_in : std_logic_vector(31 downto 0);\r
+ signal spimem_addr : std_logic_vector(8 downto 0);\r
+ signal spimem_data_out : std_logic_vector(31 downto 0);\r
+ signal spimem_dataready_out : std_logic;\r
+ signal spimem_no_more_data_out : std_logic;\r
+ signal spimem_unknown_addr_out : std_logic;\r
+ signal spimem_write_ack_out : std_logic;\r
+\r
+ signal sci1_ack : std_logic;\r
+ signal sci1_write : std_logic;\r
+ signal sci1_read : std_logic;\r
+ signal sci1_data_in : std_logic_vector(7 downto 0);\r
+ signal sci1_data_out : std_logic_vector(7 downto 0);\r
+ signal sci1_addr : std_logic_vector(8 downto 0); \r
+ signal sci2_ack : std_logic;\r
+ signal sci2_nack : std_logic;\r
+ signal sci2_write : std_logic;\r
+ signal sci2_read : std_logic;\r
+ signal sci2_data_in : std_logic_vector(7 downto 0);\r
+ signal sci2_data_out : std_logic_vector(7 downto 0);\r
+ signal sci2_addr : std_logic_vector(8 downto 0); \r
+ signal sfp_txdis_S : std_logic_vector(6 downto 1) := (others => '1'); \r
+\r
+ --SODA\r
+ signal soda_ack : std_logic;\r
+ signal soda_write : std_logic;\r
+ signal soda_read : std_logic;\r
+ signal soda_data_in : std_logic_vector(31 downto 0);\r
+ signal soda_data_out : std_logic_vector(31 downto 0);\r
+ signal soda_addr : std_logic_vector(3 downto 0); \r
+ signal soda_leds : std_logic_vector(3 downto 0); \r
+\r
+\r
+ --TDC\r
+ signal hit_in_i : std_logic_vector(63 downto 0);\r
+ \r
+ signal soda_rx_clock_half : std_logic;\r
+ signal soda_rx_clock_full : std_logic;\r
+ signal soda_tx_clock_half : std_logic;\r
+ signal soda_tx_clock_full : std_logic;\r
+ signal tx_dlm_i : std_logic;\r
+ signal rx_dlm_i : std_logic;\r
+ signal tx_dlm_word : std_logic_vector(7 downto 0);\r
+ signal rx_dlm_word : std_logic_vector(7 downto 0);\r
+ signal tx_dlm_preview_S : std_logic; --PL!\r
+ signal link_phase_S : std_logic; --PL!\r
+\r
+ --SODA\r
+ signal SOB_S : std_logic := '0';\r
+ signal soda_40mhz_cycle_S : std_logic := '0';\r
+ -- fix signal names for constraining\r
+ attribute syn_preserve of soda_rx_clock_full : signal is true;\r
+ attribute syn_keep of soda_rx_clock_full : signal is true;\r
+ attribute syn_preserve of soda_rx_clock_half : signal is true;\r
+ attribute syn_keep of soda_rx_clock_half : signal is true;\r
+ attribute syn_preserve of soda_tx_clock_full : signal is true;\r
+ attribute syn_keep of soda_tx_clock_full : signal is true;\r
+ attribute syn_preserve of soda_tx_clock_half : signal is true;\r
+ attribute syn_keep of soda_tx_clock_half : signal is true;\r
+ attribute syn_preserve of clk_100_osc : signal is true;\r
+ attribute syn_keep of clk_100_osc : signal is true;\r
+ attribute syn_preserve of clk_200_osc : signal is true;\r
+ attribute syn_keep of clk_200_osc : signal is true;\r
+ attribute syn_preserve of tx_dlm_i : signal is true;\r
+ attribute syn_keep of tx_dlm_i : signal is true;\r
+ attribute syn_preserve of rx_dlm_i : signal is true;\r
+ attribute syn_keep of rx_dlm_i : signal is true;\r
+ attribute syn_preserve of soda_40mhz_cycle_S : signal is true;\r
+ attribute syn_keep of soda_40mhz_cycle_S : signal is true;\r
+\r
+ \r
+begin\r
+---------------------------------------------------------------------------\r
+-- Reset Generation\r
+---------------------------------------------------------------------------\r
+\r
+ GSR_N <= pll_lock;\r
+\r
+ THE_RESET_HANDLER : trb_net_reset_handler\r
+ generic map(\r
+ RESET_DELAY => x"FEEE"\r
+ )\r
+ port map(\r
+ CLEAR_IN => '0', -- reset input (high active, async)\r
+ CLEAR_N_IN => '1', -- reset input (low active, async)\r
+ CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL!\r
+ SYSCLK_IN => clk_100_osc, -- PLL/DLL remastered clock\r
+ PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async)\r
+ RESET_IN => '0', -- general reset signal (SYSCLK)\r
+ TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK)\r
+ CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE!\r
+ RESET_OUT => reset_i, -- synchronous reset out (SYSCLK)\r
+ DEBUG_OUT => open\r
+ );\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Clock Handling\r
+---------------------------------------------------------------------------\r
+gen_200_PLL : if USE_125_MHZ = c_NO generate\r
+ THE_MAIN_PLL : pll_in200_out100\r
+ port map(\r
+ CLK => CLK_GPLL_RIGHT,\r
+ RESET => '0',\r
+ CLKOP => clk_100_osc,\r
+ CLKOK => clk_200_osc,\r
+ LOCK => pll_lock\r
+ );\r
+end generate; \r
+\r
+---------------------------------------------------------------------------\r
+-- The TrbNet media interface (to other FPGA)\r
+---------------------------------------------------------------------------\r
+ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp\r
+ generic map(\r
+ SERDES_NUM => 1, --number of serdes in quad\r
+ EXT_CLOCK => c_NO, --use internal clock\r
+ USE_200_MHZ => USE_200_MHZ, --run on 200 MHz clock\r
+ USE_125_MHZ => USE_125_MHZ,\r
+ USE_CTC => c_NO,\r
+ USE_SLAVE => SYNC_MODE\r
+ ) \r
+ port map(\r
+ CLK => clk_200_osc,\r
+ SYSCLK => clk_100_osc,\r
+ RESET => reset_i,\r
+ CLEAR => clear_i,\r
+ CLK_EN => '1',\r
+ --Internal Connection\r
+ MED_DATA_IN => med_data_out(15 downto 0),\r
+ MED_PACKET_NUM_IN => med_packet_num_out(2 downto 0),\r
+ MED_DATAREADY_IN => med_dataready_out(0),\r
+ MED_READ_OUT => med_read_in(0),\r
+ MED_DATA_OUT => med_data_in(15 downto 0),\r
+ MED_PACKET_NUM_OUT => med_packet_num_in(2 downto 0),\r
+ MED_DATAREADY_OUT => med_dataready_in(0),\r
+ MED_READ_IN => med_read_out(0),\r
+ REFCLK2CORE_OUT => open,\r
+ CLK_RX_HALF_OUT => open, --rx_clock_half,\r
+ CLK_RX_FULL_OUT => open, --rx_clock_full,\r
+ \r
+ --SFP Connection\r
+ SD_RXD_P_IN => SERDES_ADDON_RX(2),\r
+ SD_RXD_N_IN => SERDES_ADDON_RX(3),\r
+ SD_TXD_P_OUT => SERDES_ADDON_TX(2),\r
+ SD_TXD_N_OUT => SERDES_ADDON_TX(3),\r
+ SD_REFCLK_P_IN => '0',\r
+ SD_REFCLK_N_IN => '0',\r
+ SD_PRSNT_N_IN => FPGA5_COMM(0),\r
+ SD_LOS_IN => FPGA5_COMM(0),\r
+ SD_TXDIS_OUT => FPGA5_COMM(2),\r
+ \r
+ SCI_DATA_IN => sci1_data_in,\r
+ SCI_DATA_OUT => sci1_data_out,\r
+ SCI_ADDR => sci1_addr,\r
+ SCI_READ => sci1_read,\r
+ SCI_WRITE => sci1_write,\r
+ SCI_ACK => sci1_ack, \r
+ -- Status and control port\r
+ STAT_OP => med_stat_op(15 downto 0),\r
+ CTRL_OP => med_ctrl_op(15 downto 0),\r
+ STAT_DEBUG => open, --med_stat_debug(63 downto 0),\r
+ CTRL_DEBUG => (others => '0')\r
+ );\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Hub \r
+---------------------------------------------------------------------------\r
+\r
+THE_HUB : trb_net16_hub_base\r
+ generic map (\r
+ HUB_USED_CHANNELS => (c_NO,c_NO,c_NO,c_YES),\r
+ IBUF_SECURE_MODE => c_YES,\r
+ MII_NUMBER => NUM_INTERFACES,\r
+ MII_IS_UPLINK => (0 => 1, others => 0),\r
+ MII_IS_DOWNLINK => (0 => 0, others => 1),\r
+ MII_IS_UPLINK_ONLY=> (0 => 1, others => 0),\r
+ INT_NUMBER => 0,\r
+ USE_ONEWIRE => c_YES,\r
+ COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)),\r
+-- COMPILE_TIME => VERSION_NUMBER_TIME, \r
+ HARDWARE_VERSION => x"91003200",\r
+ INIT_ENDPOINT_ID => x"0000",\r
+ INIT_ADDRESS => x"F355",\r
+ USE_VAR_ENDPOINT_ID => c_YES,\r
+ BROADCAST_SPECIAL_ADDR => x"45",\r
+ CLOCK_FREQUENCY => CLOCK_FREQUENCY\r
+ )\r
+ port map (\r
+ CLK => clk_100_osc, --clk_sys_i, PL! 30062014\r
+ RESET => reset_i,\r
+ CLK_EN => '1',\r
+\r
+ --Media interfacces\r
+ MED_DATAREADY_OUT(NUM_INTERFACES*1-1 downto 0) => med_dataready_out,\r
+ MED_DATA_OUT(NUM_INTERFACES*16-1 downto 0) => med_data_out,\r
+ MED_PACKET_NUM_OUT(NUM_INTERFACES*3-1 downto 0) => med_packet_num_out,\r
+ MED_READ_IN(NUM_INTERFACES*1-1 downto 0) => med_read_in,\r
+ MED_DATAREADY_IN(NUM_INTERFACES*1-1 downto 0) => med_dataready_in,\r
+ MED_DATA_IN(NUM_INTERFACES*16-1 downto 0) => med_data_in,\r
+ MED_PACKET_NUM_IN(NUM_INTERFACES*3-1 downto 0) => med_packet_num_in,\r
+ MED_READ_OUT(NUM_INTERFACES*1-1 downto 0) => med_read_out,\r
+ MED_STAT_OP(NUM_INTERFACES*16-1 downto 0) => med_stat_op,\r
+ MED_CTRL_OP(NUM_INTERFACES*16-1 downto 0) => med_ctrl_op,\r
+\r
+ COMMON_STAT_REGS => common_stat_reg,\r
+ COMMON_CTRL_REGS => common_ctrl_reg,\r
+ MY_ADDRESS_OUT => open,\r
+ --REGIO INTERFACE\r
+ REGIO_ADDR_OUT => regio_addr_out,\r
+ REGIO_READ_ENABLE_OUT => regio_read_enable_out,\r
+ REGIO_WRITE_ENABLE_OUT => regio_write_enable_out,\r
+ REGIO_DATA_OUT => regio_data_out,\r
+ REGIO_DATA_IN => regio_data_in,\r
+ REGIO_DATAREADY_IN => regio_dataready_in,\r
+ REGIO_NO_MORE_DATA_IN => regio_no_more_data_in,\r
+ REGIO_WRITE_ACK_IN => regio_write_ack_in,\r
+ REGIO_UNKNOWN_ADDR_IN => regio_unknown_addr_in,\r
+ REGIO_TIMEOUT_OUT => regio_timeout_out,\r
+ REGIO_VAR_ENDPOINT_ID(1 downto 0) => CODE_LINE,\r
+ REGIO_VAR_ENDPOINT_ID(15 downto 2) => (others => '0'),\r
+ ONEWIRE => TEMPSENS,\r
+ ONEWIRE_MONITOR_OUT => open,\r
+ --Status ports (for debugging)\r
+ MPLEX_CTRL => (others => '0'),\r
+ CTRL_DEBUG => (others => '0'),\r
+ STAT_DEBUG => open\r
+ );\r
+\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Bus Handler\r
+---------------------------------------------------------------------------\r
+ THE_BUS_HANDLER : trb_net16_regio_bus_handler\r
+ generic map(\r
+ PORT_NUMBER => 4,\r
+ PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"b800", 3 => x"be00", others => x"0000"),\r
+ PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0)\r
+ )\r
+ port map(\r
+ CLK => clk_100_osc,\r
+ RESET => reset_i,\r
+\r
+ DAT_ADDR_IN => regio_addr_out,\r
+ DAT_DATA_IN => regio_data_out,\r
+ DAT_DATA_OUT => regio_data_in,\r
+ DAT_READ_ENABLE_IN => regio_read_enable_out,\r
+ DAT_WRITE_ENABLE_IN => regio_write_enable_out,\r
+ DAT_TIMEOUT_IN => regio_timeout_out,\r
+ DAT_DATAREADY_OUT => regio_dataready_in,\r
+ DAT_WRITE_ACK_OUT => regio_write_ack_in,\r
+ DAT_NO_MORE_DATA_OUT => regio_no_more_data_in,\r
+ DAT_UNKNOWN_ADDR_OUT => regio_unknown_addr_in,\r
+\r
+ BUS_READ_ENABLE_OUT(0) => spimem_read_en,\r
+ BUS_READ_ENABLE_OUT(1) => sci1_read,\r
+ BUS_READ_ENABLE_OUT(2) => sci2_read,\r
+ BUS_READ_ENABLE_OUT(3) => soda_read,\r
+\r
+ BUS_WRITE_ENABLE_OUT(0) => spimem_write_en,\r
+ BUS_WRITE_ENABLE_OUT(1) => sci1_write,\r
+ BUS_WRITE_ENABLE_OUT(2) => sci2_write,\r
+ BUS_WRITE_ENABLE_OUT(3) => soda_write,\r
+ \r
+ BUS_DATA_OUT(0*32+31 downto 0*32) => spimem_data_in,\r
+ BUS_DATA_OUT(1*32+7 downto 1*32) => sci1_data_in,\r
+ BUS_DATA_OUT(1*32+31 downto 1*32+8) => open,\r
+ BUS_DATA_OUT(2*32+7 downto 2*32) => sci2_data_in,\r
+ BUS_DATA_OUT(2*32+31 downto 2*32+8) => open,\r
+ BUS_DATA_OUT(3*32+31 downto 3*32) => soda_data_in,\r
+ \r
+ BUS_ADDR_OUT(0*16+8 downto 0*16) => spimem_addr,\r
+ BUS_ADDR_OUT(0*16+15 downto 0*16+9) => open,\r
+ BUS_ADDR_OUT(1*16+8 downto 1*16) => sci1_addr,\r
+ BUS_ADDR_OUT(1*16+15 downto 1*16+9) => open,\r
+ BUS_ADDR_OUT(2*16+8 downto 2*16) => sci2_addr,\r
+ BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open,\r
+ BUS_ADDR_OUT(3*16+3 downto 3*16) => soda_addr,\r
+ BUS_ADDR_OUT(3*16+15 downto 3*16+4) => open,\r
+ \r
+ BUS_TIMEOUT_OUT(0) => open,\r
+ BUS_TIMEOUT_OUT(1) => open,\r
+ BUS_TIMEOUT_OUT(2) => open,\r
+ BUS_TIMEOUT_OUT(3) => open,\r
+ \r
+ BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out,\r
+ BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out,\r
+ BUS_DATA_IN(1*32+31 downto 1*32+8) => (others => '0'),\r
+ BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out,\r
+ BUS_DATA_IN(2*32+31 downto 2*32+8) => (others => '0'),\r
+ BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out,\r
+ \r
+ BUS_DATAREADY_IN(0) => spimem_dataready_out,\r
+ BUS_DATAREADY_IN(1) => sci1_ack,\r
+ BUS_DATAREADY_IN(2) => sci2_ack,\r
+ BUS_DATAREADY_IN(3) => soda_ack,\r
+ \r
+ BUS_WRITE_ACK_IN(0) => spimem_write_ack_out,\r
+ BUS_WRITE_ACK_IN(1) => sci1_ack,\r
+ BUS_WRITE_ACK_IN(2) => sci2_ack,\r
+ BUS_WRITE_ACK_IN(3) => soda_ack,\r
+ \r
+ BUS_NO_MORE_DATA_IN(0) => spimem_no_more_data_out,\r
+ BUS_NO_MORE_DATA_IN(1) => '0',\r
+ BUS_NO_MORE_DATA_IN(2) => '0',\r
+ BUS_NO_MORE_DATA_IN(3) => '0',\r
+ \r
+ BUS_UNKNOWN_ADDR_IN(0) => spimem_unknown_addr_out,\r
+ BUS_UNKNOWN_ADDR_IN(1) => '0',\r
+ BUS_UNKNOWN_ADDR_IN(2) => sci2_nack,\r
+ BUS_UNKNOWN_ADDR_IN(3) => '0',\r
+\r
+ STAT_DEBUG => open\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- SPI / Flash\r
+---------------------------------------------------------------------------\r
+\r
+THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch\r
+ port map(\r
+ CLK_IN => clk_100_osc,\r
+ RESET_IN => reset_i,\r
+ \r
+ BUS_ADDR_IN => spimem_addr,\r
+ BUS_READ_IN => spimem_read_en,\r
+ BUS_WRITE_IN => spimem_write_en,\r
+ BUS_DATAREADY_OUT => spimem_dataready_out,\r
+ BUS_WRITE_ACK_OUT => spimem_write_ack_out,\r
+ BUS_UNKNOWN_ADDR_OUT => spimem_unknown_addr_out,\r
+ BUS_NO_MORE_DATA_OUT => spimem_no_more_data_out,\r
+ BUS_DATA_IN => spimem_data_in,\r
+ BUS_DATA_OUT => spimem_data_out,\r
+ \r
+ DO_REBOOT_IN => common_ctrl_reg(15), \r
+ PROGRAMN => PROGRAMN,\r
+ \r
+ SPI_CS_OUT => FLASH_CS,\r
+ SPI_SCK_OUT => FLASH_CLK,\r
+ SPI_SDO_OUT => FLASH_DIN,\r
+ SPI_SDI_IN => FLASH_DOUT\r
+ );\r
+\r
+ \r
+---------------------------------------------------------------------------\r
+-- The synchronous interface for Soda tests\r
+--------------------------------------------------------------------------- \r
+\r
+THE_SYNC_LINK : med_ecp3_sfp_sync_down\r
+ generic map(\r
+ SERDES_NUM => 0, --number of serdes in quad\r
+ IS_SYNC_SLAVE => c_NO\r
+ )\r
+ port map(\r
+ OSCCLK => clk_200_osc,\r
+ SYSCLK => clk_100_osc,\r
+ RESET => reset_i,\r
+ CLEAR => clear_i,\r
+ --Internal Connection for TrbNet data -> not used a.t.m.\r
+ MED_DATA_IN => med_data_out(31 downto 16),\r
+ MED_PACKET_NUM_IN => med_packet_num_out(5 downto 3),\r
+ MED_DATAREADY_IN => med_dataready_out(1),\r
+ MED_READ_OUT => med_read_in(1),\r
+ MED_DATA_OUT => med_data_in(31 downto 16),\r
+ MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3),\r
+ MED_DATAREADY_OUT => med_dataready_in(1),\r
+ MED_READ_IN => med_read_out(1),\r
+ RX_HALF_CLK_OUT => soda_rx_clock_half,\r
+ RX_FULL_CLK_OUT => soda_rx_clock_full,\r
+ TX_HALF_CLK_OUT => soda_tx_clock_half,\r
+ TX_FULL_CLK_OUT => soda_tx_clock_full,\r
+\r
+ RX_DLM => rx_dlm_i,\r
+ RX_DLM_WORD => rx_dlm_word,\r
+ TX_DLM => tx_dlm_i,\r
+ TX_DLM_WORD => tx_dlm_word,\r
+ TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL!\r
+ LINK_PHASE_OUT => link_phase_S, --PL!\r
+ --SFP Connection\r
+ SD_RXD_P_IN => SERDES_ADDON_RX(0),\r
+ SD_RXD_N_IN => SERDES_ADDON_RX(1),\r
+ SD_TXD_P_OUT => SERDES_ADDON_TX(0),\r
+ SD_TXD_N_OUT => SERDES_ADDON_TX(1),\r
+ SD_REFCLK_P_IN => '0',\r
+ SD_REFCLK_N_IN => '0',\r
+ SD_PRSNT_N_IN => SFP_MOD0(1),\r
+ SD_LOS_IN => SFP_LOS(1),\r
+ SD_TXDIS_OUT => sfp_txdis_S(1), --SFP_TXDIS(1),\r
+\r
+ SCI_DATA_IN => sci2_data_in,\r
+ SCI_DATA_OUT => sci2_data_out,\r
+ SCI_ADDR => sci2_addr,\r
+ SCI_READ => sci2_read,\r
+ SCI_WRITE => sci2_write,\r
+ SCI_ACK => sci2_ack, \r
+ SCI_NACK => sci2_nack,\r
+ -- Status and control port\r
+ STAT_OP => med_stat_op(31 downto 16),\r
+ CTRL_OP => med_ctrl_op(31 downto 16),\r
+ STAT_DEBUG => med_stat_debug(63 downto 0),\r
+ CTRL_DEBUG => (others => '0')\r
+ ); \r
+\r
+-- THE_SYNC_LINK : med_ecp3_sfp_sync\r
+-- generic map(\r
+-- SERDES_NUM => 0, --number of serdes in quad\r
+-- IS_SYNC_SLAVE => c_NO\r
+-- )\r
+-- port map(\r
+-- CLK => clk_200_osc,\r
+-- SYSCLK => clk_100_osc,\r
+-- RESET => reset_i,\r
+-- CLEAR => clear_i,\r
+-- --Internal Connection for TrbNet data -> not used a.t.m.\r
+-- MED_DATA_IN => med_data_out(31 downto 16),\r
+-- MED_PACKET_NUM_IN => med_packet_num_out(5 downto 3),\r
+-- MED_DATAREADY_IN => med_dataready_out(1),\r
+-- MED_READ_OUT => med_read_in(1),\r
+-- MED_DATA_OUT => med_data_in(31 downto 16),\r
+-- MED_PACKET_NUM_OUT => med_packet_num_in(5 downto 3),\r
+-- MED_DATAREADY_OUT => med_dataready_in(1),\r
+-- MED_READ_IN => med_read_out(1),\r
+-- CLK_RX_HALF_OUT => soda_rx_clock_half,\r
+-- CLK_RX_FULL_OUT => soda_rx_clock_full,\r
+-- -- TX_HALF_CLK_OUT => soda_tx_clock_half,\r
+-- -- TX_FULL_CLK_OUT => soda_tx_clock_full,\r
+-- \r
+-- RX_DLM => rx_dlm_i,\r
+-- RX_DLM_WORD => rx_dlm_word,\r
+-- TX_DLM => tx_dlm_i,\r
+-- TX_DLM_WORD => tx_dlm_word,\r
+-- -- TX_DLM_PREVIEW_IN => tx_dlm_preview_S, --PL!\r
+-- -- LINK_PHASE_OUT => link_phase_S, --PL!\r
+-- --SFP Connection\r
+-- SD_RXD_P_IN => SERDES_ADDON_RX(0),\r
+-- SD_RXD_N_IN => SERDES_ADDON_RX(1),\r
+-- SD_TXD_P_OUT => SERDES_ADDON_TX(0),\r
+-- SD_TXD_N_OUT => SERDES_ADDON_TX(1),\r
+-- SD_REFCLK_P_IN => '0',\r
+-- SD_REFCLK_N_IN => '0',\r
+-- SD_PRSNT_N_IN => SFP_MOD0(1),\r
+-- SD_LOS_IN => SFP_LOS(1),\r
+-- SD_TXDIS_OUT => sfp_txdis_S(1), --SFP_TXDIS(1),\r
+-- \r
+-- SCI_DATA_IN => sci2_data_in,\r
+-- SCI_DATA_OUT => sci2_data_out,\r
+-- SCI_ADDR => sci2_addr,\r
+-- SCI_READ => sci2_read,\r
+-- SCI_WRITE => sci2_write,\r
+-- SCI_ACK => sci2_ack, \r
+-- SCI_NACK => sci2_nack,\r
+-- -- Status and control port\r
+-- STAT_OP => med_stat_op(31 downto 16),\r
+-- CTRL_OP => med_ctrl_op(31 downto 16),\r
+-- STAT_DEBUG => med_stat_debug(63 downto 0),\r
+-- CTRL_DEBUG => (others => '0')\r
+-- ); \r
+ \r
+ SFP_TXDIS(1) <= sfp_txdis_S(1);\r
+\r
+ \r
+---------------------------------------------------------------------------\r
+-- Burst- and 40MHz cycle generator\r
+--------------------------------------------------------------------------- \r
+\r
+THE_SOB_SOURCE : soda_start_of_burst_control\r
+ generic map(\r
+ CLOCK_PERIOD => cSODA_CLOCK_PERIOD, -- clock-period in ns\r
+ CYCLE_PERIOD => cSODA_CYCLE_PERIOD, -- cycle-period in ns\r
+ BURST_PERIOD => cBURST_PERIOD -- burst-period in ns\r
+ )\r
+ port map(\r
+ SODA_CLK => clk_200_osc,\r
+ RESET => reset_i,\r
+ SODA_BURST_PULSE_OUT => SOB_S,\r
+ SODA_40MHZ_CYCLE_OUT => soda_40mhz_cycle_S\r
+ );\r
+\r
+---------------------------------------------------------------------------\r
+-- The Soda Central\r
+--------------------------------------------------------------------------- \r
+ \r
+THE_SODA_SOURCE : soda_source\r
+ port map(\r
+ SYSCLK => soda_tx_clock_half, --clk_100_osc, --clk_sys_i, PL! 30062014\r
+ SODACLK => soda_tx_clock_full, --clk_200_osc, -- PL! 30062014\r
+ RESET => reset_i,\r
+\r
+ SODA_BURST_PULSE_IN => SOB_S,\r
+ SODA_CYCLE_IN => soda_40mhz_cycle_S,\r
+\r
+ RX_DLM_WORD_IN => rx_dlm_word,\r
+ RX_DLM_IN => rx_dlm_i,\r
+ TX_DLM_OUT => tx_dlm_i, \r
+ TX_DLM_WORD_OUT => tx_dlm_word,\r
+ TX_DLM_PREVIEW_OUT => tx_dlm_preview_S,\r
+ LINK_PHASE_IN => link_phase_S,\r
+ SODA_DATA_IN => soda_data_in,\r
+ SODA_DATA_OUT => soda_data_out,\r
+ SODA_ADDR_IN => soda_addr,\r
+ SODA_READ_IN => soda_read,\r
+ SODA_WRITE_IN => soda_write,\r
+ SODA_ACK_OUT => soda_ack,\r
+ LEDS_OUT => soda_leds\r
);\r
\r
----------------------------------------------------------------------------
--- The Soda Central
----------------------------------------------------------------------------
-
-THE_SODA_SOURCE : soda_source
- port map(
- SYSCLK => soda_tx_clock_half, --clk_100_osc, --clk_sys_i, PL! 30062014
- SODACLK => soda_tx_clock_full, --clk_200_osc, -- PL! 30062014
- RESET => reset_i,
-\r
- SODA_BURST_PULSE_IN => SOB_S,
- SODA_CYCLE_IN => soda_40mhz_cycle_S,
-
- RX_DLM_WORD_IN => rx_dlm_word,
- RX_DLM_IN => rx_dlm_i,
- TX_DLM_OUT => tx_dlm_i,
- TX_DLM_WORD_OUT => tx_dlm_word,
- TX_DLM_PREVIEW_OUT => tx_dlm_preview_S,
- LINK_PHASE_IN => link_phase_S,
- SODA_DATA_IN => soda_data_in,
- SODA_DATA_OUT => soda_data_out,
- SODA_ADDR_IN => soda_addr,
- SODA_READ_IN => soda_read,
- SODA_WRITE_IN => soda_write,
- SODA_ACK_OUT => soda_ack,
- LEDS_OUT => soda_leds
- );
-
----------------------------------------------------------------------------
--- LED
----------------------------------------------------------------------------
--- LED_ORANGE <= SFP_LOS(3); --med_stat_op(8);
--- LED_YELLOW <= sfp_txdis_S(3); --med_stat_op(10);
--- LED_GREEN <= med_stat_op(12); --tx_pll_lol
--- LED_RED <= med_stat_op(11); --rx_cdr_lol
- LED_ORANGE <= '1' when (med_stat_op(26)='0') else '0';
- LED_YELLOW <= '1' when (med_stat_op(26)='0') else '0';
- LED_GREEN <= med_stat_op(11);
- LED_RED <= med_stat_op(10);
-
-\r
----------------------------------------------------------------------------
--- GREEN LED under sfp
----------------------------------------------------------------------------
- LED_LINKOK(1) <= SFP_LOS(1); --med_stat_op(8);
- LED_LINKOK(2) <= SFP_LOS(2);
- LED_LINKOK(3) <= SFP_LOS(3);
- LED_LINKOK(4) <= SFP_LOS(4);
- LED_LINKOK(5) <= SFP_LOS(5);
- LED_LINKOK(6) <= SFP_LOS(6);
-
- LED_RX(1) <= '1' when (med_stat_op(10)='0') else '0'; -- rx_allow
- LED_RX(2) <= '1';
- LED_RX(3) <= '1';
- LED_RX(4) <= '1';
- LED_RX(5) <= '1';
- LED_RX(6) <= '1';
-
- LED_TX(1) <= '1' when (med_stat_op(9)='0') else '0'; -- tx_allow
- LED_TX(2) <= '1';
- LED_TX(3) <= '1';
- LED_TX(4) <= '1';
- LED_TX(5) <= '1';
- LED_TX(6) <= '1';
-
----------------------------------------------------------------------------
--- Test Connector
----------------------------------------------------------------------------
--- TEST_LINE(15 downto 0) <= (others => '0');
----------------------------------------------------------------------------
--- Test Circuits
----------------------------------------------------------------------------
-
- blink : process (clk_100_osc)
- begin
- if rising_edge(clk_100_osc) then
- if (time_counter = x"FFFFFFFF") then
- time_counter <= x"00000000";
- else
- time_counter <= time_counter + 1;
- end if;
- end if;
- end process;
-
+---------------------------------------------------------------------------\r
+-- LED\r
+---------------------------------------------------------------------------\r
+-- LED_ORANGE <= SFP_LOS(3); --med_stat_op(8);\r
+-- LED_YELLOW <= sfp_txdis_S(3); --med_stat_op(10);\r
+-- LED_GREEN <= med_stat_op(12); --tx_pll_lol\r
+-- LED_RED <= med_stat_op(11); --rx_cdr_lol\r
+ LED_ORANGE <= '1' when (med_stat_op(26)='0') else '0';\r
+ LED_YELLOW <= '1' when (med_stat_op(26)='0') else '0';\r
+ LED_GREEN <= med_stat_op(11);\r
+ LED_RED <= med_stat_op(10);\r
+ \r
+\r
+---------------------------------------------------------------------------\r
+-- GREEN LED under sfp\r
+--------------------------------------------------------------------------- \r
+ LED_LINKOK(1) <= not med_stat_op(9);\r
+ LED_LINKOK(2) <= SFP_LOS(2);\r
+ LED_LINKOK(3) <= SFP_LOS(3);\r
+ LED_LINKOK(4) <= SFP_LOS(4);\r
+ LED_LINKOK(5) <= SFP_LOS(5);\r
+ LED_LINKOK(6) <= SFP_LOS(6);\r
+\r
+ LED_RX(1) <= not (med_stat_op(11) or med_stat_op(10));\r
+ LED_RX(2) <= '1';\r
+ LED_RX(3) <= '1';\r
+ LED_RX(4) <= '1';\r
+ LED_RX(5) <= '1';\r
+ LED_RX(6) <= '1';\r
+ \r
+ LED_TX(1) <= not med_stat_op(12);\r
+ LED_TX(2) <= '1';\r
+ LED_TX(3) <= '1';\r
+ LED_TX(4) <= '1';\r
+ LED_TX(5) <= '1';\r
+ LED_TX(6) <= '1';\r
+\r
+-- STAT_OP(12) <= led_dlm or last_led_dlm;\r
+-- STAT_OP(11) <= led_tx or last_led_tx;\r
+-- STAT_OP(10) <= led_rx or last_led_rx;\r
+-- STAT_OP(9) <= led_ok; \r
+ \r
+---------------------------------------------------------------------------\r
+-- Test Connector\r
+--------------------------------------------------------------------------- \r
+ TEST_LINE(13 downto 0) <= med_stat_debug(13 downto 0);\r
+ TEST_LINE(14) <= soda_rx_clock_half;\r
+ TEST_LINE(15) <= soda_tx_clock_half;\r
+\r
end trb3_periph_sodasource_arch;
\ No newline at end of file
jspc29 / soda.git / commitdiff