prepare combiner for potential shift to retransmission branch and add improved calibr...

diff --git a/combiner_cts/code_EBR/Cal_Limits_v2_1.vhd b/combiner_cts/code_EBR/Cal_Limits_v2_1.vhd
new file mode 100644 (file)
index 0000000..97b9869
--- /dev/null
+++ b/combiner_cts/code_EBR/Cal_Limits_v2_1.vhd
@@ -0,0 +1,395 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+library work;
+use work.trb_net_std.all;
+
+entity Cal_Limits_v2 is
+  generic (
+    cal_Limit_gen  : unsigned(19 downto 0) := "00000000000100000000";--"00000000000100000000";
+    locBufDepth    : integer := 7;
+    USE_STAT_BITS     : integer range 0 to 1 := c_NO;
+    USE_DATA_WRITE    : integer range 0 to 1 := c_NO;
+    USE_DATA_FINISHED : integer range 0 to 1 := c_NO; 
+    USE_BUSY_RELEASE  : integer range 0 to 1 := c_NO
+  );    
+  port (
+    CLK                : in  std_logic;
+    RESET              : in  std_logic;
+    stop_Limits        : in  std_logic;
+    cal_Limit_reg      : in  unsigned(19 downto 0);
+    DIN                : in  std_logic_vector(31 downto 0);
+    DIN_ready          : in  std_logic;
+    DIN_type           : in  std_logic_vector( 3 downto 0);
+    min_curr_in        : in  std_logic_vector( 9 downto 0);
+    max_curr_in        : in  std_logic_vector( 9 downto 0);
+    min_next_in        : in  std_logic_vector( 9 downto 0);
+    max_next_in        : in  std_logic_vector( 9 downto 0);
+    FPGA               : in  std_logic_vector( 3 downto 0);
+    chnl               : in  std_logic_vector( 6 downto 0);
+    Do_Cal_in          : in  std_logic;
+    chnl_cnt_in        : in  unsigned(19 downto 0);
+    BUS_Flash_value    : in  std_logic_vector(31 downto 0);
+    Flash_flag         : in  std_logic;
+    DIN_info           : in  std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0);
+    write_curr_out     : out std_logic;
+    write_next         : out std_logic;
+    min_next           : out std_logic_vector( 9 downto 0);
+    max_next           : out std_logic_vector( 9 downto 0);
+    min_curr_out       : out std_logic_vector( 9 downto 0);
+    max_curr_out       : out std_logic_vector( 9 downto 0);
+    min_out_out        : out std_logic_vector( 9 downto 0);
+    max_out_out        : out std_logic_vector( 9 downto 0);
+    Delta              : out std_logic_vector( 9 downto 0);
+    FPGA_out           : out std_logic_vector( 3 downto 0);
+    chnl_out           : out std_logic_vector( 6 downto 0);
+    FPGA_out_curr      : out std_logic_vector( 3 downto 0);
+    chnl_out_curr      : out std_logic_vector( 6 downto 0);
+    FPGA_out_write     : out std_logic_vector( 3 downto 0);
+    chnl_out_write     : out std_logic_vector( 6 downto 0);
+    FPGA_out_write_cnt : out std_logic_vector( 3 downto 0);
+    chnl_out_write_cnt : out std_logic_vector( 6 downto 0);
+    DOUT               : out std_logic_vector(31 downto 0);
+    DOUT_ready         : out std_logic;
+    DOUT_type          : out std_logic_vector( 3 downto 0);
+    Do_Cal_out         : out std_logic;
+    chnl_cnt_out       : out unsigned (19 downto 0); --:="00000000000000000000";
+    write_chnl_cnt     : out std_logic;
+    cal_Limit_set      : out unsigned (19 downto 0);
+    Debug_Data_min     : out std_logic_vector(31 downto 0);
+    Debug_Data_max     : out std_logic_vector(31 downto 0);
+    DOUT_info          : out std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0);
+    dflt_out           : out std_logic_vector(3 downto 0);
+    cnt_i_debug        : out unsigned (19 downto 0)
+  );
+end Cal_Limits_v2;
+
+architecture Behavioral of Cal_Limits_v2 is
+
+  signal Delta_i     : std_logic_vector( 9 downto 0) := "0110110100"; 
+  signal cnt_i       : unsigned(19 downto 0):="00000000000000000000";
+  signal cal_Limit   : unsigned(19 downto 0):="00011000011010100000";--"00011000011010100000";
+
+  --type array2D is array (0 to 15, 0 to 64) of std_logic_vector(19 downto 0); --(FPGA)(channel)
+  --signal def_value   : array2D := (others => (others => "10000000000000010011")); --max: 512  ;  min: 19
+  signal def_value   : std_logic_vector(19 downto 0) := "10000000000000010011";   --max: 512  ;  min: 19
+  
+  type bit_2D is array (15 downto 0, 63 downto 0) of std_logic; --(channel)
+  --signal dflt_i      : bit_2D := (others => (others => '1'));
+ 
+  type tLocalBuffer is array ( (locBufDepth-1) downto 0) of std_logic_vector(31 downto 0); --(Flag [31])(reserved [30] )(FPGA [29:26])(channel [25:20])(Max [19:10])(Min [9:0])
+  signal EBRcntr     : tLocalBuffer := (others =>(others => '0'));
+  signal EBRbufCurr  : tLocalBuffer := (others =>(others => '0'));
+  signal EBRbufNext  : tLocalBuffer := (others =>(x"3FF00"&b"00" & b"11" & x"FF"));
+  
+  signal DIN_r         : std_logic_vector(31 downto 0);
+  signal DIN_ready_r   : std_logic;
+  signal DIN_type_r    : std_logic_vector( 3 downto 0);
+  signal min_curr_in_r : std_logic_vector( 9 downto 0);
+  signal max_curr_in_r : std_logic_vector( 9 downto 0);
+  signal min_next_in_r : std_logic_vector( 9 downto 0):= "1111111111";
+  signal max_next_in_r : std_logic_vector( 9 downto 0):= "0000000000";
+  signal FPGA_r        : std_logic_vector( 3 downto 0):= "0000";
+  signal chnl_r        : std_logic_vector( 6 downto 0);
+  signal Do_Cal_in_r   : std_logic;
+  signal stop_Limits_r : std_logic;
+  signal DIN_info_r    : std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0);
+  
+  signal max_default,min_default : std_logic_vector( 9 downto 0);
+  signal write_default : std_logic;
+  signal min_out       : std_logic_vector( 9 downto 0);
+  signal max_out       : std_logic_vector( 9 downto 0);
+  signal min_curr      : std_logic_vector( 9 downto 0);
+  signal max_curr      : std_logic_vector( 9 downto 0);
+  signal write_curr    : std_logic;
+  signal first_reset    : std_logic := '1';
+  
+begin
+
+  Limit : process (CLK)
+  begin
+  if rising_edge(CLK) then 
+    if (cal_Limit_reg <= cal_Limit_gen) then
+      cal_Limit     <= cal_Limit_gen;
+      cal_Limit_set <= cal_Limit_gen;
+    else
+      cal_Limit     <= cal_Limit_reg;
+      cal_Limit_set <= cal_Limit_reg;
+    end if;
+  end if;
+  end process;
+
+  Count : process (CLK)
+  variable cnt_v : unsigned (19 downto 0);
+  begin
+  if rising_edge(CLK) then
+    if (RESET = '1') then
+       --Reset behaviour
+       if first_reset = '1' then
+         --dflt_i      <= (others => (others => '1'));
+         first_reset <= '0';
+       end if; 
+
+    else
+      cnt_v := chnl_cnt_in;
+
+           
+      if (Flash_flag = '1') and (BUS_Flash_value(19 downto 0) /= x"00000") then
+          --dflt_i(to_integer(unsigned(BUS_Flash_value( 30 downto  27))),to_integer(unsigned(BUS_Flash_value( 26 downto  20)))) <= '0'; 
+      end if;
+      
+      for i in 0 to (locBufDepth-1) loop
+        if (EBRcntr(i)(31) = '1') and (EBRcntr(i)(29 downto 26) = FPGA) and (EBRcntr(i)(25 downto 20) = chnl(5 downto 0)) then
+          cnt_v := unsigned(EBRcntr(i)(19 downto  0));
+        end if;
+      end loop;
+
+      for i in 0 to (locBufDepth-2) loop
+        EBRcntr(i) <= EBRcntr(i+1);
+      end loop;
+    
+      if ((Do_Cal_in = '1') and (stop_Limits = '0')) then
+        if cnt_v < cal_Limit then
+          cnt_v := cnt_v + 1;
+        else
+          cnt_v := to_unsigned(0,20);
+          --dflt_i(to_integer(unsigned(FPGA)),to_integer(unsigned(chnl))) <= '0';
+        end if;
+        write_chnl_cnt  <= '1';
+        chnl_cnt_out    <= cnt_v;
+        cnt_i           <= cnt_v;
+        EBRcntr(locBufDepth-1) <= "10" & FPGA & chnl(5 downto 0) & std_logic_vector(cnt_v);
+      else
+        write_chnl_cnt  <= '0';
+        chnl_cnt_out <= x"00000";
+        EBRcntr(locBufDepth-1) <= x"00000000";
+      end if;
+
+    end if;--reset|no calibration
+          
+    --sync following processes with cnt_i
+    fpga_r            <= FPGA;
+    chnl_r            <= chnl;
+    DIN_r             <= DIN;
+    DIN_ready_r       <= DIN_ready;
+    DIN_type_r        <= DIN_type;
+    min_curr_in_r     <= min_curr_in;
+    max_curr_in_r     <= max_curr_in;
+    min_next_in_r     <= min_next_in;
+    max_next_in_r     <= max_next_in;
+    Do_Cal_in_r       <= Do_Cal_in;
+    stop_Limits_r     <= stop_Limits;
+    DIN_info_r        <= DIN_info;
+    cnt_i_debug       <= cnt_i; 
+  end if;
+  end process;
+   
+   
+  THE_Mem : process(CLK)
+    variable EBRCurr_Min_v  : std_logic_vector(9 downto 0):= "1111111111";
+    variable EBRCurr_Max_v  : std_logic_vector(9 downto 0):= "0000000000";
+    variable EBRNext_Min_v  : std_logic_vector(9 downto 0):= "1111111111";
+    variable EBRNext_Max_v  : std_logic_vector(9 downto 0):= "0000000000";
+    variable use_default    : std_logic := '1';
+  begin
+  if rising_edge(CLK) then
+    if (RESET = '1') then
+       --Reset behaviour      
+    else
+      --------- Current Values -----------------------------
+      EBRCurr_Min_v := min_curr_in_r;
+      EBRCurr_Max_v := max_curr_in_r;
+      
+      if ((min_curr_in_r = "0000000000") or (min_curr_in_r = "1111111111")) and
+         ((max_curr_in_r = "0000000000") or (max_curr_in_r = "1111111111")) 
+      then
+        use_default := '1';
+      else
+        use_default := '0';
+      end if;
+
+      for i in 0 to (locBufDepth-1) loop
+        if (EBRbufCurr(i)(31) = '1') and (EBRbufCurr(i)(29 downto 26) = FPGA_r) and (EBRbufCurr(i)(25 downto 20) = chnl_r(5 downto 0)) then
+          EBRCurr_Min_v := EBRbufCurr(i)( 9 downto  0);
+          EBRCurr_Max_v := EBRbufCurr(i)(19 downto 10);
+        end if;
+      end loop;
+
+      for i in 0 to (locBufDepth-2) loop
+        EBRbufCurr(i) <= EBRbufCurr(i+1);
+      end loop;
+      
+      --------- Next Values -----------------------------
+      EBRNext_Min_v := min_next_in_r;
+      EBRNext_Max_v := max_next_in_r;
+      
+      for i in 0 to (locBufDepth-1) loop
+        if (EBRbufNext(i)(31) = '1') and (EBRbufNext(i)(29 downto 26) = FPGA_r) and (EBRbufNext(i)(25 downto 20) = chnl_r(5 downto 0)) then
+          EBRNext_Min_v := EBRbufNext(i)( 9 downto  0);
+          EBRNext_Max_v := EBRbufNext(i)(19 downto 10);
+        end if;
+      end loop;
+
+      for i in 0 to (locBufDepth-2) loop
+        EBRbufNext(i) <= EBRbufNext(i+1);
+      end loop;
+
+
+      --------------------------------------------------------------
+      --------------------------  CURRENT  -------------------------
+      --------------------------------------------------------------
+      --if dflt_i(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r))) = '0' then
+      if use_default = '0' then
+        if Do_Cal_in_r = '1' then
+          if cnt_i /= to_unsigned(0,20) then
+            min_out <= EBRCurr_Min_v;
+            max_out <= EBRCurr_Max_v;
+            if (unsigned(EBRCurr_Min_v) < unsigned(EBRCurr_Max_v)) then
+              Delta_i <= std_logic_vector(unsigned(EBRCurr_Max_v) - unsigned(EBRCurr_Min_v));
+            else
+              Delta_i <= "0110110100";
+            end if;
+            min_curr <= EBRCurr_Min_v;
+            max_curr <= EBRCurr_Max_v;
+            write_curr <= '0';
+            EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & EBRCurr_Max_v & EBRCurr_Min_v;
+          else 
+            min_out     <= EBRNext_Min_v;
+            max_out     <= EBRNext_Max_v;
+            min_curr    <= EBRNext_Min_v;
+            max_curr    <= EBRNext_Max_v;
+            if (unsigned(EBRNext_Min_v) < unsigned(EBRNext_Max_v)) then
+              Delta_i <= std_logic_vector(unsigned(EBRNext_Max_v) - unsigned(EBRNext_Min_v));
+            else
+              Delta_i <= "0110110100";
+            end if;  
+            write_curr <= '1';
+            EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & EBRNext_Max_v & EBRNext_Min_v;
+          end if;
+        else -- no calibr
+          write_curr  <= '0';
+          write_next  <= '0';
+          EBRbufNext(locBufDepth-1) <= x"00000000";
+          EBRbufCurr(locBufDepth-1) <= x"00000000";
+        end if;
+      elsif use_default = '1' then
+      --FLASH
+        if Do_Cal_in_r = '1' then
+          write_curr <= '1';
+          min_out    <= def_value( 9 downto  0);
+          max_out    <= def_value(19 downto 10);
+          min_curr   <= def_value( 9 downto  0);
+          max_curr   <= def_value(19 downto 10);
+          Delta_i    <= std_logic_vector(unsigned(def_value(19 downto 10)) - unsigned(def_value(9 downto 0)));
+          EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & def_value(19 downto 10) & def_value( 9 downto 0);
+        else
+          write_curr <= '0';
+          --min_out    <= b"0000000000";
+          --max_out    <= b"0000000000";
+          --min_curr   <= b"0000000000";  --commented at 2019-04-09; may work still, bur without 0 at beginning in Monitoring
+          --max_curr   <= b"0000000000";  --commented at 2019-04-09; may work still, bur without 0 at beginning in Monitoring
+          Delta_i    <= b"0000000000";
+          EBRbufCurr(locBufDepth-1) <= x"00000000";
+        end if;
+      else
+        write_curr <= '0';
+        min_out    <= "0000000100";
+        max_out    <= "1000000000";
+        min_curr   <= "0000000100";
+        max_curr   <= "1000000000";
+        Delta_i    <= "0111111011";--"0111111110";
+        if Do_Cal_in_r = '1' then
+          write_curr <= '1';
+          EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & "1000000000" & "0000000100";
+        else
+          EBRbufCurr(locBufDepth-1) <= x"00000000";
+        end if;
+      end if;--default value
+
+
+      --------------------------------------------------------------
+      -----------------------------  NEXT  -------------------------
+      --------------------------------------------------------------
+      if ((Do_Cal_in_r = '1') and (stop_Limits_r = '0')) then
+        write_next  <= '1';
+        if cnt_i /= to_unsigned(0,20) then --next memory
+          if unsigned(DIN_r(21 downto 12)) >= unsigned(EBRNext_Max_v) then
+            EBRNext_Max_v := DIN_r(21 downto 12);
+            Debug_Data_max <= DIN_r;
+            if unsigned(DIN_r(21 downto 12)) < unsigned(EBRNext_Min_v) then
+              EBRNext_Min_v := DIN_r(21 downto 12);
+              Debug_Data_min <= DIN_r;
+            end if; 
+          else
+            if unsigned(DIN_r(21 downto 12)) < unsigned(EBRNext_Min_v) then
+              EBRNext_Min_v := DIN_r(21 downto 12);
+              Debug_Data_min <= DIN_r;
+            end if; 
+          end if;
+        else
+          EBRNext_Min_v  := DIN_r(21 downto 12);--"1111111111";
+          EBRNext_Max_v  := DIN_r(21 downto 12);--"0000000000";
+        end if; --/= 0
+        EBRbufNext(locBufDepth-1)<= "10" & FPGA_r & chnl_r(5 downto 0) & EBRNext_Max_v & EBRNext_Min_v;
+        min_next    <= EBRNext_Min_v;
+        max_next    <= EBRNext_Max_v;
+      else -- no calib
+        write_next  <= '0';
+        min_next    <= "1010101010";
+        max_next    <= "0101010101";
+        EBRbufNext(locBufDepth-1) <= (x"3FF00"&b"00" & b"11" & x"FF");
+      end if;
+    end if; -- reset| Calibration
+  end if;--rising_edge
+  end process;
+ 
+ 
+  write_curr_out <= write_curr or write_default;
+  min_curr_out   <= min_default when write_default = '1' else
+                    min_curr;
+  min_out_out    <= min_default when write_default = '1' else
+                    min_out;
+  max_curr_out   <= max_default when write_default = '1' else
+                    max_curr;
+  max_out_out    <= max_default when write_default = '1' else
+                    max_out;
+
+  dflt_out       <= "0000";--dflt_i(0,3)&dflt_i(0,2)&dflt_i(0,1)&dflt_i(0,0);
+ 
+  --synchronous output
+  proc_slope : process (CLK)
+  begin
+  if rising_edge(CLK) then
+    DOUT           <= DIN_r;
+    DOUT_ready     <= DIN_ready_r;
+    DOUT_type      <= DIN_type_r;
+    DOUT_info      <= DIN_info_r;
+    Do_Cal_out     <= Do_Cal_in_r;
+    chnl_out_write <= chnl_r;
+    FPGA_out_write <= fpga_r;
+    FPGA_out       <= fpga_r;
+    if Flash_flag = '1' then     
+      if BUS_Flash_value(19 downto 0) = x"00000" then
+          write_default <= '0';--'1';
+      else
+          write_default <= '1';--'1';
+          --dflt_i(to_integer(unsigned(BUS_Flash_value( 30 downto  27))),to_integer(unsigned(BUS_Flash_value( 26 downto  20)))) <= '0'; 
+      end if;
+      min_default    <= BUS_Flash_value( 9 downto  0);
+      max_default    <= BUS_Flash_value(19 downto 10);
+      FPGA_out_curr  <= BUS_Flash_value( 30 downto  27); -- fpga number from Flash
+      chnl_out       <= BUS_Flash_value( 26 downto  20);
+      chnl_out_curr  <= BUS_Flash_value( 26 downto  20);
+    else 
+      FPGA_out_curr  <= fpga_r;
+      chnl_out       <= chnl_r;
+      chnl_out_curr  <= chnl_r;
+    end if;
+   
+  end if;
+  end process;
+  
+  chnl_out_write_cnt <= chnl_r;
+  FPGA_out_write_cnt <= fpga_r;
+  Delta              <= Delta_i;
+end Behavioral;

diff --git a/combiner_cts/combiner.lpf b/combiner_cts/combiner.lpf
index 4bda532255e0476509fe86a9fa545e967fa97a7c..bfd632900b0fd2fb202629d25f739de8ac3b1f96 100644 (file)
--- a/combiner_cts/combiner.lpf
+++ b/combiner_cts/combiner.lpf
@@ -9,8 +9,11 @@ FREQUENCY PORT CLOCK_PLL 200 MHz;
 FREQUENCY PORT CLOCK_PCLK 200 MHz;
 
 
-FREQUENCY NET "THE_MEDIA*/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps 
-FREQUENCY NET "THE_MEDIA*/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps 
+FREQUENCY NET "THE_MEDIA_4*/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps
+FREQUENCY NET "THE_MEDIA_4*/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps
+
+FREQUENCY NET "THE_MEDIA_INTERFACE*/clk_rx_full" 240 MHz; # HOLD_MARGIN 500 ps
+FREQUENCY NET "THE_MEDIA_INTERFACE*/clk_tx_full" 240 MHz; # HOLD_MARGIN 500 ps
 
 #BLOCK PATH FROM CELL THE_TDC/calibration_o*;
 BLOCK PATH FROM CELL THE_CTS/TIME_REFERENCE_OUT TO CELL THE_TDC/ReferenceChannel/Channel200/SimAdderNo.FC/FF*;

diff --git a/combiner_cts/combiner.prj b/combiner_cts/combiner.prj
index 7b434cd196c17f1e14eff239f8fc1d8164f4f1b6..e1ecf1d3102be4e5256b6d46424174f60e2f4024 100644 (file)
--- a/combiner_cts/combiner.prj
+++ b/combiner_cts/combiner.prj
@@ -266,7 +266,7 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp3/PLL/pll_in240_out50.vhd"
 
 #TDC Calibration
 add_file -vhdl -lib work "./code_EBR/Calibration.vhd"
-add_file -vhdl -lib work "./code_EBR/Cal_Limits_v2.vhd"
+add_file -vhdl -lib work "./code_EBR/Cal_Limits_v2_1.vhd"
 add_file -vhdl -lib work "./code_EBR/cnt_val.vhd"
 add_file -vhdl -lib work "./code_EBR/default_val.vhd"
 add_file -vhdl -lib work "./code_EBR/LUT.vhd"

diff --git a/combiner_cts/combiner.vhd b/combiner_cts/combiner.vhd
index 516241e157728463f097f9dd5b4e3b54ce583a87..840ccb0098e47954a0d800ceb3094e4601b689ef 100644 (file)
--- a/combiner_cts/combiner.vhd
+++ b/combiner_cts/combiner.vhd
@@ -413,8 +413,9 @@ THE_MEDIA_INTERFACE : entity work.med_ecp3_sfp_sync_240
 
 THE_MEDIA_4_DOWN_A : entity work.med_ecp3_sfp_sync_4
   generic map(
-    IS_SYNC_SLAVE   => (c_NO, c_NO, c_NO, c_NO),
-    IS_USED         => (c_YES,c_YES,c_YES,c_YES)
+    IS_SYNC_SLAVE      => (c_NO, c_NO, c_NO, c_NO),
+--    USE_RETRANSMISSION => USE_RETRANSMISSION,
+    IS_USED            => (c_YES,c_YES,c_YES,c_YES)
     )
   port map(
     CLK_REF_FULL       => clk_full_osc, --med2int(0).clk_full,
@@ -465,8 +466,9 @@ THE_MEDIA_4_DOWN_A : entity work.med_ecp3_sfp_sync_4
 
 THE_MEDIA_4_DOWN_B : entity work.med_ecp3_sfp_sync_4
   generic map(
-    IS_SYNC_SLAVE   => (c_NO, c_NO, c_NO, c_NO),
-    IS_USED         => (c_YES,c_YES,c_YES,c_YES)
+    IS_SYNC_SLAVE      => (c_NO, c_NO, c_NO, c_NO),
+--    USE_RETRANSMISSION => USE_RETRANSMISSION,
+    IS_USED            => (c_YES,c_YES,c_YES,c_YES)
     )
   port map(
     CLK_REF_FULL       => clk_full_osc, --med2int(0).clk_full,
@@ -517,8 +519,9 @@ THE_MEDIA_4_DOWN_B : entity work.med_ecp3_sfp_sync_4
 
 THE_MEDIA_4_DOWN_D : entity work.med_ecp3_sfp_sync_4
   generic map(
-    IS_SYNC_SLAVE   => (c_NO, c_NO, c_NO, c_NO),
-    IS_USED         => (c_YES,c_YES,c_YES,c_YES)
+    IS_SYNC_SLAVE      => (c_NO, c_NO, c_NO, c_NO),
+--    USE_RETRANSMISSION => USE_RETRANSMISSION,
+    IS_USED            => (c_YES,c_YES,c_YES,c_YES)
     )
   port map(
     CLK_REF_FULL       => clk_full_osc, --med2int(0).clk_full,

diff --git a/combiner_cts/config.vhd b/combiner_cts/config.vhd
index 2c6fc1c58daf2a90b5e55a861d99e0aa455f81fa..ffcf10c94ad40d5f9994a126f1bcd93065721f47 100644 (file)
--- a/combiner_cts/config.vhd
+++ b/combiner_cts/config.vhd
@@ -48,14 +48,17 @@ package config is
     constant INCLUDE_TDC            : integer  := c_YES;  -- IMPORTANT: TDC part into entity has to be commented in/out by hand
                                                           --            (no generic possible due to constraints naming)
     constant INCLUDE_TRIGGER_LOGIC  : integer  := c_NO;
-    constant INCLUDE_STATISTICS     : integer  := c_YES;
+    constant INCLUDE_STATISTICS     : integer  := c_NO;
     constant TRIG_GEN_INPUT_NUM     : integer  := 0;
     constant TRIG_GEN_OUTPUT_NUM    : integer  := 0;
     constant MONITOR_INPUT_NUM      : integer  := 32;
 
     constant INCLUDE_GBE            : integer  := c_NO;
    
-    
+    --Retransmission
+    constant USE_RETRANSMISSION     : integer  := c_NO;
+
+
     constant GEN_BUSY_OUTPUT : integer := c_NO;
     
     constant TRIGGER_COIN_COUNT      : integer := 1;

diff --git a/combiner_cts/par.p2t b/combiner_cts/par.p2t
index c251db6369b801a5e39c11e52ab40cb1a6f1e9f9..e1df63aa8f935e615fbe8383933cff91ce9e74f4 100644 (file)
--- a/combiner_cts/par.p2t
+++ b/combiner_cts/par.p2t
@@ -4,7 +4,8 @@
 -n 1
 -y
 -s 12
--t 42
+#-t 42
+-t 22
 -c 1
 -e 2
 #-g guidefile.ncd