initial commit

diff --git a/.gitignore b/.gitignore
new file mode 100644 (file)
index 0000000..5aaed8d
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,34 @@
+*~
+*.tcl
+*.log
+*.rpt
+netlists
+version.vhd
+*.jhd
+*.naf
+*.sort
+*.srp
+*.sym
+*tmpl.vhd
+*.log
+workdir
+workdir_*
+*.bit
+*.kate-swp*
+*.kate-swap*
+.run_manager.ini
+reportview.xml
+.kateproject.d
+*/project/
+*/project2/
+modelsim.ini
+*.mti
+*.bak
+work
+*.wlf
+*stacktrace.txt
+*edn
+licbug.txt
+old
+config_compile.pl
+._Real_._Math_.vhd
\ No newline at end of file

diff --git a/testbench/tb.vhd b/testbench/tb.vhd
new file mode 100644 (file)
index 0000000..1624c85
--- /dev/null
+++ b/testbench/tb.vhd
@@ -0,0 +1,86 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+  
+library work;
+  use work.trb_net_std.all;
+
+entity tb is
+end entity;
+
+
+architecture arch of tb is
+
+component trigger_logic 
+  generic(
+    INPUTS  : integer := 32;
+    OUTPUTS : integer := 32
+    );
+  port(
+    CLK      : in std_logic;
+    RESET    : in std_logic;
+    
+    --Slowcontrol
+    BUS_RX     : in  CTRLBUS_RX;
+    BUS_TX     : out CTRLBUS_TX;
+    
+    --Inputs and Outputs
+    INPUT  : in  std_logic_vector(INPUTS-1 downto 0);
+    OUTPUT : out std_logic_vector(OUTPUTS-1 downto 0)
+    );
+end component;
+
+
+
+signal CLK : std_logic := '1';
+
+signal inputs : std_logic_vector(31 downto 0);
+
+signal BUS_RX : CTRLBUS_RX;
+signal BUS_TX : CTRLBUS_TX;
+
+
+begin
+
+CLK <= not CLK after 5 ns;
+
+
+PROC_INIT_REGISTERS : process begin
+  BUS_RX.write <= '0';
+  BUS_RX.read <= '0';
+  wait for 100 ns;
+  wait until rising_edge(CLK); wait for 1 ns;
+  BUS_RX.write <= '1'; BUS_RX.addr <= x"0000"; BUS_RX.data <= x"0000FFFF";
+  wait until rising_edge(CLK); wait for 1 ns;
+  BUS_RX.write <= '0';
+  wait;
+end process;
+
+
+PROC_INPUTS : process begin
+  inputs <= (others => '0');
+  wait for 500 ns;
+  wait for 24 ns;
+  inputs <= x"00000001";
+  wait for 27 ns;
+  inputs <= x"00000000";
+end process;
+
+
+THE_LOGIC : trigger_logic 
+  generic map(
+    INPUTS => 32,
+    OUTPUTS => 32
+    )
+  port map(
+    CLK => CLK,
+    RESET => '0',
+    BUS_RX => BUS_RX,
+    BUS_TX => open,
+    INPUT  => inputs,
+    OUTPUT => open
+    );
+
+
+
+end architecture;

diff --git a/trigger_logic.vhd b/trigger_logic.vhd
new file mode 100644 (file)
index 0000000..5ae4259
--- /dev/null
+++ b/trigger_logic.vhd
@@ -0,0 +1,68 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+  
+library work;
+  use work.trb_net_std.all;
+  
+entity trigger_logic is
+  generic(
+    INPUTS  : integer := 32;
+    OUTPUTS : integer := 32
+    );
+  port(
+    CLK      : in std_logic;
+    RESET    : in std_logic;
+    
+    --Slowcontrol
+    BUS_RX     : in  CTRLBUS_RX;
+    BUS_TX     : out CTRLBUS_TX;
+    
+    --Inputs and Outputs
+    INPUT  : in  std_logic_vector(INPUTS-1 downto 0);
+    OUTPUT : out std_logic_vector(OUTPUTS-1 downto 0)
+    );
+end entity;
+
+
+
+architecture arch of trigger_logic is
+
+--Registers
+signal REG_ENABLE : std_logic_vector(31 downto 0);
+
+begin
+
+
+
+
+---------------------------------------------------------------------------
+-- Registers
+---------------------------------------------------------------------------
+THE_REGS : process begin
+  wait until rising_edge(CLK);
+  BUS_TX.ack     <= '0';
+  BUS_TX.nack    <= '0';
+  BUS_TX.unknown <= '0';
+  
+  if BUS_RX.read = '1' then
+    BUS_TX.ack <= '1';
+    case BUS_RX.addr(7 downto 0) is
+      when x"00" =>  BUS_TX.data <= REG_ENABLE;
+      when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
+    end case;
+    
+  elsif BUS_RX.write = '1' then
+    BUS_TX.ack <= '1';
+    case BUS_RX.addr(7 downto 0) is
+      when x"00" => REG_ENABLE <= BUS_RX.data;
+      when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1';
+    end case;
+  end if;
+  
+end process;
+
+
+
+
+end architecture;