--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.trb_net_std.all;
+
+
+entity ffarray is
+ port(
+ CLK : in std_logic;
+ RESET_IN : in std_logic;
+ SIGNAL_IN : in std_logic;
+
+ DATA_OUT : out std_logic_vector(8 downto 0);
+ READ_IN : in std_logic := '0';
+ EMPTY_OUT : out std_logic := '0'
+ );
+end entity;
+
+architecture ffarray_arch of ffarray is
+
+attribute syn_hier : string;
+attribute syn_hier of ffarray_arch : architecture is "hard";
+
+signal CLKt : std_logic_vector(3 downto 0);
+signal CLKa : std_logic_vector(7 downto 0);
+
+signal final1, final2 : std_logic_vector(7 downto 0);
+signal final_t : std_logic_vector(7 downto 0);
+signal final : std_logic_vector(8 downto 0);
+type ffarr_t is array(0 to 3) of std_logic_vector(7 downto 0);
+signal ffarr : ffarr_t;
+
+type ram_t is array(0 to 1023) of std_logic_vector(7 downto 0);
+signal ram : ram_t;
+
+signal fifo_write, last : std_logic;
+
+
+ attribute syn_preserve : boolean;
+ attribute syn_keep : boolean;
+
+ attribute syn_preserve of CLKa : signal is true;
+ attribute syn_keep of CLKa : signal is true;
+ attribute syn_preserve of CLKt : signal is true;
+ attribute syn_keep of CLKt : signal is true;
+
+
+begin
+
+THE_PLL : entity work.pll_4x266
+ port map(
+ CLKI => CLK,
+ CLKOP => CLKt(0),
+ CLKOS => CLKt(1),
+ CLKOS2 => CLKt(2),
+ CLKOS3 => CLKt(3)
+ );
+
+CLKa(3 downto 0) <= CLKt(3 downto 0);
+CLKa(7 downto 4) <= not CLKt(3 downto 0);
+
+gen_ffarr_first : for i in 0 to 7 generate
+ ffarr(0)(i) <= SIGNAL_IN when rising_edge(CLKa(i));
+ ffarr(1)(i) <= ffarr(0)(i) when rising_edge(CLKa((i/4)*4));
+ ffarr(2)(i) <= ffarr(1)(i) when rising_edge(CLKa(0));
+end generate;
+
+process begin
+ wait until falling_edge(CLK);
+ final_t <= ffarr(2);
+end process;
+
+
+process begin
+ wait until rising_edge(CLK);
+ final1 <= final_t;
+ final2 <= ffarr(2);
+ last <= final2(7);
+ if (final1(7) xor last) = '1' then
+ fifo_write <= '1';
+ final <= final1 & last;
+ elsif (final2(7) xor final1(7)) = '1' then
+ fifo_write <= '1';
+ final <= final2 & final1(7);
+ else
+ fifo_write <= '0';
+ end if;
+end process;
+
+
+THE_FIFO : entity work.fifo_9x2k_oreg
+ port map(
+ Data => final,
+ WrClock => CLK,
+ RdClock => CLK,
+ WrEn => fifo_write,
+ RdEn => READ_IN,
+ Reset => RESET_IN,
+ RPReset => RESET_IN,
+ Q => DATA_OUT,
+ Empty => EMPTY_OUT,
+ Full => open,
+ AlmostEmpty => open,
+ AlmostFull => open
+ );
+
+end architecture;
\ No newline at end of file
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<DiamondModule name="pll_4x266" module="PLL" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2016 04 05 17:14:33.785" version="5.8" type="Module" synthesis="synplify" source_format="VHDL">
+ <Package>
+ <File name="pll_4x266.lpc" type="lpc" modified="2016 04 05 17:14:32.000"/>
+ <File name="pll_4x266.vhd" type="top_level_vhdl" modified="2016 04 05 17:14:32.000"/>
+ <File name="pll_4x266_tmpl.vhd" type="template_vhdl" modified="2016 04 05 17:14:32.000"/>
+ </Package>
+</DiamondModule>
--- /dev/null
+[Device]
+Family=machxo3lf
+PartType=LCMXO3LF-2100E
+PartName=LCMXO3LF-2100E-5UWG49CTR
+SpeedGrade=5
+Package=WLCSP49
+OperatingCondition=COM
+Status=S
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=PLL
+CoreRevision=5.8
+ModuleName=pll_4x266
+SourceFormat=VHDL
+ParameterFileVersion=1.0
+Date=04/05/2016
+Time=17:14:32
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=None
+Order=None
+IO=0
+mode=Frequency
+CLKI=125
+CLKI_DIV=1
+BW=10.504
+VCO=500.000
+fb_mode=INT_OP
+CLKFB_DIV=2
+FRACN_ENABLE=0
+FRACN_DIV=0
+DynamicPhase=STATIC
+ClkEnable=0
+Standby=0
+Enable_sel=0
+PLLRst=0
+PLLMRst=0
+ClkOS2Rst=0
+ClkOS3Rst=0
+LockSig=0
+LockStk=0
+WBProt=0
+OPBypass=0
+OPUseDiv=0
+CLKOP_DIV=2
+FREQ_PIN_CLKOP=250
+OP_Tol=1.0
+CLKOP_AFREQ=250.000000
+CLKOP_PHASEADJ=0
+CLKOP_TRIM_POL=Rising
+CLKOP_TRIM_DELAY=0
+EnCLKOS=1
+OSBypass=0
+OSUseDiv=0
+CLKOS_DIV=2
+FREQ_PIN_CLKOS=250
+OS_Tol=0.0
+CLKOS_AFREQ=250.000000
+CLKOS_PHASEADJ=45
+CLKOS_TRIM_POL=Rising
+CLKOS_TRIM_DELAY=0
+EnCLKOS2=1
+OS2Bypass=0
+OS2UseDiv=0
+CLKOS2_DIV=2
+FREQ_PIN_CLKOS2=250
+OS2_Tol=0.0
+CLKOS2_AFREQ=250.000000
+CLKOS2_PHASEADJ=90
+EnCLKOS3=1
+OS3Bypass=0
+OS3UseDiv=0
+CLKOS3_DIV=2
+FREQ_PIN_CLKOS3=250
+OS3_Tol=0.0
+CLKOS3_AFREQ=250.000000
+CLKOS3_PHASEADJ=135
+
+[Command]
+cmd_line= -w -n pll_4x266 -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 125 -fclkop 250 -fclkop_tol 1.0 -fclkos 250 -fclkos_tol 0.0 -fclkos2 250 -fclkos2_tol 0.0 -fclkos3 250 -fclkos3_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 45 -trims_r -phases2 90 -phases3 135 -phase_cntl STATIC -fb_mode 5
--- /dev/null
+-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.7.0.96.1
+-- Module Version: 5.7
+--/d/jspc29/lattice/diamond/3.7_x64/ispfpga/bin/lin64/scuba -w -n pll_4x266 -lang vhdl -synth synplify -arch xo3c00f -type pll -fin 125 -fclkop 250 -fclkop_tol 1.0 -fclkos 250 -fclkos_tol 0.0 -fclkos2 250 -fclkos2_tol 0.0 -fclkos3 250 -fclkos3_tol 0.0 -trimp 0 -phasep 0 -trimp_r -trims 0 -phases 45 -trims_r -phases2 90 -phases3 135 -phase_cntl STATIC -fb_mode 5
+
+-- Tue Apr 5 17:14:32 2016
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library MACHXO3L;
+use MACHXO3L.components.all;
+-- synopsys translate_on
+
+entity pll_4x266 is
+ port (
+ CLKI: in std_logic;
+ CLKOP: out std_logic;
+ CLKOS: out std_logic;
+ CLKOS2: out std_logic;
+ CLKOS3: out std_logic);
+end pll_4x266;
+
+architecture Structure of pll_4x266 is
+
+ -- internal signal declarations
+ signal LOCK: std_logic;
+ signal CLKOS3_t: std_logic;
+ signal CLKOS2_t: std_logic;
+ signal CLKOS_t: std_logic;
+ signal CLKOP_t: std_logic;
+ signal CLKFB_t: std_logic;
+ signal scuba_vlo: std_logic;
+
+ -- local component declarations
+ component VLO
+ port (Z: out std_logic);
+ end component;
+ component EHXPLLJ
+ generic (INTFB_WAKE : in String; DDRST_ENA : in String;
+ DCRST_ENA : in String; MRST_ENA : in String;
+ PLLRST_ENA : in String; DPHASE_SOURCE : in String;
+ STDBY_ENABLE : in String; OUTDIVIDER_MUXD2 : in String;
+ OUTDIVIDER_MUXC2 : in String;
+ OUTDIVIDER_MUXB2 : in String;
+ OUTDIVIDER_MUXA2 : in String;
+ PREDIVIDER_MUXD1 : in Integer;
+ PREDIVIDER_MUXC1 : in Integer;
+ PREDIVIDER_MUXB1 : in Integer;
+ PREDIVIDER_MUXA1 : in Integer; PLL_USE_WB : in String;
+ PLL_LOCK_MODE : in Integer;
+ CLKOS_TRIM_DELAY : in Integer;
+ CLKOS_TRIM_POL : in String;
+ CLKOP_TRIM_DELAY : in Integer;
+ CLKOP_TRIM_POL : in String; FRACN_DIV : in Integer;
+ FRACN_ENABLE : in String; FEEDBK_PATH : in String;
+ CLKOS3_FPHASE : in Integer; CLKOS2_FPHASE : in Integer;
+ CLKOS_FPHASE : in Integer; CLKOP_FPHASE : in Integer;
+ CLKOS3_CPHASE : in Integer; CLKOS2_CPHASE : in Integer;
+ CLKOS_CPHASE : in Integer; CLKOP_CPHASE : in Integer;
+ VCO_BYPASS_D0 : in String; VCO_BYPASS_C0 : in String;
+ VCO_BYPASS_B0 : in String; VCO_BYPASS_A0 : in String;
+ CLKOS3_ENABLE : in String; CLKOS2_ENABLE : in String;
+ CLKOS_ENABLE : in String; CLKOP_ENABLE : in String;
+ CLKOS3_DIV : in Integer; CLKOS2_DIV : in Integer;
+ CLKOS_DIV : in Integer; CLKOP_DIV : in Integer;
+ CLKFB_DIV : in Integer; CLKI_DIV : in Integer);
+ port (CLKI: in std_logic; CLKFB: in std_logic;
+ PHASESEL1: in std_logic; PHASESEL0: in std_logic;
+ PHASEDIR: in std_logic; PHASESTEP: in std_logic;
+ LOADREG: in std_logic; STDBY: in std_logic;
+ PLLWAKESYNC: in std_logic; RST: in std_logic;
+ RESETM: in std_logic; RESETC: in std_logic;
+ RESETD: in std_logic; ENCLKOP: in std_logic;
+ ENCLKOS: in std_logic; ENCLKOS2: in std_logic;
+ ENCLKOS3: in std_logic; PLLCLK: in std_logic;
+ PLLRST: in std_logic; PLLSTB: in std_logic;
+ PLLWE: in std_logic; PLLADDR4: in std_logic;
+ PLLADDR3: in std_logic; PLLADDR2: in std_logic;
+ PLLADDR1: in std_logic; PLLADDR0: in std_logic;
+ PLLDATI7: in std_logic; PLLDATI6: in std_logic;
+ PLLDATI5: in std_logic; PLLDATI4: in std_logic;
+ PLLDATI3: in std_logic; PLLDATI2: in std_logic;
+ PLLDATI1: in std_logic; PLLDATI0: in std_logic;
+ CLKOP: out std_logic; CLKOS: out std_logic;
+ CLKOS2: out std_logic; CLKOS3: out std_logic;
+ LOCK: out std_logic; INTLOCK: out std_logic;
+ REFCLK: out std_logic; CLKINTFB: out std_logic;
+ DPHSRC: out std_logic; PLLACK: out std_logic;
+ PLLDATO7: out std_logic; PLLDATO6: out std_logic;
+ PLLDATO5: out std_logic; PLLDATO4: out std_logic;
+ PLLDATO3: out std_logic; PLLDATO2: out std_logic;
+ PLLDATO1: out std_logic; PLLDATO0: out std_logic);
+ end component;
+ attribute FREQUENCY_PIN_CLKOS3 : string;
+ attribute FREQUENCY_PIN_CLKOS2 : string;
+ attribute FREQUENCY_PIN_CLKOS : string;
+ attribute FREQUENCY_PIN_CLKOP : string;
+ attribute FREQUENCY_PIN_CLKI : string;
+ attribute ICP_CURRENT : string;
+ attribute LPF_RESISTOR : string;
+ attribute FREQUENCY_PIN_CLKOS3 of PLLInst_0 : label is "250.000000";
+ attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "250.000000";
+ attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "250.000000";
+ attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "250.000000";
+ attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "125.000000";
+ attribute ICP_CURRENT of PLLInst_0 : label is "10";
+ attribute LPF_RESISTOR of PLLInst_0 : label is "24";
+ attribute syn_keep : boolean;
+ attribute NGD_DRC_MASK : integer;
+ attribute NGD_DRC_MASK of Structure : architecture is 1;
+
+begin
+ -- component instantiation statements
+ scuba_vlo_inst: VLO
+ port map (Z=>scuba_vlo);
+
+ PLLInst_0: EHXPLLJ
+ generic map (DDRST_ENA=> "DISABLED", DCRST_ENA=> "DISABLED",
+ MRST_ENA=> "DISABLED", PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED",
+ STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED",
+ PLL_USE_WB=> "DISABLED", CLKOS3_FPHASE=> 6, CLKOS3_CPHASE=> 1,
+ CLKOS2_FPHASE=> 4, CLKOS2_CPHASE=> 1, CLKOS_FPHASE=> 2,
+ CLKOS_CPHASE=> 1, CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 1,
+ PLL_LOCK_MODE=> 0, CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING",
+ CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", FRACN_DIV=> 0,
+ FRACN_ENABLE=> "DISABLED", OUTDIVIDER_MUXD2=> "DIVD",
+ PREDIVIDER_MUXD1=> 0, VCO_BYPASS_D0=> "DISABLED", CLKOS3_ENABLE=> "ENABLED",
+ OUTDIVIDER_MUXC2=> "DIVC", PREDIVIDER_MUXC1=> 0, VCO_BYPASS_C0=> "DISABLED",
+ CLKOS2_ENABLE=> "ENABLED", OUTDIVIDER_MUXB2=> "DIVB",
+ PREDIVIDER_MUXB1=> 0, VCO_BYPASS_B0=> "DISABLED", CLKOS_ENABLE=> "ENABLED",
+ OUTDIVIDER_MUXA2=> "DIVA", PREDIVIDER_MUXA1=> 0, VCO_BYPASS_A0=> "DISABLED",
+ CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 2, CLKOS2_DIV=> 2,
+ CLKOS_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 2, CLKI_DIV=> 1,
+ FEEDBK_PATH=> "INT_DIVA")
+ port map (CLKI=>CLKI, CLKFB=>CLKFB_t, PHASESEL1=>scuba_vlo,
+ PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo,
+ PHASESTEP=>scuba_vlo, LOADREG=>scuba_vlo, STDBY=>scuba_vlo,
+ PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, RESETM=>scuba_vlo,
+ RESETC=>scuba_vlo, RESETD=>scuba_vlo, ENCLKOP=>scuba_vlo,
+ ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo,
+ PLLCLK=>scuba_vlo, PLLRST=>scuba_vlo, PLLSTB=>scuba_vlo,
+ PLLWE=>scuba_vlo, PLLADDR4=>scuba_vlo, PLLADDR3=>scuba_vlo,
+ PLLADDR2=>scuba_vlo, PLLADDR1=>scuba_vlo,
+ PLLADDR0=>scuba_vlo, PLLDATI7=>scuba_vlo,
+ PLLDATI6=>scuba_vlo, PLLDATI5=>scuba_vlo,
+ PLLDATI4=>scuba_vlo, PLLDATI3=>scuba_vlo,
+ PLLDATI2=>scuba_vlo, PLLDATI1=>scuba_vlo,
+ PLLDATI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t,
+ CLKOS2=>CLKOS2_t, CLKOS3=>CLKOS3_t, LOCK=>LOCK,
+ INTLOCK=>open, REFCLK=>open, CLKINTFB=>CLKFB_t, DPHSRC=>open,
+ PLLACK=>open, PLLDATO7=>open, PLLDATO6=>open, PLLDATO5=>open,
+ PLLDATO4=>open, PLLDATO3=>open, PLLDATO2=>open,
+ PLLDATO1=>open, PLLDATO0=>open);
+
+ CLKOS3 <= CLKOS3_t;
+ CLKOS2 <= CLKOS2_t;
+ CLKOS <= CLKOS_t;
+ CLKOP <= CLKOP_t;
+end Structure;
+
+-- synopsys translate_off
+library MACHXO3L;
+configuration Structure_CON of pll_4x266 is
+ for Structure
+ for all:VLO use entity MACHXO3L.VLO(V); end for;
+ for all:EHXPLLJ use entity MACHXO3L.EHXPLLJ(V); end for;
+ end for;
+end Structure_CON;
+
+-- synopsys translate_on
--- /dev/null
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+SYSCONFIG MCCLK_FREQ=133 BACKGROUND_RECONFIG=ON ENABLE_TRANSFR=ENABLE JTAG_PORT=DISABLE MUX_CONFIGURATION_PORTS=ENABLE ;
+LOCATE COMP "LVDS[1]" SITE "A6" ;
+# LOCATE COMP "OUTPUT[3]" SITE "C5" ;
+LOCATE COMP "LVDS[0]" SITE "B4" ;
+# LOCATE COMP "OUTPUT[1]" SITE "B5" ;
+LOCATE COMP "CONTROLI" SITE "B1" ;
+LOCATE COMP "CONTROLO" SITE "A1" ;
+LOCATE COMP "LED[0]" SITE "A7" ;
+LOCATE COMP "LED[1]" SITE "E5" ;
+LOCATE COMP "LED[2]" SITE "C1" ;
+LOCATE COMP "LED[3]" SITE "B2" ;
+LOCATE COMP "DEBUG[0]" SITE "F7" ;
+LOCATE COMP "DEBUG[2]" SITE "G7" ;
+LOCATE COMP "DEBUG[3]" SITE "F4" ;
+LOCATE COMP "DEBUG[1]" SITE "F3" ;
+LOCATE COMP "RX_OUT" SITE "F1" ;
+LOCATE COMP "TX_IN" SITE "C4" ;
+LOCATE COMP "CBUS" SITE "C3" ;
+LOCATE COMP "CLK" SITE "G4" ;
+LOCATE COMP "STATUSO" SITE "G2" ;
+LOCATE COMP "STATUSI" SITE "G1" ;
+IOBUF PORT "DEBUG[0]" IO_TYPE=LVTTL33 ;
+IOBUF PORT "DEBUG[1]" IO_TYPE=LVTTL33 ;
+IOBUF PORT "DEBUG[2]" IO_TYPE=LVTTL33 ;
+IOBUF PORT "DEBUG[3]" IO_TYPE=LVTTL33 ;
+IOBUF PORT "CONTROLI" IO_TYPE=LVTTL33 ;
+IOBUF PORT "CONTROLO" IO_TYPE=LVTTL33 ;
+IOBUF PORT "LED[0]" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "LED[1]" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "LED[2]" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "LED[3]" IO_TYPE=LVTTL33 PULLMODE=NONE ;
+IOBUF PORT "LVDS[0]" IO_TYPE=LVDS25 ;
+IOBUF PORT "LVDS[1]" IO_TYPE=LVDS25 ;
+IOBUF PORT "RX_OUT" IO_TYPE=LVTTL33 ;
+IOBUF PORT "TX_IN" IO_TYPE=LVTTL33 ;
+IOBUF PORT "CBUS" IO_TYPE=LVTTL33 ;
+IOBUF PORT "CLK" IO_TYPE=LVDS25 ;
+IOBUF PORT "STATUSO" IO_TYPE=LVTTL33 ;
+IOBUF PORT "STATUSI" IO_TYPE=LVTTL33 PULLMODE=DOWN;
+BANK 0 VCCIO 3.3 V;
+BANK 5 VCCIO 3.3 V;
+BANK 2 VCCIO 3.3 V;
+
+
+FREQUENCY PORT CLK 125 MHz;
+FREQUENCY NET clk_osc 133 MHz;
\ No newline at end of file
--- /dev/null
+../../trb3sc/scripts/compile.pl
\ No newline at end of file
--- /dev/null
+Familyname => 'MachXO3LF',
+Devicename => 'LCMXO3LF-2100E',
+Package => 'WLCSP49',
+Speedgrade => '5',
+
+TOPNAME => "testtdc",
+lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de";
+lm_license_file_for_par => "1702\@hadeb05.gsi.de",
+lattice_path => '/d/jspc29/lattice/diamond/3.7_x64',
+#synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/',
+ synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options",
+# synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp",
+# synplify_command => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #",
+nodelist_file => 'nodelist_frankfurt.txt',
+
+
+#Include only necessary lpf files
+#pinout_file => '', #name of pin-out file, if not equal TOPNAME
+include_TDC => 0,
+include_GBE => 0,
+
+#Report settings
+firefox_open => 0,
+twr_number_of_errors => 20,
+no_ltxt2ptxt => 1, #if there is no serdes being used
+make_jed => 1,
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<BaliProject version="3.2" title="L" device="LCMXO3LF-2100E-5UWG49CTR" default_implementation="L">
+ <Options/>
+ <Implementation title="L" dir="L" description="L" synthesis="synplify" default_strategy="Strategy1">
+ <Options def_top="uart_sctrl" top="logicbox"/>
+ <Source name="../testtdc.vhd" type="VHDL" type_short="VHDL">
+ <Options top_module="logicbox"/>
+ </Source>
+ <Source name="../../../trbnet/special/uart_rec.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/special/uart_trans.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../padiwa/amps/version.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/trb_net_std.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../code/sedcheck.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../code/uart_sctrl.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="L/L.xcf" type="Programming Project File" type_short="Programming">
+ <Options/>
+ </Source>
+
+ <Source name="../../pinout/testtdc.lpf" type="Logic Preference" type_short="LPF">
+ <Options/>
+ </Source>
+
+ <Source name="../../cores/pll_4x266.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../code/ffarray.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+ <Source name="../../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd" type="VHDL" type_short="VHDL">
+ <Options/>
+ </Source>
+
+ </Implementation>
+ <Strategy name="Strategy1" file="LogicBox1.sty"/>
+</BaliProject>
--- /dev/null
+-w
+-i 15
+-l 5
+-n 1
+-y
+-s 12
+-t 1
+-c 1
+-e 2
+#-g guidefile.ncd
+#-m nodelist.txt
+# -w
+# -i 6
+# -l 5
+# -n 1
+# -t 1
+# -s 1
+# -c 0
+# -e 0
+#
+-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1
--- /dev/null
+#!/usr/bin/perl
+
+use strict;
+use warnings;
+use Device::SerialPort;
+use feature 'state';
+use URI::Escape;
+use Data::Dumper;
+use HADES::TrbNet;
+use Time::HiRes qw( usleep);
+use Getopt::Long;
+
+
+my @counters;
+my $port;
+my $help;
+my $ser_dev;
+my $isTrbNet = 0;
+Getopt::Long::Configure(qw(gnu_getopt));
+GetOptions(
+ 'help|h' => \$help,
+ 'device|d=s' => \$ser_dev,
+ ) ;
+
+
+$ser_dev = "/dev/ttyUSB0" unless defined $ser_dev;
+
+
+sub Cmd {
+ my ($c) = @_;
+ if($isTrbNet == 0) {
+ $port->write($c."\r\n");
+ for my $j (0..10) {
+ my ($l,$s) = $port->read(11);
+ if ($l < 11) {next;}
+ if ($s =~ /^R[A-Fa-f0-9]{8}/) {return hex(substr($s,1,8));}
+ usleep(1000);
+ }
+ }
+# else {
+# trb_register_read_mem($ser_dev,0xd600,1,100); #clear memory
+# my @c = split('',$c."\n");
+# my @cmd = map(ord, @c);
+# trb_register_write_mem($ser_dev,0xd600,1,\@cmd,scalar @cmd);
+# usleep(20000);
+# my $r = trb_register_read_mem($ser_dev,0xd600,1,5);
+# my $s = join('',map (chr($_ & 0xff),@{$r->{$ser_dev}}));
+# if ($s =~ /^\w[a-f0-9]{3}/) {return hex(substr($s,1,3));}
+# if ($s =~ /^\w[a-f0-9]{2}/) {return hex(substr($s,1,2));}
+# }
+ return 0xdeaddead;
+ }
+
+if ($help || (defined $ARGV[0] && $ARGV[0] =~ /help/)) {
+ exit;
+ }
+
+
+$SIG{"INT"} = \&finish;
+$SIG{"QUIT"} = \&stats;
+
+sub finish{
+ stats();
+ exit;
+}
+
+sub stats{
+ print "----------------------\n";
+ my @sum;
+ for(my $i=0; $i < 512; $i++){
+ if ($counters[$i]) {
+ $sum[$i/256] += $counters[$i];
+ }
+ }
+ for(my $i=0; $i < 512; $i++){
+ if ($counters[$i]) {
+ printf("%03x\t%i\t%i\n",$i,$counters[$i], $counters[$i]/$sum[$i/256]*1000000/266)
+ }
+ }
+ print ("$sum[0] $sum[1]\n");
+ print "----------------------\n";
+ }
+
+
+ $port = new Device::SerialPort($ser_dev);
+ unless ($port) {
+ print "can't open serial interface $ser_dev\n";
+ exit;
+ }
+ $port->user_msg('ON');
+ $port->baudrate(115200);
+ $port->parity("none");
+ $port->databits(8);
+ $port->stopbits(1);
+ $port->handshake("none");
+ $port->read_char_time(0);
+ $port->read_const_time(50);
+ $port->write_settings;
+
+
+
+while(1) {
+ usleep(1000);
+ my $v = Cmd("R80");
+# printf("%08x\n",$v);
+ if ($v & 0x10000000) {next;}
+ $counters[$v&0x1ff]++;
+
+ }
+
+
--- /dev/null
+UGROUP "ffarr0group"
+ BLKNAME THE_TDC/ffarr[0]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[0][1]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[0][2]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[0][3]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[0][4]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[0][5]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[0][6]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[0][7]
+ ;
+
+UGROUP "ffarr12group"
+ BLKNAME THE_TDC/ffarr[1]
+ BLKNAME THE_TDC/ffarr[2]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[1][1]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[2][1]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[1][2]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[2][2]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[1][3]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[2][3]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[1][4]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[2][4]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[1][5]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[2][5]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[1][6]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[2][6]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[1][7]
+ BLKNAME THE_TDC/gen_ffarr_first.0.ffarr[2][7]
+ ;
+
+
+REGION "FFARR0" "R2C15" 1 4 DEVSIZE;
+REGION "FFARR12" "R2C17" 1 2 DEVSIZE;
+LOCATE UGROUP "ffarr0group" REGION "FFARR0";
+LOCATE UGROUP "ffarr12group" REGION "FFARR12";
+
+USE PRIMARY NET "THE_TDC/CLKa*";
+USE PRIMARY NET "THE_TDC_CLKa*";
+USE PRIMARY NET "THE_TDC/CLKa[0]";
+USE PRIMARY NET "THE_TDC/CLKa[1]";
+USE PRIMARY NET "THE_TDC/CLKa[2]";
+USE PRIMARY NET "THE_TDC/CLKa[3]";
+USE PRIMARY NET "THE_TDC_CLKa[0]";
+USE PRIMARY NET "THE_TDC_CLKa[1]";
+USE PRIMARY NET "THE_TDC_CLKa[2]";
+USE PRIMARY NET "THE_TDC_CLKa[3]";
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
--- /dev/null
+#-- Synopsys, Inc.
+#-- Version J-2015.03L-SP1
+#-- Project file /d/jspc22/trb/git/LogicBox/diamond/LogicBox/run_options.txt
+
+#project files
+
+add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesis/vhdl/machxo3lf.vhd"
+
+add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd"
+add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
+add_file -vhdl -lib work "../code/uart_sctrl.vhd"
+add_file -vhdl -lib work "../code/sedcheck.vhd"
+add_file -vhdl -lib work "../cores/pll_4x266.vhd"
+add_file -vhdl -lib work "../code/ffarray.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
+add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
+add_file -vhdl -lib work "testtdc.vhd"
+
+
+
+#implementation: "LogicBox"
+impl -add workdir -type fpga
+
+#
+#implementation attributes
+
+set_option -vlog_std v2001
+set_option -project_relative_includes 1
+
+#par_1 attributes
+set_option -job par_1 -add par
+
+#device options
+set_option -technology MACHXO3LF
+set_option -part LCMXO3LF_2100E
+set_option -package UWG49CTR
+set_option -speed_grade -5
+set_option -part_companion ""
+
+#compilation/mapping options
+set_option -top_module "logicbox"
+
+# mapper_options
+set_option -frequency 1
+set_option -write_verilog 0
+set_option -write_vhdl 0
+set_option -srs_instrumentation 1
+
+# Lattice XP
+set_option -maxfan 1000
+set_option -disable_io_insertion 0
+set_option -retiming 0
+set_option -pipe 1
+set_option -forcegsr false
+set_option -fix_gated_and_generated_clocks 1
+set_option -rw_check_on_ram 1
+set_option -update_models_cp 0
+set_option -syn_edif_array_rename 1
+set_option -Write_declared_clocks_only 1
+
+# sequential_optimization_options
+set_option -symbolic_fsm_compiler 1
+
+# Compiler Options
+set_option -compiler_compatible 0
+set_option -resource_sharing 1
+set_option -multi_file_compilation_unit 1
+
+# Compiler Options
+set_option -auto_infer_blackbox 0
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+#set result format/file last
+project -result_format "edif"
+project -result_file "workdir/testtdc.edf"
+
+#set log file
+set_option log_file "workdir/testtdc.srf"
+impl -active "workdir"
--- /dev/null
+library ieee;\r
+use ieee.std_logic_1164.all;\r
+use ieee.numeric_std.all;\r
+\r
+library machxo3lf;\r
+use machxo3lf.all;\r
+\r
+library work;\r
+use work.trb_net_std.all;\r
+\r
+entity logicbox is\r
+ port(\r
+ CLK : in std_logic;\r
+ \r
+ DEBUG : out std_logic_vector(3 downto 0);\r
+ LVDS : in std_logic_vector(1 downto 0);\r
+ \r
+ LED : inout std_logic_vector(3 downto 0);\r
+ \r
+ STATUSI : in std_logic;\r
+ STATUSO : in std_logic;\r
+ CONTROLI : out std_logic;\r
+ CONTROLO : out std_logic;\r
+ \r
+ RX_OUT : out std_logic;\r
+ TX_IN : in std_logic;\r
+ CBUS : in std_logic\r
+ );\r
+end entity;\r
+\r
+architecture arch of logicbox is\r
+ signal clk_i, clk_osc : std_logic;\r
+ signal clk_p : std_logic_vector(3 downto 0);\r
+ signal led_i : std_logic_vector(3 downto 0);\r
+ signal timer_i : unsigned(31 downto 0) := (others => '0');\r
+ signal config : std_logic_vector(3 downto 0);\r
+ signal led_highz : std_logic;\r
+ \r
+ type led_timer_t is array(0 to 3) of unsigned(24 downto 0);\r
+ signal led_timer : led_timer_t;\r
+ signal led_state : std_logic_vector(3 downto 0);\r
+ \r
+ signal uart_rx_data : std_logic_vector(31 downto 0);\r
+ signal uart_tx_data : std_logic_vector(31 downto 0);\r
+ signal uart_addr : std_logic_vector(7 downto 0);\r
+ signal bus_read : std_logic := '0';\r
+ signal bus_write : std_logic := '0';\r
+ signal bus_ready : std_logic; \r
+ \r
+ signal input_i : std_logic_vector(3 downto 0);\r
+ signal input_selected : std_logic_vector(3 downto 0); \r
+ signal input_stretched, input_hold : std_logic_vector(3 downto 0);\r
+ signal input_reg_0, input_reg_1, input_reg_2 : std_logic_vector(3 downto 0);\r
+ \r
+ signal edge_rising, edge_falling : std_logic_vector(3 downto 0);\r
+ signal pulser : std_logic;\r
+ signal reg : std_logic_vector(31 downto 0);\r
+ signal last_config : std_logic_vector(3 downto 0);\r
+ \r
+ signal sed_error : std_logic;\r
+ signal sed_debug : std_logic_vector(31 downto 0);\r
+ signal controlsed_i : std_logic_vector(3 downto 0);\r
+ \r
+ signal f_read, f_empty : std_logic;\r
+ signal f_data : std_logic_vector(8 downto 0);\r
+ \r
+ component OSCH\r
+ generic (NOM_FREQ: string := "133.00");\r
+ port (\r
+ STDBY :IN std_logic;\r
+ OSC :OUT std_logic;\r
+ SEDSTDBY :OUT std_logic\r
+ );\r
+ end component; \r
+ \r
+begin\r
+\r
+input_selected <= '0' & '0' & LVDS(1) & LVDS(0);\r
+\r
+input_hold <= input_selected or (input_hold and not input_reg_0);\r
+\r
+input_reg_0 <= input_selected or input_hold when rising_edge(clk_i);\r
+input_reg_1 <= input_reg_0 when rising_edge(clk_i);\r
+input_reg_2 <= input_reg_1 when rising_edge(clk_i);\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- LED\r
+---------------------------------------------------------------------------\r
+ PROC_LED : process begin\r
+ wait until rising_edge(clk_i);\r
+ if not (config = last_config) and timer_i(27) = '0' then\r
+ led_i <= config; \r
+ elsif STATUSI = '0' then\r
+ led_i <= led_state;\r
+ else\r
+ led_i <= led_state(2) & led_state(3) & led_state(0) & led_state(1);\r
+ end if; \r
+ end process;\r
+\r
+ PROC_LED_STATE : process begin\r
+ wait until rising_edge(clk_i);\r
+ for i in 0 to 2 loop\r
+ if (input_reg_2(i) xor input_reg_1(i)) = '1' and (led_timer(i)(23 downto 21) > 0) then\r
+ led_state(i) <= not led_state(i);\r
+ led_timer(i) <= 0;\r
+ elsif led_timer(i)(23) = '1' then\r
+ led_state(i) <= input_reg_1(i);\r
+ else\r
+ led_timer(i) <= led_timer(i) + 1;\r
+ end if;\r
+ end loop;\r
+ end process; \r
+ \r
+ \r
+---------------------------------------------------------------------------\r
+-- Clock\r
+---------------------------------------------------------------------------\r
+clk_source: OSCH\r
+ generic map ( NOM_FREQ => "133" )\r
+ port map (\r
+ STDBY => '0',\r
+ OSC => clk_osc,\r
+ SEDSTDBY => open\r
+ );\r
+clk_i <= CLK;\r
+\r
+timer_i <= timer_i + 1 when rising_edge(clk_i);\r
+\r
+\r
+\r
+\r
+---------------------------------------------------------------------------\r
+-- Read configuration switch\r
+---------------------------------------------------------------------------\r
+process begin\r
+ wait until rising_edge(clk_i);\r
+ \r
+\r
+ if timer_i(27 downto 10) = 0 then\r
+ led_highz <= '1';\r
+ last_config <= config;\r
+ if timer_i(9 downto 0) = "11"&x"ff" then\r
+ config <= not LED;\r
+ end if;\r
+ else\r
+ led_highz <= '0';\r
+ end if;\r
+end process; \r
+\r
+LED <= led_i when led_highz = '0' else "ZZZZ";\r
+-- LED <= sed_debug(3 downto 0);\r
+\r
+---------------------------------------------------------------------------\r
+-- UART\r
+---------------------------------------------------------------------------\r
+THE_UART : entity work.uart_sctrl\r
+ generic map(\r
+ CLOCK_SPEED => 125000000\r
+ )\r
+ port map(\r
+ CLK => clk_i,\r
+ RESET => '0',\r
+ UART_RX => TX_IN,\r
+ UART_TX => RX_OUT,\r
+ \r
+ DATA_OUT => uart_rx_data,\r
+ DATA_IN => uart_tx_data,\r
+ ADDR_OUT => uart_addr, \r
+ WRITE_OUT => bus_write,\r
+ READ_OUT => bus_read,\r
+ READY_IN => bus_ready,\r
+ \r
+ DEBUG => open\r
+ );\r
+\r
+\r
+PROC_REGS : process begin\r
+ wait until rising_edge(clk_i);\r
+ bus_ready <= '0';\r
+ f_read <= '0';\r
+ if bus_read = '1' then\r
+ bus_ready <= '1';\r
+ case uart_addr is\r
+ when x"00" => uart_tx_data <= x"0000000" & config;\r
+ when x"10" => uart_tx_data <= reg;\r
+ when x"80" => \r
+ f_read <= '1';\r
+ uart_tx_data <= "000" & f_empty & x"0000" & "000" & f_data;\r
+ when x"ee" => uart_tx_data <= sed_debug;\r
+ end case;\r
+ elsif bus_write = '1' then\r
+ case uart_addr is\r
+ when x"10" => reg <= uart_rx_data;\r
+ when x"ee" => controlsed_i <= uart_rx_data(3 downto 0);\r
+ end case;\r
+ end if;\r
+end process;\r
+\r
+\r
+THE_SED : entity work.sedcheck\r
+ port map(\r
+ CLK => clk_i,\r
+ ERROR_OUT => sed_error,\r
+ \r
+ CONTROL_IN => controlsed_i,\r
+ DEBUG => sed_debug\r
+ );\r
+\r
+ \r
+---------------------------------------------------------------------------\r
+-- LVDS\r
+--------------------------------------------------------------------------- \r
+\r
+THE_TDC : entity work.ffarray\r
+ port map(\r
+ CLK => clk_i,\r
+ RESET_IN => '0',\r
+ SIGNAL_IN => LVDS(0),\r
+ \r
+ DATA_OUT => f_data,\r
+ READ_IN => f_read,\r
+ EMPTY_OUT => f_empty\r
+ );\r
+\r
+\r
+DEBUG <= '0' & '0' & LVDS(1) & LVDS(0);\r
+\r
+\r
+end architecture;\r
+\r
+ \r
+
\ No newline at end of file
jspc29 / logicbox.git / commitdiff