$o .= "<font style=\"color:red\" title=\"for output 1\">".(($d->{0} & (1<<($i*4+$s)))?'➊':'◻')."</font> ";
$o .= "<font style=\"color:blue\" title=\"for output 2\">".(($d->{4} & (1<<($i*4+$s)))?'➋':'◻')."</font><br>";
$o .= "<font style=\"color:orange\" title=\"for output 3\">".(($d->{8} & (1<<($i*4+$s)))?'➌':'◻')."</font> ";
+ $o .= "<font style=\"color:purple\" title=\"for output 4\">".(($d->{12} & (1<<($i*4+$s)))?'➍':'◻')."</font> ";
$o .= "<font style=\"color:#0a0\" title=\"for mult\">".(($d->{0x33} & (1<<($i*4+$s)))?'◼':'◻')."</font><br>";
}
return $o;
$out .= sprintf("<tr class=\"master\"><td>0x%4x<td colspan=\"2\"><td colspan=\"2\"><td colspan=\"2\"><td colspan=\"2\"><td>",$b);
if ($data->{$boards->[0]}{0x33} != 0) {
$out .= "mult >=".(($data->{$boards->[0]}{0x32} >> 16)&0xFF)." ";
- $out .= "<font style=\"color:red\" title=\"for output 1\">".(($data->{$b}{0x34} & (1 << 8))?'◼':'◻')."</font> ";
- $out .= "<font style=\"color:blue\" title=\"for output 2\">".(($data->{$b}{0x34} & (9 << 9))?'◼':'◻')."</font> ";
-# $out .= sprintf("on outputs %04b",($data->{$b}{0x34} >> 8));
+ $out .= "<font style=\"color:red\" title=\"for output 1\">".(($data->{$b}{0x34} & (1 << 8))?'➊':'◻')."</font> ";
+ $out .= "<font style=\"color:blue\" title=\"for output 2\">".(($data->{$b}{0x34} & (1 << 9))?'➋':'◻')."</font> ";
+ $out .= "<font style=\"color:orange\" title=\"for output 3\">".(($data->{$b}{0x34} & (1 << 10))?'➌':'◻')."</font> ";
+ $out .= "<font style=\"color:purple\" title=\"for output 4\">".(($data->{$b}{0x34} & (1 << 11))?'➍':'◻')."</font> ";
+ # $out .= sprintf("on outputs %04b",($data->{$b}{0x34} >> 8));
}
$out .= "</table>";
- $out .= qq#<table><tr><th>Red<td>selected in 'or' for output 1 on central FPGA (TRG3)
- <tr><th>Blue<td>selected in 'or' for output 2 on central FPGA (CLK3)
- <tr><th>Orange<td>selected in 'or' for output 3 central FPGA (CLK4)
+ $out .= qq#<table>
+ <tr><th>Red<td>selected in 'or' for output 1 on central FPGA (TRG3)
+ <tr><th>Blue<td>selected in 'or' for output 2 on central FPGA (TRG4)
+ <tr><th>Orange<td>selected in 'or' for output 3 on central FPGA (CLK3)
+ <tr><th>Purple<td>selected in 'or' for output 4 central FPGA (CLK4)
<tr><th>Green<td>selected for multiplicity logic
<tr><th>Black<td>Enabled in 'or'
<tr><th>Generic<td>The generic tab only works for TRB3 central and TRB3sc crate master FPGA!
$page->{getscript} = "trigger.pl";
my @setup;
-
+
+push(@setup,({name => "Generic",
+ cmd => "getmap-0x8000",
+ period => -1,
+ address => 1,
+ norate => 1,
+ nocache => 1,}));
push(@setup,({name => "EC0",
cmd => "getmap-0x8a00",
period => -1,
noaddress => 1,
norate => 1,
nocache => 1,}));
-push(@setup,({name => "Generic",
- cmd => "getmap-0x8000",
- period => -1,
- address => 1,
- norate => 1,
- nocache => 1,}));
+
xmlpage::initPage(\@setup,$page);
}
<description>Select inputs 63-32 for multiplicity logic</description>
<field name="MultiplicityEnable2" start="0" bits="32" format="bitmask" noflag="true"/>
</register>
-
+ <register name="TriggerStretchSet" address="0036" mode="rw" >
+ <description>If available, adds this amount of length to each input signal. Used for coincidence and multiplicity</description>
+ <field name="TriggerStretchSet" start="0" bits="6" format="unsigned" unit="ns" scale="10" noflag="true"/>
+ </register>
<register name="Coincidence" address="0040" mode="rw" repeat="16">
<description>Coincidence Logic</description>
<field name="Enable" start="31" bits="1" format="bitmask" />